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https://github.com/brain-hackers/u-boot-brain
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pci: imx: Factor out hard-coded register base addresses
Pull out hard-coded register base addresses into driver private structure in preparation for DM conversion. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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@ -92,6 +92,18 @@
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#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
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#define PCIE_ATU_UPPER_TARGET 0x91C
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struct imx_pcie_priv {
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void __iomem *dbi_base;
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void __iomem *cfg_base;
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};
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static struct imx_pcie_priv imx_pcie_priv = {
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.dbi_base = (void __iomem *)MX6_DBI_ADDR,
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.cfg_base = (void __iomem *)MX6_ROOT_ADDR,
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};
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static struct imx_pcie_priv *priv = &imx_pcie_priv;
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/*
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* PHY access functions
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*/
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@ -231,7 +243,7 @@ static int imx6_pcie_link_up(void)
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int rx_valid, temp;
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/* link is debug bit 36, debug register 1 starts at bit 32 */
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rc = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1);
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rc = readl(priv->dbi_base + PCIE_PHY_DEBUG_R1);
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if ((rc & PCIE_PHY_DEBUG_R1_LINK_UP) &&
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!(rc & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING))
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return -EAGAIN;
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@ -243,8 +255,8 @@ static int imx6_pcie_link_up(void)
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* && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
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* to gen2 is stuck
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*/
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pcie_phy_read((void *)MX6_DBI_ADDR, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
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ltssm = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0) & 0x3F;
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pcie_phy_read(priv->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
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ltssm = readl(priv->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F;
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if (rx_valid & 0x01)
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return 0;
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@ -254,15 +266,15 @@ static int imx6_pcie_link_up(void)
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printf("transition to gen2 is stuck, reset PHY!\n");
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pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp);
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pcie_phy_read(priv->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
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temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
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pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp);
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pcie_phy_write(priv->dbi_base, PHY_RX_OVRD_IN_LO, temp);
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udelay(3000);
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pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp);
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pcie_phy_read(priv->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
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temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
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pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp);
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pcie_phy_write(priv->dbi_base, PHY_RX_OVRD_IN_LO, temp);
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return 0;
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}
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@ -285,24 +297,25 @@ static int imx_pcie_regions_setup(void)
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*/
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/* CMD reg:I/O space, MEM space, and Bus Master Enable */
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setbits_le32(MX6_DBI_ADDR | PCI_COMMAND,
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setbits_le32(priv->dbi_base + PCI_COMMAND,
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PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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/* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
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setbits_le32(MX6_DBI_ADDR + PCI_CLASS_REVISION,
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setbits_le32(priv->dbi_base + PCI_CLASS_REVISION,
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PCI_CLASS_BRIDGE_PCI << 16);
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/* Region #0 is used for Outbound CFG space access. */
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writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT);
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writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);
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writel(MX6_ROOT_ADDR, MX6_DBI_ADDR + PCIE_ATU_LOWER_BASE);
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writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_BASE);
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writel(MX6_ROOT_ADDR + MX6_ROOT_SIZE, MX6_DBI_ADDR + PCIE_ATU_LIMIT);
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writel((u32)priv->cfg_base, priv->dbi_base + PCIE_ATU_LOWER_BASE);
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writel(0, priv->dbi_base + PCIE_ATU_UPPER_BASE);
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writel((u32)priv->cfg_base + MX6_ROOT_SIZE,
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priv->dbi_base + PCIE_ATU_LIMIT);
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writel(0, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET);
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writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_TARGET);
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writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1);
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writel(PCIE_ATU_ENABLE, MX6_DBI_ADDR + PCIE_ATU_CR2);
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writel(0, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
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writel(0, priv->dbi_base + PCIE_ATU_UPPER_TARGET);
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writel(PCIE_ATU_TYPE_CFG0, priv->dbi_base + PCIE_ATU_CR1);
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writel(PCIE_ATU_ENABLE, priv->dbi_base + PCIE_ATU_CR2);
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return 0;
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}
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@ -315,18 +328,18 @@ static uint32_t get_bus_address(pci_dev_t d, int where)
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uint32_t va_address;
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/* Reconfigure Region #0 */
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writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT);
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writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);
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if (PCI_BUS(d) < 2)
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writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1);
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writel(PCIE_ATU_TYPE_CFG0, priv->dbi_base + PCIE_ATU_CR1);
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else
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writel(PCIE_ATU_TYPE_CFG1, MX6_DBI_ADDR + PCIE_ATU_CR1);
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writel(PCIE_ATU_TYPE_CFG1, priv->dbi_base + PCIE_ATU_CR1);
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if (PCI_BUS(d) == 0) {
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va_address = MX6_DBI_ADDR;
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va_address = (u32)priv->dbi_base;
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} else {
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writel(d << 8, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET);
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va_address = MX6_IO_ADDR + SZ_16M - SZ_1M;
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writel(d << 8, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
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va_address = (u32)priv->cfg_base;
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}
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va_address += (where & ~0x3);
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@ -465,12 +478,12 @@ static int imx6_pcie_assert_core_reset(bool prepare_for_boot)
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gpr12 = readl(&iomuxc_regs->gpr[12]);
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if ((gpr1 & IOMUXC_GPR1_PCIE_REF_CLK_EN) &&
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(gpr12 & IOMUXC_GPR12_PCIE_CTL_2)) {
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val = readl(MX6_DBI_ADDR + PCIE_PL_PFLR);
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val = readl(priv->dbi_base + PCIE_PL_PFLR);
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val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
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val |= PCIE_PL_PFLR_FORCE_LINK;
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imx_pcie_fix_dabt_handler(true);
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writel(val, MX6_DBI_ADDR + PCIE_PL_PFLR);
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writel(val, priv->dbi_base + PCIE_PL_PFLR);
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imx_pcie_fix_dabt_handler(false);
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gpr12 &= ~IOMUXC_GPR12_PCIE_CTL_2;
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@ -621,9 +634,9 @@ static int imx_pcie_link_up(void)
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* Force the PCIe RC subordinate to 0xff, otherwise no downstream
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* devices will be detected if the enumeration is applied strictly.
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*/
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tmp = readl(MX6_DBI_ADDR + 0x18);
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tmp = readl(priv->dbi_base + 0x18);
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tmp |= (0xff << 16);
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writel(tmp, MX6_DBI_ADDR + 0x18);
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writel(tmp, priv->dbi_base + 0x18);
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/*
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* FIXME: Force the PCIe RC to Gen1 operation
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@ -631,10 +644,10 @@ static int imx_pcie_link_up(void)
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* up, otherwise no downstream devices are detected. After the
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* link is up, a managed Gen1->Gen2 transition can be initiated.
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*/
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tmp = readl(MX6_DBI_ADDR + 0x7c);
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tmp = readl(priv->dbi_base + 0x7c);
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tmp &= ~0xf;
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tmp |= 0x1;
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writel(tmp, MX6_DBI_ADDR + 0x7c);
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writel(tmp, priv->dbi_base + 0x7c);
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/* LTSSM enable, starting link. */
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setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
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@ -647,8 +660,8 @@ static int imx_pcie_link_up(void)
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puts("PCI: pcie phy link never came up\n");
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#endif
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debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
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readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0),
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readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1));
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readl(priv->dbi_base + PCIE_PHY_DEBUG_R0),
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readl(priv->dbi_base + PCIE_PHY_DEBUG_R1));
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return -EINVAL;
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}
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}
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