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ram: rk3399: Add phy pctrl reset support
Add support for phy pctrl reset support for both channel 0, 1. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
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@ -35,6 +35,10 @@
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#define PHY_DRV_ODT_40 0xe
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#define PHY_DRV_ODT_40 0xe
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#define PHY_DRV_ODT_34_3 0xf
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#define PHY_DRV_ODT_34_3 0xf
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#define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \
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((n) << (8 + (ch) * 4)))
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#define CRU_SFTRST_DDR_PHY(ch, n) ((0x1 << (9 + 16 + (ch) * 4)) | \
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((n) << (9 + (ch) * 4)))
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struct chan_info {
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struct chan_info {
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struct rk3399_ddr_pctl_regs *pctl;
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struct rk3399_ddr_pctl_regs *pctl;
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struct rk3399_ddr_pi_regs *pi;
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struct rk3399_ddr_pi_regs *pi;
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@ -79,6 +83,29 @@ static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
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}
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}
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}
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}
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static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl,
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u32 phy)
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{
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channel &= 0x1;
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ctl &= 0x1;
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phy &= 0x1;
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writel(CRU_SFTRST_DDR_CTRL(channel, ctl) |
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CRU_SFTRST_DDR_PHY(channel, phy),
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&cru->softrst_con[4]);
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}
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static void phy_pctrl_reset(struct rk3399_cru *cru, u32 channel)
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{
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rkclk_ddr_reset(cru, channel, 1, 1);
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udelay(10);
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rkclk_ddr_reset(cru, channel, 1, 0);
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udelay(10);
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rkclk_ddr_reset(cru, channel, 0, 0);
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udelay(10);
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}
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static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs,
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static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs,
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u32 freq)
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u32 freq)
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{
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{
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@ -1129,6 +1156,7 @@ static int sdram_init(struct dram_info *dram,
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{
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{
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unsigned char dramtype = params->base.dramtype;
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unsigned char dramtype = params->base.dramtype;
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unsigned int ddr_freq = params->base.ddr_freq;
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unsigned int ddr_freq = params->base.ddr_freq;
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struct rk3399_cru *cru = dram->cru;
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int channel;
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int channel;
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int ret;
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int ret;
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@ -1145,6 +1173,7 @@ static int sdram_init(struct dram_info *dram,
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const struct chan_info *chan = &dram->chan[channel];
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const struct chan_info *chan = &dram->chan[channel];
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struct rk3399_ddr_publ_regs *publ = chan->publ;
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struct rk3399_ddr_publ_regs *publ = chan->publ;
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phy_pctrl_reset(cru, channel);
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phy_dll_bypass_set(publ, ddr_freq);
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phy_dll_bypass_set(publ, ddr_freq);
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if (channel >= params->base.num_channels)
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if (channel >= params->base.num_channels)
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