mirror of
https://github.com/brain-hackers/u-boot-brain
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fpga: virtex2: Split out image writing from pre/post operations
This is in preparation for adding slave serial programming support, which uses the same pre/post operations as slave SelectMAP, to avoid duplicating code. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
parent
25d63a3677
commit
3372081cfd
@ -154,204 +154,221 @@ static int virtex2_info(xilinx_desc *desc)
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* INIT_B and DONE lines. If both are high, configuration has
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* INIT_B and DONE lines. If both are high, configuration has
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* succeeded. Congratulations!
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* succeeded. Congratulations!
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*/
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*/
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static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
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static int virtex2_slave_pre(xilinx_virtex2_slave_selectmap_fns *fn, int cookie)
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{
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{
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int ret_val = FPGA_FAIL;
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unsigned long ts;
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xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns;
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PRINTF("%s:%d: Start with interface functions @ 0x%p\n",
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PRINTF("%s:%d: Start with interface functions @ 0x%p\n",
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__func__, __LINE__, fn);
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__func__, __LINE__, fn);
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if (fn) {
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if (!fn) {
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size_t bytecount = 0;
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printf("%s:%d: NULL Interface function table!\n",
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unsigned char *data = (unsigned char *)buf;
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__func__, __LINE__);
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int cookie = desc->cookie;
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return FPGA_FAIL;
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unsigned long ts;
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}
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/* Gotta split this one up (so the stack won't blow??) */
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/* Gotta split this one up (so the stack won't blow??) */
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PRINTF("%s:%d: Function Table:\n"
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PRINTF("%s:%d: Function Table:\n"
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" base 0x%p\n"
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" base 0x%p\n"
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" struct 0x%p\n"
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" struct 0x%p\n"
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" pre 0x%p\n"
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" pre 0x%p\n"
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" prog 0x%p\n"
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" prog 0x%p\n"
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" init 0x%p\n"
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" init 0x%p\n"
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" error 0x%p\n",
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" error 0x%p\n",
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__func__, __LINE__,
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__func__, __LINE__,
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&fn, fn, fn->pre, fn->pgm, fn->init, fn->err);
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&fn, fn, fn->pre, fn->pgm, fn->init, fn->err);
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PRINTF(" clock 0x%p\n"
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PRINTF(" clock 0x%p\n"
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" cs 0x%p\n"
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" cs 0x%p\n"
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" write 0x%p\n"
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" write 0x%p\n"
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" rdata 0x%p\n"
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" rdata 0x%p\n"
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" wdata 0x%p\n"
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" wdata 0x%p\n"
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" busy 0x%p\n"
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" busy 0x%p\n"
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" abort 0x%p\n"
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" abort 0x%p\n"
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" post 0x%p\n\n",
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" post 0x%p\n\n",
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fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata,
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fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata,
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fn->busy, fn->abort, fn->post);
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fn->busy, fn->abort, fn->post);
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
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printf("Initializing FPGA Device %d...\n", cookie);
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printf("Initializing FPGA Device %d...\n", cookie);
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#endif
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#endif
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/*
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/*
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* Run the pre configuration function if there is one.
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* Run the pre configuration function if there is one.
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*/
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*/
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if (*fn->pre)
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if (*fn->pre)
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(*fn->pre)(cookie);
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(*fn->pre)(cookie);
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/*
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/*
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* Assert the program line. The minimum pulse width for
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* Assert the program line. The minimum pulse width for
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* Virtex II devices is 300 nS (Tprogram parameter in
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* Virtex II devices is 300 nS (Tprogram parameter in datasheet).
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* datasheet). There is no maximum value for the pulse width.
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* There is no maximum value for the pulse width. Check to make
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* Check to make sure that INIT_B goes low after assertion of
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* sure that INIT_B goes low after assertion of PROG_B
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* PROG_B
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*/
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*/
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(*fn->pgm)(true, true, cookie);
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(*fn->pgm)(true, true, cookie);
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udelay(10);
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udelay(10);
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ts = get_timer(0);
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ts = get_timer(0);
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do {
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do {
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if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
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if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
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printf("%s:%d: ** Timeout after %d ticks waiting for INIT to assert.\n",
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printf("%s:%d: ** Timeout after %d ticks waiting for INIT to assert.\n",
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__func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT);
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__func__, __LINE__,
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(*fn->abort)(cookie);
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CONFIG_SYS_FPGA_WAIT_INIT);
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return FPGA_FAIL;
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(*fn->abort)(cookie);
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}
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return FPGA_FAIL;
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} while (!(*fn->init)(cookie));
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}
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} while (!(*fn->init)(cookie));
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(*fn->pgm)(false, true, cookie);
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(*fn->pgm)(false, true, cookie);
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CONFIG_FPGA_DELAY();
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CONFIG_FPGA_DELAY();
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if (fn->clk)
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(*fn->clk)(true, true, cookie);
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(*fn->clk)(true, true, cookie);
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/*
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/*
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* Start a timer and wait for INIT_B to go high
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* Start a timer and wait for INIT_B to go high
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*/
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*/
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ts = get_timer(0);
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ts = get_timer(0);
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do {
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do {
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CONFIG_FPGA_DELAY();
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CONFIG_FPGA_DELAY();
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if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
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if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
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printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n",
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printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n",
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__func__, __LINE__,
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__func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT);
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CONFIG_SYS_FPGA_WAIT_INIT);
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(*fn->abort)(cookie);
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(*fn->abort)(cookie);
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return FPGA_FAIL;
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return FPGA_FAIL;
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}
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}
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} while ((*fn->init)(cookie) && (*fn->busy)(cookie));
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} while ((*fn->init)(cookie) && (*fn->busy)(cookie));
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if (fn->wr)
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(*fn->wr)(true, true, cookie);
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(*fn->wr)(true, true, cookie);
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if (fn->cs)
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(*fn->cs)(true, true, cookie);
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(*fn->cs)(true, true, cookie);
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mdelay(10);
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mdelay(10);
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return FPGA_SUCCESS;
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}
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/*
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static int virtex2_slave_post(xilinx_virtex2_slave_selectmap_fns *fn,
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* Load the data byte by byte
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int cookie)
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*/
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{
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while (bytecount < bsize) {
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int ret_val = FPGA_SUCCESS;
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#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
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unsigned long ts;
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if (ctrlc()) {
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(*fn->abort)(cookie);
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return FPGA_FAIL;
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}
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#endif
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if ((*fn->done)(cookie) == FPGA_SUCCESS) {
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/*
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PRINTF("%s:%d:done went active early, bytecount = %d\n",
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* Finished writing the data; deassert FPGA CS_B and WRITE_B signals.
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__func__, __LINE__, bytecount);
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*/
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break;
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CONFIG_FPGA_DELAY();
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}
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if (fn->cs)
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#ifdef CONFIG_SYS_FPGA_CHECK_ERROR
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if ((*fn->init)(cookie)) {
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printf("\n%s:%d: ** Error: INIT asserted during configuration\n",
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__func__, __LINE__);
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printf("%d = buffer offset, %d = buffer size\n",
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bytecount, bsize);
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(*fn->abort)(cookie);
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return FPGA_FAIL;
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}
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#endif
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(*fn->wdata)(data[bytecount++], true, cookie);
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CONFIG_FPGA_DELAY();
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/*
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* Cycle the clock pin
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*/
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(*fn->clk)(false, true, cookie);
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CONFIG_FPGA_DELAY();
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(*fn->clk)(true, true, cookie);
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#ifdef CONFIG_SYS_FPGA_CHECK_BUSY
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ts = get_timer(0);
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while ((*fn->busy)(cookie)) {
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if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_BUSY) {
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printf("%s:%d: ** Timeout after %d ticks waiting for BUSY to deassert\n",
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__func__, __LINE__,
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CONFIG_SYS_FPGA_WAIT_BUSY);
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(*fn->abort)(cookie);
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return FPGA_FAIL;
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}
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}
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#endif
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
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if (bytecount % (bsize / 40) == 0)
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putc('.');
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#endif
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}
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/*
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* Finished writing the data; deassert FPGA CS_B and WRITE_B
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* signals.
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*/
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CONFIG_FPGA_DELAY();
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(*fn->cs)(false, true, cookie);
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(*fn->cs)(false, true, cookie);
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if (fn->wr)
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(*fn->wr)(false, true, cookie);
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(*fn->wr)(false, true, cookie);
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
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putc('\n');
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putc('\n');
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#endif
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#endif
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/*
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* Check for successful configuration. FPGA INIT_B and DONE
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* should both be high upon successful configuration.
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*/
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ts = get_timer(0);
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ret_val = FPGA_SUCCESS;
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while (((*fn->done)(cookie) == FPGA_FAIL) ||
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(*fn->init)(cookie)) {
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if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) {
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printf("%s:%d: ** Timeout after %d ticks waiting for DONE to assert and INIT to deassert\n",
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__func__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG);
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(*fn->abort)(cookie);
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ret_val = FPGA_FAIL;
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break;
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}
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}
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if (ret_val == FPGA_SUCCESS) {
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
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printf("Initialization of FPGA device %d complete\n", cookie);
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#endif
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/*
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/*
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* Check for successful configuration. FPGA INIT_B and DONE
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* Run the post configuration function if there is one.
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* should both be high upon successful configuration.
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*/
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*/
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ts = get_timer(0);
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if (*fn->post)
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ret_val = FPGA_SUCCESS;
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(*fn->post)(cookie);
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while (((*fn->done)(cookie) == FPGA_FAIL) ||
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(*fn->init)(cookie)) {
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if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) {
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printf("%s:%d: ** Timeout after %d ticks waiting for DONE toassert and INIT to deassert\n",
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__func__, __LINE__,
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CONFIG_SYS_FPGA_WAIT_CONFIG);
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(*fn->abort)(cookie);
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ret_val = FPGA_FAIL;
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break;
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}
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}
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if (ret_val == FPGA_SUCCESS) {
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
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printf("Initialization of FPGA device %d complete\n",
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cookie);
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#endif
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/*
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* Run the post configuration function if there is one.
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*/
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if (*fn->post)
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(*fn->post)(cookie);
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} else {
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
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printf("** Initialization of FPGA device %d FAILED\n",
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cookie);
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#endif
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}
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} else {
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} else {
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printf("%s:%d: NULL Interface function table!\n",
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
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__func__, __LINE__);
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printf("** Initialization of FPGA device %d FAILED\n",
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cookie);
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#endif
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}
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}
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return ret_val;
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return ret_val;
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}
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}
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static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
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{
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int ret_val = FPGA_FAIL;
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xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns;
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size_t bytecount = 0;
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unsigned char *data = (unsigned char *)buf;
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int cookie = desc->cookie;
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ret_val = virtex2_slave_pre(fn, cookie);
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if (ret_val != FPGA_SUCCESS)
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return ret_val;
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/*
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* Load the data byte by byte
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*/
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while (bytecount < bsize) {
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#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
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if (ctrlc()) {
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(*fn->abort)(cookie);
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return FPGA_FAIL;
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}
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#endif
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if ((*fn->done)(cookie) == FPGA_SUCCESS) {
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PRINTF("%s:%d:done went active early, bytecount = %d\n",
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__func__, __LINE__, bytecount);
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break;
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}
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#ifdef CONFIG_SYS_FPGA_CHECK_ERROR
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if ((*fn->init)(cookie)) {
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printf("\n%s:%d: ** Error: INIT asserted during configuration\n",
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__func__, __LINE__);
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printf("%zu = buffer offset, %zu = buffer size\n",
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bytecount, bsize);
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(*fn->abort)(cookie);
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return FPGA_FAIL;
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}
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#endif
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(*fn->wdata)(data[bytecount++], true, cookie);
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CONFIG_FPGA_DELAY();
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/*
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* Cycle the clock pin
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*/
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(*fn->clk)(false, true, cookie);
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CONFIG_FPGA_DELAY();
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(*fn->clk)(true, true, cookie);
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#ifdef CONFIG_SYS_FPGA_CHECK_BUSY
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ts = get_timer(0);
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while ((*fn->busy)(cookie)) {
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if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_BUSY) {
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printf("%s:%d: ** Timeout after %d ticks waiting for BUSY to deassert\n",
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__func__, __LINE__,
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CONFIG_SYS_FPGA_WAIT_BUSY);
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(*fn->abort)(cookie);
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return FPGA_FAIL;
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}
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}
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#endif
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
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if (bytecount % (bsize / 40) == 0)
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putc('.');
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#endif
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}
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return virtex2_slave_post(fn, cookie);
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}
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/*
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/*
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* Read the FPGA configuration data
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* Read the FPGA configuration data
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*/
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*/
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