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ARM: am33xx: Always inhibit init/refresh during DDR phy init
A couple of commits have modified the am33xx/am437x ddr2/ddr3 initialization path to fix certain issues, but have had the side effect of causing L3 noc errors during initialization. The two commits are: 69b918 "am33xx,ddr3: fix ddr3 sdram configuration" fc46ba "arm: am437x: Enable hardware leveling for EMIF" The EMIF_REG_INITREF_DIS_MASK bit still needs to be set for all platforms. This delays initialization and refresh until a later stage. The 500us timer can be programmed for platforms that require it and for platforms that don't require it. It is currently hardcoded for 400MHz systems. For systems with a higher memory frequency this needs to be a larger value, and for systems with a lower memory frequency this can be a lower value. This can be considered a separate issue and corrected in a later commit. Signed-off-by: Russ Dill <Russ.Dill@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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@ -292,19 +292,14 @@ static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr)
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void config_ddr_phy(const struct emif_regs *regs, int nr)
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{
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/*
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* Disable initialization and refreshes for now until we
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* finish programming EMIF regs.
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* Also set time between rising edge of DDR_RESET to rising
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* edge of DDR_CKE to > 500us per memory spec.
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* Disable initialization and refreshes for now until we finish
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* programming EMIF regs and set time between rising edge of
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* DDR_RESET to rising edge of DDR_CKE to > 500us per memory spec.
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* We currently hardcode a value based on a max expected frequency
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* of 400MHz.
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*/
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#ifndef CONFIG_AM43XX
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setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
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EMIF_REG_INITREF_DIS_MASK);
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#endif
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if (regs->zq_config)
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/* Set time between rising edge of DDR_RESET to rising
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* edge of DDR_CKE to > 500us per memory spec. */
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writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
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writel(EMIF_REG_INITREF_DIS_MASK | 0x3100,
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&emif_reg[nr]->emif_sdram_ref_ctrl);
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writel(regs->emif_ddr_phy_ctlr_1,
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&emif_reg[nr]->emif_ddr_phy_ctrl_1);
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