mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-29 16:10:24 +09:00
Merge commit 'wd/master'
This commit is contained in:
commit
33211469f7
@ -616,6 +616,10 @@ Alex Z
|
||||
lart SA1100
|
||||
dnp1110 SA1110
|
||||
|
||||
Sergey Lapin <slapin@ossfans.org>
|
||||
|
||||
afeb9260 ARM926EJS (AT91SAM9260 SoC)
|
||||
|
||||
-------------------------------------------------------------------------
|
||||
|
||||
Unknown / orphaned boards:
|
||||
@ -722,6 +726,7 @@ TsiChung Liew <Tsi-Chung.Liew@freescale.com>
|
||||
M52277EVB mcf5227x
|
||||
M5235EVB mcf52x2
|
||||
M5253DEMO mcf52x2
|
||||
M53017EVB mcf532x
|
||||
M5329EVB mcf532x
|
||||
M5373EVB mcf532x
|
||||
M54455EVB mcf5445x
|
||||
|
2
MAKEALL
2
MAKEALL
@ -534,6 +534,7 @@ LIST_ARM11=" \
|
||||
#########################################################################
|
||||
|
||||
LIST_at91=" \
|
||||
afeb9260 \
|
||||
at91cap9adk \
|
||||
at91rm9200dk \
|
||||
at91sam9260ek \
|
||||
@ -709,6 +710,7 @@ LIST_coldfire=" \
|
||||
M5272C3 \
|
||||
M5275EVB \
|
||||
M5282EVB \
|
||||
M53017EVB \
|
||||
M5329AFEE \
|
||||
M5373EVB \
|
||||
M54451EVB \
|
||||
|
46
Makefile
46
Makefile
@ -1932,7 +1932,27 @@ ZPC1900_config: unconfig
|
||||
## Coldfire
|
||||
#########################################################################
|
||||
|
||||
M52277EVB_config: unconfig
|
||||
M52277EVB_config \
|
||||
M52277EVB_spansion_config \
|
||||
M52277EVB_stmicro_config : unconfig
|
||||
@case "$@" in \
|
||||
M52277EVB_config) FLASH=SPANSION;; \
|
||||
M52277EVB_spansion_config) FLASH=SPANSION;; \
|
||||
M52277EVB_stmicro_config) FLASH=STMICRO;; \
|
||||
esac; \
|
||||
if [ "$${FLASH}" = "SPANSION" ] ; then \
|
||||
echo "#define CONFIG_SYS_SPANSION_BOOT" >> $(obj)include/config.h ; \
|
||||
echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m52277evb/config.tmp ; \
|
||||
cp $(obj)board/freescale/m52277evb/u-boot.spa $(obj)board/freescale/m52277evb/u-boot.lds ; \
|
||||
$(XECHO) "... with SPANSION boot..." ; \
|
||||
fi; \
|
||||
if [ "$${FLASH}" = "STMICRO" ] ; then \
|
||||
echo "#define CONFIG_CF_SBF" >> $(obj)include/config.h ; \
|
||||
echo "#define CONFIG_SYS_STMICRO_BOOT" >> $(obj)include/config.h ; \
|
||||
echo "TEXT_BASE = 0x43E00000" > $(obj)board/freescale/m52277evb/config.tmp ; \
|
||||
cp $(obj)board/freescale/m52277evb/u-boot.stm $(obj)board/freescale/m52277evb/u-boot.lds ; \
|
||||
$(XECHO) "... with ST Micro boot..." ; \
|
||||
fi
|
||||
@$(MKCONFIG) -a M52277EVB m68k mcf5227x m52277evb freescale
|
||||
|
||||
M5235EVB_config \
|
||||
@ -1992,6 +2012,9 @@ M5275EVB_config : unconfig
|
||||
M5282EVB_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5282evb freescale
|
||||
|
||||
M53017EVB_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) m68k mcf532x m53017evb freescale
|
||||
|
||||
M5329AFEE_config \
|
||||
M5329BFEE_config : unconfig
|
||||
@case "$@" in \
|
||||
@ -2527,15 +2550,6 @@ shannon_config : unconfig
|
||||
at91rm9200dk_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm920t at91rm9200dk atmel at91rm9200
|
||||
|
||||
at91sam9261ek_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9261ek atmel at91
|
||||
|
||||
at91sam9263ek_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9263ek atmel at91
|
||||
|
||||
at91sam9rlek_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9rlek atmel at91
|
||||
|
||||
cmc_pu2_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200
|
||||
|
||||
@ -2555,12 +2569,24 @@ mp2usb_config : unconfig
|
||||
## Atmel ARM926EJ-S Systems
|
||||
#########################################################################
|
||||
|
||||
afeb9260_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm926ejs afeb9260 NULL at91
|
||||
|
||||
at91cap9adk_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91cap9adk atmel at91
|
||||
|
||||
at91sam9260ek_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9260ek atmel at91
|
||||
|
||||
at91sam9261ek_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9261ek atmel at91
|
||||
|
||||
at91sam9263ek_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9263ek atmel at91
|
||||
|
||||
at91sam9rlek_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9rlek atmel at91
|
||||
|
||||
########################################################################
|
||||
## ARM Integrator boards - see doc/README-integrator for more info.
|
||||
integratorap_config \
|
||||
|
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o cfm_flash.o flash.o VCxK.o mii.o
|
||||
COBJS = $(BOARD).o cfm_flash.o flash.o VCxK.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
@ -1,304 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
if (setclear) {
|
||||
MCFGPIO_PASPAR |= 0x0F00;
|
||||
MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
|
||||
} else {
|
||||
MCFGPIO_PASPAR &= 0xF0FF;
|
||||
MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_AMD79C874VC "AMD79C874VC"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_s *info)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (info->miibase);
|
||||
int i;
|
||||
|
||||
fecp->ecr = FEC_ECR_RESET;
|
||||
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
||||
udelay(1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf("FEC_RESET_DELAY timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
volatile fec_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fec_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_s *info = dev->priv;
|
||||
int phyaddr, pass;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init)
|
||||
return info->phy_addr;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_AMD79C874VC:
|
||||
strcpy(info->phy_name,
|
||||
STR_ID_AMD79C874VC);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_AMD79C874VC:
|
||||
printf(STR_ID_AMD79C874VC);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY */
|
||||
|
||||
void mii_init(void) __attribute__((weak,alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fec_t *fecp;
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fec_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
56
board/afeb9260/Makefile
Normal file
56
board/afeb9260/Makefile
Normal file
@ -0,0 +1,56 @@
|
||||
#
|
||||
# (C) Copyright 2003-2008
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# (C) Copyright 2008
|
||||
# Stelian Pop <stelian.pop@leadtechdesign.com>
|
||||
# Lead Tech Design <www.leadtechdesign.com>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS-y += afeb9260.o
|
||||
COBJS-y += partition.o
|
||||
COBJS-$(CONFIG_CMD_NAND) += nand.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS-y))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
243
board/afeb9260/afeb9260.c
Normal file
243
board/afeb9260/afeb9260.c
Normal file
@ -0,0 +1,243 @@
|
||||
/*
|
||||
* (C) Copyright 2007-2008
|
||||
* Stelian Pop <stelian.pop@leadtechdesign.com>
|
||||
* Lead Tech Design <www.leadtechdesign.com>
|
||||
* (C) Copyright 2008 Sergey Lapin <slapin@ossfans.org>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/at91sam9260.h>
|
||||
#include <asm/arch/at91sam9260_matrix.h>
|
||||
#include <asm/arch/at91sam9_smc.h>
|
||||
#include <asm/arch/at91_pmc.h>
|
||||
#include <asm/arch/at91_rstc.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/io.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
|
||||
#include <netdev.h>
|
||||
#include <net.h>
|
||||
#endif
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/*
|
||||
* Miscelaneous platform dependent initialisations
|
||||
*/
|
||||
|
||||
static void afeb9260_serial_hw_init(void)
|
||||
{
|
||||
#ifdef CONFIG_USART0
|
||||
at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */
|
||||
at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USART1
|
||||
at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */
|
||||
at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USART2
|
||||
at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */
|
||||
at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USART3 /* DBGU */
|
||||
at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */
|
||||
at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void afeb9260_nand_hw_init(void)
|
||||
{
|
||||
unsigned long csa;
|
||||
|
||||
/* Enable CS3 */
|
||||
csa = at91_sys_read(AT91_MATRIX_EBICSA);
|
||||
at91_sys_write(AT91_MATRIX_EBICSA,
|
||||
csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
|
||||
|
||||
/* Configure SMC CS3 for NAND/SmartMedia */
|
||||
at91_sys_write(AT91_SMC_SETUP(3),
|
||||
AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
|
||||
AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
|
||||
at91_sys_write(AT91_SMC_PULSE(3),
|
||||
AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
|
||||
AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
|
||||
at91_sys_write(AT91_SMC_CYCLE(3),
|
||||
AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
|
||||
at91_sys_write(AT91_SMC_MODE(3),
|
||||
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
|
||||
AT91_SMC_EXNWMODE_DISABLE |
|
||||
AT91_SMC_DBW_8 |
|
||||
AT91_SMC_TDF_(2));
|
||||
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
|
||||
|
||||
/* Configure RDY/BSY */
|
||||
at91_set_gpio_input(AT91_PIN_PC13, 1);
|
||||
|
||||
/* Enable NandFlash */
|
||||
at91_set_gpio_output(AT91_PIN_PC14, 1);
|
||||
}
|
||||
|
||||
static void afeb9260_spi_hw_init(void)
|
||||
{
|
||||
at91_set_A_periph(AT91_PIN_PA3, 0); /* SPI0_NPCS0 */
|
||||
at91_set_B_periph(AT91_PIN_PC11, 0); /* SPI0_NPCS1 */
|
||||
|
||||
at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
|
||||
at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
|
||||
at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
|
||||
|
||||
/* Enable clock */
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI0);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MACB
|
||||
static void afeb9260_macb_hw_init(void)
|
||||
{
|
||||
/* Enable clock */
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
|
||||
|
||||
/*
|
||||
* Disable pull-up on:
|
||||
* RXDV (PA17) => PHY normal mode (not Test mode)
|
||||
* ERX0 (PA14) => PHY ADDR0
|
||||
* ERX1 (PA15) => PHY ADDR1
|
||||
* ERX2 (PA25) => PHY ADDR2
|
||||
* ERX3 (PA26) => PHY ADDR3
|
||||
* ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
|
||||
*
|
||||
* PHY has internal pull-down
|
||||
*/
|
||||
writel(pin_to_mask(AT91_PIN_PA14) |
|
||||
pin_to_mask(AT91_PIN_PA15) |
|
||||
pin_to_mask(AT91_PIN_PA17) |
|
||||
pin_to_mask(AT91_PIN_PA25) |
|
||||
pin_to_mask(AT91_PIN_PA26) |
|
||||
pin_to_mask(AT91_PIN_PA28),
|
||||
pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
|
||||
|
||||
/* Need to reset PHY -> 500ms reset */
|
||||
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
|
||||
AT91_RSTC_ERSTL | (0x0D << 8) |
|
||||
AT91_RSTC_URSTEN);
|
||||
|
||||
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
|
||||
|
||||
/* Wait for end hardware reset */
|
||||
while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
|
||||
|
||||
/* Restore NRST value */
|
||||
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
|
||||
AT91_RSTC_ERSTL | (0x0 << 8) |
|
||||
AT91_RSTC_URSTEN);
|
||||
|
||||
/* Re-enable pull-up */
|
||||
writel(pin_to_mask(AT91_PIN_PA14) |
|
||||
pin_to_mask(AT91_PIN_PA15) |
|
||||
pin_to_mask(AT91_PIN_PA17) |
|
||||
pin_to_mask(AT91_PIN_PA25) |
|
||||
pin_to_mask(AT91_PIN_PA26) |
|
||||
pin_to_mask(AT91_PIN_PA28),
|
||||
pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
|
||||
|
||||
at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */
|
||||
at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */
|
||||
at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */
|
||||
at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */
|
||||
at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */
|
||||
at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */
|
||||
at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */
|
||||
at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */
|
||||
at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */
|
||||
at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */
|
||||
|
||||
#ifndef CONFIG_RMII
|
||||
at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */
|
||||
at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */
|
||||
at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */
|
||||
at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */
|
||||
at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */
|
||||
at91_set_B_periph(AT91_PIN_PA10, 0); /* ETX2 */
|
||||
at91_set_B_periph(AT91_PIN_PA11, 0); /* ETX3 */
|
||||
at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */
|
||||
#endif
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* Enable Ctrlc */
|
||||
console_init_f();
|
||||
|
||||
/* arch number of AT91SAM9260EK-Board */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_AFEB9260;
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||
|
||||
afeb9260_serial_hw_init();
|
||||
#ifdef CONFIG_CMD_NAND
|
||||
afeb9260_nand_hw_init();
|
||||
#endif
|
||||
afeb9260_spi_hw_init();
|
||||
#ifdef CONFIG_MACB
|
||||
afeb9260_macb_hw_init();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM;
|
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_RESET_PHY_R
|
||||
void reset_phy(void)
|
||||
{
|
||||
#ifdef CONFIG_MACB
|
||||
/*
|
||||
* Initialize ethernet HW addr prior to starting Linux,
|
||||
* needed for nfsroot
|
||||
*/
|
||||
eth_init(gd->bd);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int rc = 0;
|
||||
#ifdef CONFIG_MACB
|
||||
rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00);
|
||||
#endif
|
||||
return rc;
|
||||
}
|
1
board/afeb9260/config.mk
Normal file
1
board/afeb9260/config.mk
Normal file
@ -0,0 +1 @@
|
||||
TEXT_BASE = 0x21f00000
|
78
board/afeb9260/nand.c
Normal file
78
board/afeb9260/nand.c
Normal file
@ -0,0 +1,78 @@
|
||||
/*
|
||||
* (C) Copyright 2007-2008
|
||||
* Stelian Pop <stelian.pop@leadtechdesign.com>
|
||||
* Lead Tech Design <www.leadtechdesign.com>
|
||||
*
|
||||
* (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/at91sam9260.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/at91_pio.h>
|
||||
|
||||
#include <nand.h>
|
||||
|
||||
/*
|
||||
* hardware specific access to control-lines
|
||||
*/
|
||||
#define MASK_ALE (1 << 21) /* our ALE is AD21 */
|
||||
#define MASK_CLE (1 << 22) /* our CLE is AD22 */
|
||||
|
||||
static void at91sam9260ek_nand_hwcontrol(struct mtd_info *mtd,
|
||||
int cmd, unsigned int ctrl)
|
||||
{
|
||||
struct nand_chip *this = mtd->priv;
|
||||
|
||||
if (ctrl & NAND_CTRL_CHANGE) {
|
||||
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
|
||||
IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
|
||||
|
||||
if (ctrl & NAND_CLE)
|
||||
IO_ADDR_W |= MASK_CLE;
|
||||
if (ctrl & NAND_ALE)
|
||||
IO_ADDR_W |= MASK_ALE;
|
||||
|
||||
at91_set_gpio_value(AT91_PIN_PC14, !(ctrl & NAND_NCE));
|
||||
this->IO_ADDR_W = (void *) IO_ADDR_W;
|
||||
}
|
||||
|
||||
if (cmd != NAND_CMD_NONE)
|
||||
writeb(cmd, this->IO_ADDR_W);
|
||||
}
|
||||
|
||||
static int at91sam9260ek_nand_ready(struct mtd_info *mtd)
|
||||
{
|
||||
return at91_get_gpio_value(AT91_PIN_PC13);
|
||||
}
|
||||
|
||||
int board_nand_init(struct nand_chip *nand)
|
||||
{
|
||||
nand->ecc.mode = NAND_ECC_SOFT;
|
||||
#ifdef CONFIG_SYS_NAND_DBW_16
|
||||
nand->options = NAND_BUSWIDTH_16;
|
||||
#endif
|
||||
nand->cmd_ctrl = at91sam9260ek_nand_hwcontrol;
|
||||
nand->dev_ready = at91sam9260ek_nand_ready;
|
||||
nand->chip_delay = 20;
|
||||
|
||||
return 0;
|
||||
}
|
37
board/afeb9260/partition.c
Normal file
37
board/afeb9260/partition.c
Normal file
@ -0,0 +1,37 @@
|
||||
/*
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <config.h>
|
||||
#include <asm/hardware.h>
|
||||
#include <dataflash.h>
|
||||
|
||||
AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
|
||||
|
||||
struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
|
||||
{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
|
||||
{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1, 1}
|
||||
};
|
||||
|
||||
/*define the area offsets*/
|
||||
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
|
||||
{0x00000000, 0x000041FF, FLAG_PROTECT_CLEAR, 0, "Bootstrap"},
|
||||
{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
|
||||
{0x00008400, 0x00041FFF, FLAG_PROTECT_CLEAR, 0, "U-Boot"},
|
||||
};
|
||||
|
@ -98,7 +98,7 @@ tlbtab:
|
||||
tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
|
||||
#if defined(CONFIG_RAPIDIO)
|
||||
/* TLB-entries for RapidIO (SRIO) */
|
||||
/* TLB-entries for RapidIO (SRIO) */
|
||||
tlbentry(CONFIG_SYS_SRGPL0_REG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_REG_BAR,
|
||||
0xD, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_SRGPL0_CFG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_CFG_BAR,
|
||||
|
@ -52,19 +52,19 @@ static void at91cap9_serial_hw_init(void)
|
||||
#ifdef CONFIG_USART0
|
||||
at91_set_A_periph(AT91_PIN_PA22, 1); /* TXD0 */
|
||||
at91_set_A_periph(AT91_PIN_PA23, 0); /* RXD0 */
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US0);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USART1
|
||||
at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
|
||||
at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US1);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USART2
|
||||
at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
|
||||
at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US2);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USART3 /* DBGU */
|
||||
@ -412,7 +412,7 @@ int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int rc = 0;
|
||||
#ifdef CONFIG_MACB
|
||||
rc = macb_eth_initialize(0, (void *)AT91_BASE_EMAC, 0x00);
|
||||
rc = macb_eth_initialize(0, (void *)AT91CAP9_BASE_EMAC, 0x00);
|
||||
#endif
|
||||
return rc;
|
||||
}
|
||||
|
@ -48,19 +48,19 @@ static void at91sam9260ek_serial_hw_init(void)
|
||||
#ifdef CONFIG_USART0
|
||||
at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */
|
||||
at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USART1
|
||||
at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */
|
||||
at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USART2
|
||||
at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */
|
||||
at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USART3 /* DBGU */
|
||||
@ -255,7 +255,7 @@ int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int rc = 0;
|
||||
#ifdef CONFIG_MACB
|
||||
rc = macb_eth_initialize(0, (void *)AT91_BASE_EMAC, 0x00);
|
||||
rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00);
|
||||
#endif
|
||||
return rc;
|
||||
}
|
||||
|
@ -48,19 +48,19 @@ static void at91sam9261ek_serial_hw_init(void)
|
||||
#ifdef CONFIG_USART0
|
||||
at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */
|
||||
at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US0);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USART1
|
||||
at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */
|
||||
at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US1);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USART2
|
||||
at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */
|
||||
at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US2);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USART3 /* DBGU */
|
||||
|
@ -51,19 +51,19 @@ static void at91sam9263ek_serial_hw_init(void)
|
||||
#ifdef CONFIG_USART0
|
||||
at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */
|
||||
at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US0);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USART1
|
||||
at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
|
||||
at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US1);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USART2
|
||||
at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
|
||||
at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US2);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USART3 /* DBGU */
|
||||
@ -344,7 +344,7 @@ int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int rc = 0;
|
||||
#ifdef CONFIG_MACB
|
||||
rc = macb_eth_initialize(0, (void *)AT91_BASE_EMAC, 0x00);
|
||||
rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00);
|
||||
#endif
|
||||
return rc;
|
||||
}
|
||||
|
@ -48,19 +48,19 @@ static void at91sam9rlek_serial_hw_init(void)
|
||||
#ifdef CONFIG_USART0
|
||||
at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */
|
||||
at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US0);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USART1
|
||||
at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */
|
||||
at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US1);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USART2
|
||||
at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */
|
||||
at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US2);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USART3 /* DBGU */
|
||||
|
@ -377,7 +377,7 @@ int last_stage_init(void)
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
|
||||
struct pci_controller *hose);
|
||||
struct pci_controller *hose);
|
||||
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
|
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o flash.o mii.o
|
||||
COBJS = $(BOARD).o flash.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
@ -1,303 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
|
||||
if (setclear) {
|
||||
gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
|
||||
} else {
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_AMD79C874VC "AMD79C874VC"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_s *info)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (info->miibase);
|
||||
int i;
|
||||
|
||||
fecp->ecr = FEC_ECR_RESET;
|
||||
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
||||
udelay(1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf("FEC_RESET_DELAY timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
volatile fec_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fec_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_s *info = dev->priv;
|
||||
int phyaddr, pass;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init)
|
||||
return info->phy_addr;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_AMD79C874VC:
|
||||
strcpy(info->phy_name,
|
||||
STR_ID_AMD79C874VC);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_AMD79C874VC:
|
||||
printf(STR_ID_AMD79C874VC);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY */
|
||||
|
||||
void mii_init(void) __attribute__((weak,alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fec_t *fecp;
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fec_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
@ -46,8 +46,6 @@
|
||||
# define DFC_DEBUG3(fmt, args...)
|
||||
#endif
|
||||
|
||||
#define MIN(x, y) ((x < y) ? x : y)
|
||||
|
||||
/* These really don't belong here, as they are specific to the NAND Model */
|
||||
static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
|
||||
|
||||
|
@ -22,4 +22,6 @@
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
TEXT_BASE = 0
|
||||
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
|
||||
|
||||
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
|
||||
|
@ -38,8 +38,18 @@ int checkboard(void)
|
||||
|
||||
phys_size_t initdram(int board_type)
|
||||
{
|
||||
u32 dramsize;
|
||||
|
||||
#ifdef CONFIG_CF_SBF
|
||||
/*
|
||||
* Serial Boot: The dram is already initialized in start.S
|
||||
* only require to return DRAM size
|
||||
*/
|
||||
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
|
||||
#else
|
||||
volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
|
||||
u32 dramsize, i;
|
||||
volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
|
||||
u32 i;
|
||||
|
||||
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
|
||||
|
||||
@ -49,6 +59,8 @@ phys_size_t initdram(int board_type)
|
||||
}
|
||||
i--;
|
||||
|
||||
gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
|
||||
|
||||
sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
|
||||
|
||||
sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
|
||||
@ -56,24 +68,30 @@ phys_size_t initdram(int board_type)
|
||||
|
||||
/* Issue PALL */
|
||||
sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
|
||||
__asm__("nop");
|
||||
|
||||
/* Issue LEMR */
|
||||
/*sdram->sdmr = CONFIG_SYS_SDRAM_EMOD; */
|
||||
sdram->sdmr = CONFIG_SYS_SDRAM_MODE;
|
||||
__asm__("nop");
|
||||
sdram->sdmr = CONFIG_SYS_SDRAM_EMOD;
|
||||
__asm__("nop");
|
||||
|
||||
udelay(1000);
|
||||
|
||||
/* Issue PALL */
|
||||
sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
|
||||
__asm__("nop");
|
||||
|
||||
/* Perform two refresh cycles */
|
||||
sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
|
||||
__asm__("nop");
|
||||
sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
|
||||
__asm__("nop");
|
||||
|
||||
sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
|
||||
sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000C00;
|
||||
|
||||
udelay(100);
|
||||
|
||||
#endif
|
||||
return (dramsize);
|
||||
};
|
||||
|
||||
|
@ -33,11 +33,11 @@ SECTIONS
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
@ -55,15 +55,7 @@ SECTIONS
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/mcf523x/start.o (.text)
|
||||
cpu/mcf523x/cpu_init.o (.text)
|
||||
lib_m68k/traps.o (.text)
|
||||
lib_m68k/interrupts.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
. = DEFINED(env_offset) ? env_offset : .;
|
||||
common/env_embedded.o (.text)
|
||||
cpu/mcf5227x/start.o (.text)
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
@ -129,7 +121,7 @@ SECTIONS
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss (NOLOAD) :
|
||||
.bss :
|
||||
{
|
||||
_sbss = .;
|
||||
*(.sbss) *(.scommon)
|
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o mii.o
|
||||
COBJS = $(BOARD).o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
@ -1,307 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
|
||||
if (setclear) {
|
||||
gpio->par_feci2c |=
|
||||
(GPIO_PAR_FECI2C_EMDC_FECEMDC | GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
|
||||
} else {
|
||||
gpio->par_feci2c &=
|
||||
~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
#define STR_ID_KS8721BL "KS8721BL"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_s *info)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (info->miibase);
|
||||
int i;
|
||||
|
||||
fecp->ecr = FEC_ECR_RESET;
|
||||
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
||||
udelay(1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf("FEC_RESET_DELAY timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
volatile fec_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fec_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_s *info = dev->priv;
|
||||
int phyaddr, pass;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init)
|
||||
return info->phy_addr;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_KS8721BL:
|
||||
strcpy(info->phy_name,
|
||||
STR_ID_KS8721BL);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_KS8721BL:
|
||||
printf(STR_ID_KS8721BL);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY */
|
||||
|
||||
void mii_init(void) __attribute__((weak,alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fec_t *fecp;
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fec_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o mii.o
|
||||
COBJS = $(BOARD).o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
@ -1,303 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
if (setclear) {
|
||||
/* Enable Ethernet pins */
|
||||
mbar_writeByte(MCF_GPIO_PAR_FECI2C, CONFIG_SYS_FECI2C);
|
||||
} else {
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
#define STR_ID_KS8721BL "KS8721BL"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_s *info)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (info->miibase);
|
||||
int i;
|
||||
|
||||
fecp->ecr = FEC_ECR_RESET;
|
||||
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
||||
udelay(1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf("FEC_RESET_DELAY timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
volatile fec_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fec_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_s *info = dev->priv;
|
||||
int phyaddr, pass;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init)
|
||||
return info->phy_addr;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_KS8721BL:
|
||||
strcpy(info->phy_name,
|
||||
STR_ID_KS8721BL);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_KS8721BL:
|
||||
printf(STR_ID_KS8721BL);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY */
|
||||
|
||||
void mii_init(void) __attribute__((weak,alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fec_t *fecp;
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fec_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o flash.o mii.o
|
||||
COBJS = $(BOARD).o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
@ -1,378 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2000-2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
|
||||
#define FLASH_BANK_SIZE 0x200000
|
||||
|
||||
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
|
||||
|
||||
void flash_print_info (flash_info_t * info)
|
||||
{
|
||||
int i;
|
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) {
|
||||
case (AMD_MANUFACT & FLASH_VENDMASK):
|
||||
printf ("AMD: ");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Vendor ");
|
||||
break;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case (AMD_ID_PL160CB & FLASH_TYPEMASK):
|
||||
printf ("AM29PL160CB (16Mbit)\n");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Chip Type\n");
|
||||
goto Done;
|
||||
break;
|
||||
}
|
||||
|
||||
printf (" Size: %ld MB in %d Sectors\n",
|
||||
info->size >> 20, info->sector_count);
|
||||
|
||||
printf (" Sector Start Addresses:");
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
if ((i % 5) == 0) {
|
||||
printf ("\n ");
|
||||
}
|
||||
printf (" %08lX%s", info->start[i],
|
||||
info->protect[i] ? " (RO)" : " ");
|
||||
}
|
||||
printf ("\n");
|
||||
|
||||
Done:
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
int i, j;
|
||||
ulong size = 0;
|
||||
|
||||
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
|
||||
ulong flashbase = 0;
|
||||
|
||||
flash_info[i].flash_id =
|
||||
(AMD_MANUFACT & FLASH_VENDMASK) |
|
||||
(AMD_ID_PL160CB & FLASH_TYPEMASK);
|
||||
flash_info[i].size = FLASH_BANK_SIZE;
|
||||
flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
|
||||
memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
|
||||
if (i == 0)
|
||||
flashbase = PHYS_FLASH_1;
|
||||
else
|
||||
panic ("configured to many flash banks!\n");
|
||||
|
||||
for (j = 0; j < flash_info[i].sector_count; j++) {
|
||||
if (j == 0) {
|
||||
/* 1st is 16 KiB */
|
||||
flash_info[i].start[j] = flashbase;
|
||||
}
|
||||
if ((j >= 1) && (j <= 2)) {
|
||||
/* 2nd and 3rd are 8 KiB */
|
||||
flash_info[i].start[j] =
|
||||
flashbase + 0x4000 + 0x2000 * (j - 1);
|
||||
}
|
||||
if (j == 3) {
|
||||
/* 4th is 224 KiB */
|
||||
flash_info[i].start[j] = flashbase + 0x8000;
|
||||
}
|
||||
if ((j >= 4) && (j <= 10)) {
|
||||
/* rest is 256 KiB */
|
||||
flash_info[i].start[j] =
|
||||
flashbase + 0x40000 + 0x40000 * (j -
|
||||
4);
|
||||
}
|
||||
}
|
||||
size += flash_info[i].size;
|
||||
}
|
||||
|
||||
flash_protect (FLAG_PROTECT_SET,
|
||||
CONFIG_SYS_FLASH_BASE,
|
||||
CONFIG_SYS_FLASH_BASE + 0x3ffff, &flash_info[0]);
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
|
||||
#define CMD_READ_ARRAY 0x00F0
|
||||
#define CMD_UNLOCK1 0x00AA
|
||||
#define CMD_UNLOCK2 0x0055
|
||||
#define CMD_ERASE_SETUP 0x0080
|
||||
#define CMD_ERASE_CONFIRM 0x0030
|
||||
#define CMD_PROGRAM 0x00A0
|
||||
#define CMD_UNLOCK_BYPASS 0x0020
|
||||
|
||||
#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555<<1)))
|
||||
#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA<<1)))
|
||||
|
||||
#define BIT_ERASE_DONE 0x0080
|
||||
#define BIT_RDY_MASK 0x0080
|
||||
#define BIT_PROGRAM_ERROR 0x0020
|
||||
#define BIT_TIMEOUT 0x80000000 /* our flag */
|
||||
|
||||
#define READY 1
|
||||
#define ERR 2
|
||||
#define TMO 4
|
||||
|
||||
|
||||
int flash_erase (flash_info_t * info, int s_first, int s_last)
|
||||
{
|
||||
ulong result;
|
||||
int iflag, cflag, prot, sect;
|
||||
int rc = ERR_OK;
|
||||
int chip1;
|
||||
|
||||
/* first look for protection bits */
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN)
|
||||
return ERR_UNKNOWN_FLASH_TYPE;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
return ERR_INVAL;
|
||||
}
|
||||
|
||||
if ((info->flash_id & FLASH_VENDMASK) !=
|
||||
(AMD_MANUFACT & FLASH_VENDMASK)) {
|
||||
return ERR_UNKNOWN_FLASH_VENDOR;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect = s_first; sect <= s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
if (prot)
|
||||
return ERR_PROTECTED;
|
||||
|
||||
/*
|
||||
* Disable interrupts which might cause a timeout
|
||||
* here. Remember that our exception vectors are
|
||||
* at address 0 in the flash, and we don't want a
|
||||
* (ticker) exception to happen while the flash
|
||||
* chip is in programming mode.
|
||||
*/
|
||||
|
||||
cflag = icache_status ();
|
||||
icache_disable ();
|
||||
iflag = disable_interrupts ();
|
||||
|
||||
printf ("\n");
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
|
||||
printf ("Erasing sector %2d ... ", sect);
|
||||
|
||||
/* arm simple, non interrupt dependent timer */
|
||||
set_timer (0);
|
||||
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
volatile u16 *addr =
|
||||
(volatile u16 *) (info->start[sect]);
|
||||
|
||||
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
|
||||
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
|
||||
MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
|
||||
|
||||
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
|
||||
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
|
||||
*addr = CMD_ERASE_CONFIRM;
|
||||
|
||||
/* wait until flash is ready */
|
||||
chip1 = 0;
|
||||
|
||||
do {
|
||||
result = *addr;
|
||||
|
||||
/* check timeout */
|
||||
if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
|
||||
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
|
||||
chip1 = TMO;
|
||||
break;
|
||||
}
|
||||
|
||||
if (!chip1
|
||||
&& (result & 0xFFFF) & BIT_ERASE_DONE)
|
||||
chip1 = READY;
|
||||
|
||||
} while (!chip1);
|
||||
|
||||
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
|
||||
|
||||
if (chip1 == ERR) {
|
||||
rc = ERR_PROG_ERROR;
|
||||
goto outahere;
|
||||
}
|
||||
if (chip1 == TMO) {
|
||||
rc = ERR_TIMOUT;
|
||||
goto outahere;
|
||||
}
|
||||
|
||||
printf ("ok.\n");
|
||||
} else { /* it was protected */
|
||||
|
||||
printf ("protected!\n");
|
||||
}
|
||||
}
|
||||
|
||||
if (ctrlc ())
|
||||
printf ("User Interrupt!\n");
|
||||
|
||||
outahere:
|
||||
/* allow flash to settle - wait 10 ms */
|
||||
udelay (10000);
|
||||
|
||||
if (iflag)
|
||||
enable_interrupts ();
|
||||
|
||||
if (cflag)
|
||||
icache_enable ();
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int write_word (flash_info_t * info, ulong dest, ulong data)
|
||||
{
|
||||
volatile u16 *addr = (volatile u16 *) dest;
|
||||
ulong result;
|
||||
int rc = ERR_OK;
|
||||
int cflag, iflag;
|
||||
int chip1;
|
||||
|
||||
/*
|
||||
* Check if Flash is (sufficiently) erased
|
||||
*/
|
||||
result = *addr;
|
||||
if ((result & data) != data)
|
||||
return ERR_NOT_ERASED;
|
||||
|
||||
|
||||
/*
|
||||
* Disable interrupts which might cause a timeout
|
||||
* here. Remember that our exception vectors are
|
||||
* at address 0 in the flash, and we don't want a
|
||||
* (ticker) exception to happen while the flash
|
||||
* chip is in programming mode.
|
||||
*/
|
||||
|
||||
cflag = icache_status ();
|
||||
icache_disable ();
|
||||
iflag = disable_interrupts ();
|
||||
|
||||
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
|
||||
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
|
||||
MEM_FLASH_ADDR1 = CMD_PROGRAM;
|
||||
*addr = data;
|
||||
|
||||
/* arm simple, non interrupt dependent timer */
|
||||
set_timer (0);
|
||||
|
||||
/* wait until flash is ready */
|
||||
chip1 = 0;
|
||||
do {
|
||||
result = *addr;
|
||||
|
||||
/* check timeout */
|
||||
if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
|
||||
chip1 = ERR | TMO;
|
||||
break;
|
||||
}
|
||||
if (!chip1 && ((result & 0x80) == (data & 0x80)))
|
||||
chip1 = READY;
|
||||
|
||||
} while (!chip1);
|
||||
|
||||
*addr = CMD_READ_ARRAY;
|
||||
|
||||
if (chip1 == ERR || *addr != data)
|
||||
rc = ERR_PROG_ERROR;
|
||||
|
||||
if (iflag)
|
||||
enable_interrupts ();
|
||||
|
||||
if (cflag)
|
||||
icache_enable ();
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
||||
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong wp, data;
|
||||
int rc;
|
||||
|
||||
if (addr & 1) {
|
||||
printf ("unaligned destination not supported\n");
|
||||
return ERR_ALIGN;
|
||||
}
|
||||
|
||||
#if 0
|
||||
if (cnt & 1) {
|
||||
printf ("odd transfer sizes not supported\n");
|
||||
return ERR_ALIGN;
|
||||
}
|
||||
#endif
|
||||
|
||||
wp = addr;
|
||||
|
||||
if (addr & 1) {
|
||||
data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *)
|
||||
src);
|
||||
if ((rc = write_word (info, wp - 1, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
src += 1;
|
||||
wp += 1;
|
||||
cnt -= 1;
|
||||
}
|
||||
|
||||
while (cnt >= 2) {
|
||||
data = *((volatile u16 *) src);
|
||||
if ((rc = write_word (info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
src += 2;
|
||||
wp += 2;
|
||||
cnt -= 2;
|
||||
}
|
||||
|
||||
if (cnt == 1) {
|
||||
data = (*((volatile u8 *) src) << 8) |
|
||||
*((volatile u8 *) (wp + 1));
|
||||
if ((rc = write_word (info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
src += 1;
|
||||
wp += 1;
|
||||
cnt -= 1;
|
||||
}
|
||||
|
||||
return ERR_OK;
|
||||
}
|
@ -1,303 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
|
||||
if (setclear) {
|
||||
gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
|
||||
} else {
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_AMD79C874VC "AMD79C874VC"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_s *info)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (info->miibase);
|
||||
int i;
|
||||
|
||||
fecp->ecr = FEC_ECR_RESET;
|
||||
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
||||
udelay(1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf("FEC_RESET_DELAY timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
volatile fec_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fec_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_s *info = dev->priv;
|
||||
int phyaddr, pass;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init)
|
||||
return info->phy_addr;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_AMD79C874VC:
|
||||
strcpy(info->phy_name,
|
||||
STR_ID_AMD79C874VC);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_AMD79C874VC:
|
||||
printf(STR_ID_AMD79C874VC);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY */
|
||||
|
||||
void mii_init(void) __attribute__((weak,alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fec_t *fecp;
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fec_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o mii.o
|
||||
COBJS = $(BOARD).o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
@ -1,319 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
struct fec_info_s *info = (struct fec_info_s *) dev->priv;
|
||||
volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
|
||||
|
||||
if (setclear) {
|
||||
/* Enable Ethernet pins */
|
||||
if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
|
||||
gpio->par_feci2c |= 0x0F00;
|
||||
gpio->par_fec0hl |= 0xC0;
|
||||
} else {
|
||||
gpio->par_feci2c |= 0x00A0;
|
||||
gpio->par_fec1hl |= 0xC0;
|
||||
}
|
||||
} else {
|
||||
if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
|
||||
gpio->par_feci2c &= ~0x0F00;
|
||||
gpio->par_fec0hl &= ~0xC0;
|
||||
} else {
|
||||
gpio->par_feci2c &= ~0x00A0;
|
||||
gpio->par_fec1hl &= ~0xC0;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
#define STR_ID_KS8721BL "KS8721BL"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_s *info)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (info->miibase);
|
||||
int i;
|
||||
|
||||
fecp->ecr = FEC_ECR_RESET;
|
||||
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
||||
udelay(1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf("FEC_RESET_DELAY timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
volatile fec_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fec_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_s *info = dev->priv;
|
||||
int phyaddr, pass;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init)
|
||||
return info->phy_addr;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_KS8721BL:
|
||||
strcpy(info->phy_name,
|
||||
STR_ID_KS8721BL);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_KS8721BL:
|
||||
printf(STR_ID_KS8721BL);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY */
|
||||
|
||||
void mii_init(void) __attribute__((weak,alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fec_t *fecp;
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fec_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o mii.o
|
||||
COBJS = $(BOARD).o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
@ -1,304 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
if (setclear) {
|
||||
MCFGPIO_PASPAR |= 0x0F00;
|
||||
MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
|
||||
} else {
|
||||
MCFGPIO_PASPAR &= 0xF0FF;
|
||||
MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_AMD79C874VC "AMD79C874VC"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_s *info)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (info->miibase);
|
||||
int i;
|
||||
|
||||
fecp->ecr = FEC_ECR_RESET;
|
||||
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
||||
udelay(1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf("FEC_RESET_DELAY timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
volatile fec_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fec_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_s *info = dev->priv;
|
||||
int phyaddr, pass;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init)
|
||||
return info->phy_addr;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_AMD79C874VC:
|
||||
strcpy(info->phy_name,
|
||||
STR_ID_AMD79C874VC);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_AMD79C874VC:
|
||||
printf(STR_ID_AMD79C874VC);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY */
|
||||
|
||||
void mii_init(void) __attribute__((weak,alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fec_t *fecp;
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fec_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
44
board/freescale/m53017evb/Makefile
Normal file
44
board/freescale/m53017evb/Makefile
Normal file
@ -0,0 +1,44 @@
|
||||
#
|
||||
# (C) Copyright 2000-2003
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
25
board/freescale/m53017evb/config.mk
Normal file
25
board/freescale/m53017evb/config.mk
Normal file
@ -0,0 +1,25 @@
|
||||
#
|
||||
# (C) Copyright 2000-2003
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
TEXT_BASE = 0
|
94
board/freescale/m53017evb/m53017evb.c
Normal file
94
board/freescale/m53017evb/m53017evb.c
Normal file
@ -0,0 +1,94 @@
|
||||
/*
|
||||
* (C) Copyright 2000-2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: ");
|
||||
puts("Freescale M53017EVB\n");
|
||||
return 0;
|
||||
};
|
||||
|
||||
phys_size_t initdram(int board_type)
|
||||
{
|
||||
volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
|
||||
u32 dramsize, i;
|
||||
|
||||
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
|
||||
|
||||
for (i = 0x13; i < 0x20; i++) {
|
||||
if (dramsize == (1 << i))
|
||||
break;
|
||||
}
|
||||
i--;
|
||||
|
||||
sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
|
||||
#ifdef CONFIG_SYS_SDRAM_BASE1
|
||||
sdram->cs1 = (CONFIG_SYS_SDRAM_BASE | i);
|
||||
#endif
|
||||
sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
|
||||
sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
|
||||
|
||||
udelay(500);
|
||||
|
||||
/* Issue PALL */
|
||||
sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
|
||||
asm("nop");
|
||||
|
||||
/* Perform two refresh cycles */
|
||||
sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
|
||||
sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
|
||||
asm("nop");
|
||||
|
||||
/* Issue LEMR */
|
||||
sdram->mode = CONFIG_SYS_SDRAM_MODE;
|
||||
asm("nop");
|
||||
sdram->mode = CONFIG_SYS_SDRAM_EMOD;
|
||||
asm("nop");
|
||||
|
||||
sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
|
||||
asm("nop");
|
||||
|
||||
sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
|
||||
asm("nop");
|
||||
|
||||
udelay(100);
|
||||
|
||||
return dramsize;
|
||||
};
|
||||
|
||||
int testdram(void)
|
||||
{
|
||||
/* TODO: XXX XXX XXX */
|
||||
printf("DRAM test not implemented!\n");
|
||||
|
||||
return (0);
|
||||
}
|
@ -55,9 +55,9 @@ SECTIONS
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/mcf5445x/start.o (.text)
|
||||
lib_m68k/traps.o (.text)
|
||||
lib_m68k/interrupts.o (.text)
|
||||
cpu/mcf532x/start.o (.text)
|
||||
cpu/mcf532x/libmcf532x.a (.text)
|
||||
lib_m68k/libm68k.a (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o mii.o nand.o
|
||||
COBJS = $(BOARD).o nand.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
@ -1,306 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
|
||||
if (setclear) {
|
||||
gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
|
||||
gpio->par_feci2c |=
|
||||
GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO;
|
||||
} else {
|
||||
gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
|
||||
gpio->par_feci2c &=
|
||||
~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_s *info)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (info->miibase);
|
||||
int i;
|
||||
|
||||
fecp->ecr = FEC_ECR_RESET;
|
||||
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
||||
udelay(1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf("FEC_RESET_DELAY timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
volatile fec_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fec_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_s *info = dev->priv;
|
||||
int phyaddr, pass;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init)
|
||||
return info->phy_addr;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_DP83848VV:
|
||||
strcpy(info->phy_name,
|
||||
STR_ID_DP83848VV);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_DP83848VV:
|
||||
printf(STR_ID_DP83848VV);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY */
|
||||
|
||||
void mii_init(void) __attribute__((weak,alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fec_t *fecp;
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fec_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
@ -36,56 +36,42 @@ DECLARE_GLOBAL_DATA_PTR;
|
||||
#include <linux/mtd/mtd.h>
|
||||
|
||||
#define SET_CLE 0x10
|
||||
#define CLR_CLE ~SET_CLE
|
||||
#define SET_ALE 0x08
|
||||
#define CLR_ALE ~SET_ALE
|
||||
|
||||
static void nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
|
||||
static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
|
||||
{
|
||||
struct nand_chip *this = mtdinfo->priv;
|
||||
/* volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; TODO: handle wp */
|
||||
u32 nand_baseaddr = (u32) this->IO_ADDR_W;
|
||||
volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
|
||||
|
||||
if (ctrl & NAND_CTRL_CHANGE) {
|
||||
if ( ctrl & NAND_CLE )
|
||||
nand_baseaddr |= SET_CLE;
|
||||
else
|
||||
nand_baseaddr &= CLR_CLE;
|
||||
if ( ctrl & NAND_ALE )
|
||||
nand_baseaddr |= SET_ALE;
|
||||
else
|
||||
nand_baseaddr &= CLR_ALE;
|
||||
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
|
||||
|
||||
IO_ADDR_W &= ~(SET_ALE | SET_CLE);
|
||||
*nCE &= 0xFFFB;
|
||||
|
||||
if (ctrl & NAND_NCE)
|
||||
*nCE |= 0x0004;
|
||||
if (ctrl & NAND_CLE)
|
||||
IO_ADDR_W |= SET_CLE;
|
||||
if (ctrl & NAND_ALE)
|
||||
IO_ADDR_W |= SET_ALE;
|
||||
|
||||
this->IO_ADDR_W = (void *)IO_ADDR_W;
|
||||
}
|
||||
this->IO_ADDR_W = (void __iomem *)(nand_baseaddr);
|
||||
|
||||
if (cmd != NAND_CMD_NONE)
|
||||
writeb(cmd, this->IO_ADDR_W);
|
||||
}
|
||||
|
||||
static void nand_write_byte(struct mtd_info *mtdinfo, u_char byte)
|
||||
{
|
||||
struct nand_chip *this = mtdinfo->priv;
|
||||
*((volatile u8 *)(this->IO_ADDR_W)) = byte;
|
||||
}
|
||||
|
||||
static u8 nand_read_byte(struct mtd_info *mtdinfo)
|
||||
{
|
||||
struct nand_chip *this = mtdinfo->priv;
|
||||
return (u8) (*((volatile u8 *)this->IO_ADDR_R));
|
||||
}
|
||||
|
||||
static int nand_dev_ready(struct mtd_info *mtdinfo)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
int board_nand_init(struct nand_chip *nand)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
|
||||
*((volatile u16 *)CONFIG_SYS_LATCH_ADDR) |= 0x0004;
|
||||
|
||||
/* set up pin configuration */
|
||||
/*
|
||||
* set up pin configuration - enabled 2nd output buffer's signals
|
||||
* (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
|
||||
* to use nCE signal
|
||||
*/
|
||||
gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
|
||||
gpio->pddr_timer |= 0x08;
|
||||
gpio->ppd_timer |= 0x08;
|
||||
@ -95,9 +81,6 @@ int board_nand_init(struct nand_chip *nand)
|
||||
nand->chip_delay = 50;
|
||||
nand->ecc.mode = NAND_ECC_SOFT;
|
||||
nand->cmd_ctrl = nand_hwcontrol;
|
||||
nand->read_byte = nand_read_byte;
|
||||
nand->write_byte = nand_write_byte;
|
||||
nand->dev_ready = nand_dev_ready;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o mii.o nand.o
|
||||
COBJS = $(BOARD).o nand.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
@ -1,306 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
|
||||
if (setclear) {
|
||||
gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
|
||||
gpio->par_feci2c |=
|
||||
GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO;
|
||||
} else {
|
||||
gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
|
||||
gpio->par_feci2c &=
|
||||
~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_s *info)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (info->miibase);
|
||||
int i;
|
||||
|
||||
fecp->ecr = FEC_ECR_RESET;
|
||||
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
||||
udelay(1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf("FEC_RESET_DELAY timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
volatile fec_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fec_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_s *info = dev->priv;
|
||||
int phyaddr, pass;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init)
|
||||
return info->phy_addr;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_DP83848VV:
|
||||
strcpy(info->phy_name,
|
||||
STR_ID_DP83848VV);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_DP83848VV:
|
||||
printf(STR_ID_DP83848VV);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY */
|
||||
|
||||
void mii_init(void) __attribute__((weak,alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fec_t *fecp;
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fec_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
@ -41,19 +41,21 @@ DECLARE_GLOBAL_DATA_PTR;
|
||||
static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
|
||||
{
|
||||
struct nand_chip *this = mtdinfo->priv;
|
||||
volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
|
||||
u32 nand_baseaddr = (u32) this->IO_ADDR_W;
|
||||
volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
|
||||
|
||||
if (ctrl & NAND_CTRL_CHANGE) {
|
||||
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
|
||||
IO_ADDR_W &= ~(SET_ALE | SE_CLE);
|
||||
|
||||
IO_ADDR_W &= ~(SET_ALE | SET_CLE);
|
||||
*nCE &= 0xFFFB;
|
||||
|
||||
if (ctrl & NAND_NCE)
|
||||
*nCE |= 0x0004;
|
||||
if (ctrl & NAND_CLE)
|
||||
IO_ADDR_W |= SET_CLE;
|
||||
if (ctrl & NAND_ALE)
|
||||
IO_ADDR_W |= SET_ALE;
|
||||
|
||||
at91_set_gpio_value(AT91_PIN_PD15, !(ctrl & NAND_NCE));
|
||||
this->IO_ADDR_W = (void *)IO_ADDR_W;
|
||||
|
||||
}
|
||||
@ -67,10 +69,13 @@ int board_nand_init(struct nand_chip *nand)
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
|
||||
|
||||
*((volatile u16 *)CONFIG_SYS_LATCH_ADDR) |= 0x0004;
|
||||
fbcs->csmr2 &= ~FBCS_CSMR_WP;
|
||||
|
||||
/* set up pin configuration */
|
||||
/*
|
||||
* set up pin configuration - enabled 2nd output buffer's signals
|
||||
* (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
|
||||
* to use nCE signal
|
||||
*/
|
||||
gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
|
||||
gpio->pddr_timer |= 0x08;
|
||||
gpio->ppd_timer |= 0x08;
|
||||
|
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o mii.o
|
||||
COBJS = $(BOARD).o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
@ -1,303 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
struct fec_info_s *info = (struct fec_info_s *)dev->priv;
|
||||
|
||||
if (setclear) {
|
||||
gpio->par_feci2c |=
|
||||
(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
|
||||
|
||||
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
|
||||
gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
|
||||
else
|
||||
gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA;
|
||||
} else {
|
||||
gpio->par_feci2c &=
|
||||
~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
|
||||
|
||||
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
|
||||
gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK;
|
||||
else
|
||||
gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_KSZ8041NL 0x00221512
|
||||
#define STR_ID_KSZ8041NL "KSZ8041NL"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_s *info)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (info->miibase);
|
||||
struct eth_device *dev;
|
||||
int i, miispd;
|
||||
u16 rst = 0;
|
||||
|
||||
dev = eth_get_dev();
|
||||
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
miiphy_write(dev->name, info->phy_addr, PHY_BMCR, PHY_BMCR_RESET);
|
||||
for (i = 0; i < FEC_RESET_DELAY; ++i) {
|
||||
udelay(500);
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMCR, &rst);
|
||||
if ((rst & PHY_BMCR_RESET) == 0)
|
||||
break;
|
||||
}
|
||||
if (i == FEC_RESET_DELAY)
|
||||
printf("Mii reset timeout %d\n", i);
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
volatile fec_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fec_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_s *info = dev->priv;
|
||||
int phyaddr, pass;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init)
|
||||
return info->phy_addr;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_KSZ8041NL:
|
||||
strcpy(info->phy_name,
|
||||
STR_ID_KSZ8041NL);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_KSZ8041NL:
|
||||
printf(STR_ID_KSZ8041NL);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY */
|
||||
|
||||
void mii_init(void) __attribute__ ((weak, alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fec_t *fecp;
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fec_t *) info->miibase;
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o mii.o
|
||||
COBJS = $(BOARD).o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
@ -1,324 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
struct fec_info_s *info = (struct fec_info_s *)dev->priv;
|
||||
|
||||
if (setclear) {
|
||||
gpio->par_feci2c |=
|
||||
(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
|
||||
|
||||
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
|
||||
gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
|
||||
else
|
||||
gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA;
|
||||
} else {
|
||||
gpio->par_feci2c &=
|
||||
~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
|
||||
|
||||
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
|
||||
gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK;
|
||||
else
|
||||
gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_s *info)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (info->miibase);
|
||||
struct eth_device *dev;
|
||||
int i, miispd;
|
||||
u16 rst = 0;
|
||||
|
||||
dev = eth_get_dev();
|
||||
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
miiphy_write(dev->name, info->phy_addr, PHY_BMCR, PHY_BMCR_RESET);
|
||||
for (i = 0; i < FEC_RESET_DELAY; ++i) {
|
||||
udelay(500);
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMCR, &rst);
|
||||
if ((rst & PHY_BMCR_RESET) == 0)
|
||||
break;
|
||||
}
|
||||
if (i == FEC_RESET_DELAY)
|
||||
printf("Mii reset timeout %d\n", i);
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
volatile fec_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fec_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_s *info = dev->priv;
|
||||
int phyaddr, pass;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init)
|
||||
return info->phy_addr;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_DP83848VV:
|
||||
strcpy(info->phy_name,
|
||||
STR_ID_DP83848VV);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_DP83848VV:
|
||||
printf(STR_ID_DP83848VV);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY */
|
||||
|
||||
void mii_init(void) __attribute__((weak,alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fec_t *fecp;
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fec_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o mii.o
|
||||
COBJS = $(BOARD).o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
@ -1,322 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
#include <asm/immap.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/fsl_mcdmafec.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
struct fec_info_dma *info = (struct fec_info_dma *)dev->priv;
|
||||
|
||||
if (setclear) {
|
||||
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
|
||||
gpio->par_feci2cirq |= 0xF000;
|
||||
else
|
||||
gpio->par_feci2cirq |= 0x0FC0;
|
||||
} else {
|
||||
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
|
||||
gpio->par_feci2cirq &= 0x0FFF;
|
||||
else
|
||||
gpio->par_feci2cirq &= 0xF03F;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
#define PHY_ID_BCM5222 0x00406322 /* Broadcom 5222 */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
#define STR_ID_BCM5222 "BCM5222"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_dma *info)
|
||||
{
|
||||
volatile fecdma_t *fecp = (fecdma_t *) (info->miibase);
|
||||
int i;
|
||||
|
||||
fecp->ecr = FEC_ECR_RESET;
|
||||
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
||||
udelay(1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf("FEC_RESET_DELAY timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_dma *info;
|
||||
struct eth_device *dev;
|
||||
volatile fecdma_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fecdma_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_dma *info = dev->priv;
|
||||
int phyaddr, pass, temp;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init) {
|
||||
return info->phy_addr;
|
||||
}
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
temp = 0;
|
||||
if (info->index > 0) {
|
||||
/* Some phy have multiple address, to solve the issue
|
||||
where phyno keeps starting from 0, check the
|
||||
previous phy address if both miibase are the same. */
|
||||
if (info->miibase == (info->next)->miibase) {
|
||||
temp = (info->next)->phy_addr + 1;
|
||||
}
|
||||
}
|
||||
|
||||
for (phyno = temp; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_BCM5222:
|
||||
strcpy(info->phy_name, STR_ID_BCM5222);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_BCM5222:
|
||||
printf(STR_ID_BCM5222);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY */
|
||||
|
||||
void mii_init(void) __attribute__ ((weak, alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fecdma_t *fecp;
|
||||
struct fec_info_dma *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fecdma_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o mii.o
|
||||
COBJS = $(BOARD).o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
@ -1,322 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
#include <asm/immap.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/fsl_mcdmafec.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
struct fec_info_dma *info = (struct fec_info_dma *)dev->priv;
|
||||
|
||||
if (setclear) {
|
||||
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
|
||||
gpio->par_feci2cirq |= 0xF000;
|
||||
else
|
||||
gpio->par_feci2cirq |= 0x0FC0;
|
||||
} else {
|
||||
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
|
||||
gpio->par_feci2cirq &= 0x0FFF;
|
||||
else
|
||||
gpio->par_feci2cirq &= 0xF03F;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
#define PHY_ID_BCM5222 0x00406322 /* Broadcom 5222 */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
#define STR_ID_BCM5222 "BCM5222"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_dma *info)
|
||||
{
|
||||
volatile fecdma_t *fecp = (fecdma_t *) (info->miibase);
|
||||
int i;
|
||||
|
||||
fecp->ecr = FEC_ECR_RESET;
|
||||
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
||||
udelay(1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf("FEC_RESET_DELAY timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_dma *info;
|
||||
struct eth_device *dev;
|
||||
volatile fecdma_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fecdma_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_dma *info = dev->priv;
|
||||
int phyaddr, pass, temp;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init) {
|
||||
return info->phy_addr;
|
||||
}
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
temp = 0;
|
||||
if (info->index > 0) {
|
||||
/* Some phy have multiple address, to solve the issue
|
||||
where phyno keeps starting from 0, check the
|
||||
previous phy address if both miibase are the same. */
|
||||
if (info->miibase == (info->next)->miibase) {
|
||||
temp = (info->next)->phy_addr + 1;
|
||||
}
|
||||
}
|
||||
|
||||
for (phyno = temp; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_BCM5222:
|
||||
strcpy(info->phy_name, STR_ID_BCM5222);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_BCM5222:
|
||||
printf(STR_ID_BCM5222);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY */
|
||||
|
||||
void mii_init(void) __attribute__ ((weak, alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fecdma_t *fecp;
|
||||
struct fec_info_dma *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fecdma_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
@ -439,8 +439,8 @@ int board_early_init_r(void)
|
||||
*/
|
||||
|
||||
/* Flush d-cache and invalidate i-cache of any FLASH data */
|
||||
flush_dcache();
|
||||
invalidate_icache();
|
||||
flush_dcache();
|
||||
invalidate_icache();
|
||||
|
||||
/* invalidate existing TLB entry for flash + promjet */
|
||||
disable_tlb(flash_esel);
|
||||
@ -646,7 +646,7 @@ int board_eth_init(bd_t *bis)
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
|
||||
struct pci_controller *hose);
|
||||
struct pci_controller *hose);
|
||||
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
|
@ -488,7 +488,7 @@ int board_eth_init(bd_t *bis)
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
|
||||
struct pci_controller *hose);
|
||||
struct pci_controller *hose);
|
||||
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
|
@ -479,7 +479,7 @@ int last_stage_init(void)
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
|
||||
struct pci_controller *hose);
|
||||
struct pci_controller *hose);
|
||||
|
||||
void ft_pci_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
|
@ -496,7 +496,7 @@ pci_init_board(void)
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
|
||||
struct pci_controller *hose);
|
||||
struct pci_controller *hose);
|
||||
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
|
@ -362,8 +362,8 @@ int board_early_init_r(void)
|
||||
*/
|
||||
|
||||
/* Flush d-cache and invalidate i-cache of any FLASH data */
|
||||
flush_dcache();
|
||||
invalidate_icache();
|
||||
flush_dcache();
|
||||
invalidate_icache();
|
||||
|
||||
/* invalidate existing TLB entry for flash + promjet */
|
||||
disable_tlb(flash_esel);
|
||||
@ -560,7 +560,7 @@ int board_eth_init(bd_t *bis)
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
|
||||
struct pci_controller *hose);
|
||||
struct pci_controller *hose);
|
||||
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
|
@ -403,7 +403,7 @@ void pci_init_board(void)
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
|
||||
struct pci_controller *hose);
|
||||
struct pci_controller *hose);
|
||||
|
||||
void
|
||||
ft_board_setup(void *blob, bd_t *bd)
|
||||
|
@ -47,12 +47,12 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
|
||||
}
|
||||
|
||||
typedef struct {
|
||||
u32 datarate_mhz_low;
|
||||
u32 datarate_mhz_high;
|
||||
u32 n_ranks;
|
||||
u32 clk_adjust;
|
||||
u32 cpo;
|
||||
u32 write_data_delay;
|
||||
u32 datarate_mhz_low;
|
||||
u32 datarate_mhz_high;
|
||||
u32 n_ranks;
|
||||
u32 clk_adjust;
|
||||
u32 cpo;
|
||||
u32 write_data_delay;
|
||||
} board_specific_parameters_t;
|
||||
|
||||
/* XXX: these values need to be checked for all interleaving modes. */
|
||||
@ -84,7 +84,7 @@ const board_specific_parameters_t board_specific_parameters[2][16] = {
|
||||
|
||||
{
|
||||
/* memory controller 1 */
|
||||
/* lo| hi| num| clk| cpo|wrdata */
|
||||
/* lo| hi| num| clk| cpo|wrdata */
|
||||
/* mhz| mhz|ranks|adjst| | delay */
|
||||
{ 0, 333, 4, 7, 7, 3},
|
||||
{334, 400, 4, 7, 9, 3},
|
||||
@ -129,7 +129,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
|
||||
if (i&1) { /* odd CS */
|
||||
popts->cs_local_opts[i].odt_rd_cfg = 0;
|
||||
popts->cs_local_opts[i].odt_wr_cfg = 0;
|
||||
} else { /* even CS */
|
||||
} else { /* even CS */
|
||||
if ((CONFIG_DIMM_SLOTS_PER_CTLR == 2) &&
|
||||
(pdimm[i/2].n_ranks != 0)) {
|
||||
popts->cs_local_opts[i].odt_rd_cfg = 3;
|
||||
|
@ -249,7 +249,7 @@ void pci_init_board(void)
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
|
||||
struct pci_controller *hose);
|
||||
struct pci_controller *hose);
|
||||
|
||||
void
|
||||
ft_board_setup(void *blob, bd_t *bd)
|
||||
|
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o flash.o mii.o
|
||||
COBJS = $(BOARD).o flash.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
303
board/idmr/mii.c
303
board/idmr/mii.c
@ -1,303 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
if (setclear) {
|
||||
/* Enable Ethernet pins */
|
||||
mbar_writeByte(MCF_GPIO_PAR_FECI2C, CONFIG_SYS_FECI2C);
|
||||
} else {
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
#define STR_ID_KS8721BL "KS8721BL"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_s *info)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (info->miibase);
|
||||
int i;
|
||||
|
||||
fecp->ecr = FEC_ECR_RESET;
|
||||
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
||||
udelay(1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf("FEC_RESET_DELAY timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
volatile fec_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fec_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_s *info = dev->priv;
|
||||
int phyaddr, pass;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init)
|
||||
return info->phy_addr;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_KS8721BL:
|
||||
strcpy(info->phy_name,
|
||||
STR_ID_KS8721BL);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_KS8721BL:
|
||||
printf(STR_ID_KS8721BL);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY */
|
||||
|
||||
void mii_init(void) __attribute__((weak,alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fec_t *fecp;
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fec_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
@ -45,152 +45,152 @@ extern int ivm_read_eeprom (void);
|
||||
const iop_conf_t iop_conf_tab[4][32] = {
|
||||
|
||||
/* Port A */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PA31 */ { 0, 0, 0, 0, 0, 0 }, /* PA31 */
|
||||
/* PA30 */ { 0, 0, 0, 0, 0, 0 }, /* PA30 */
|
||||
/* PA29 */ { 0, 0, 0, 0, 0, 0 }, /* PA29 */
|
||||
/* PA28 */ { 0, 0, 0, 0, 0, 0 }, /* PA28 */
|
||||
/* PA27 */ { 0, 0, 0, 0, 0, 0 }, /* PA27 */
|
||||
/* PA26 */ { 0, 0, 0, 0, 0, 0 }, /* PA26 */
|
||||
/* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
|
||||
/* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
|
||||
/* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
|
||||
/* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
|
||||
/* PA21 */ { 0, 0, 0, 0, 0, 0 }, /* PA21 */
|
||||
/* PA20 */ { 0, 0, 0, 0, 0, 0 }, /* PA20 */
|
||||
/* PA19 */ { 0, 0, 0, 0, 0, 0 }, /* PA19 */
|
||||
/* PA18 */ { 0, 0, 0, 0, 0, 0 }, /* PA18 */
|
||||
/* PA17 */ { 0, 0, 0, 0, 0, 0 }, /* PA17 */
|
||||
/* PA16 */ { 0, 0, 0, 0, 0, 0 }, /* PA16 */
|
||||
/* PA15 */ { 0, 0, 0, 0, 0, 0 }, /* PA15 */
|
||||
/* PA14 */ { 0, 0, 0, 0, 0, 0 }, /* PA14 */
|
||||
/* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
|
||||
/* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
|
||||
/* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
|
||||
/* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
|
||||
/* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TxD */
|
||||
/* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RxD */
|
||||
/* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
|
||||
/* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
|
||||
/* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
|
||||
/* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
|
||||
/* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
|
||||
/* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
|
||||
/* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
|
||||
/* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PA31 */ { 0, 0, 0, 0, 0, 0 }, /* PA31 */
|
||||
/* PA30 */ { 0, 0, 0, 0, 0, 0 }, /* PA30 */
|
||||
/* PA29 */ { 0, 0, 0, 0, 0, 0 }, /* PA29 */
|
||||
/* PA28 */ { 0, 0, 0, 0, 0, 0 }, /* PA28 */
|
||||
/* PA27 */ { 0, 0, 0, 0, 0, 0 }, /* PA27 */
|
||||
/* PA26 */ { 0, 0, 0, 0, 0, 0 }, /* PA26 */
|
||||
/* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
|
||||
/* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
|
||||
/* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
|
||||
/* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
|
||||
/* PA21 */ { 0, 0, 0, 0, 0, 0 }, /* PA21 */
|
||||
/* PA20 */ { 0, 0, 0, 0, 0, 0 }, /* PA20 */
|
||||
/* PA19 */ { 0, 0, 0, 0, 0, 0 }, /* PA19 */
|
||||
/* PA18 */ { 0, 0, 0, 0, 0, 0 }, /* PA18 */
|
||||
/* PA17 */ { 0, 0, 0, 0, 0, 0 }, /* PA17 */
|
||||
/* PA16 */ { 0, 0, 0, 0, 0, 0 }, /* PA16 */
|
||||
/* PA15 */ { 0, 0, 0, 0, 0, 0 }, /* PA15 */
|
||||
/* PA14 */ { 0, 0, 0, 0, 0, 0 }, /* PA14 */
|
||||
/* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
|
||||
/* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
|
||||
/* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
|
||||
/* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
|
||||
/* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TxD */
|
||||
/* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RxD */
|
||||
/* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
|
||||
/* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
|
||||
/* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
|
||||
/* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
|
||||
/* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
|
||||
/* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
|
||||
/* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
|
||||
/* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
|
||||
},
|
||||
|
||||
/* Port B */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PB31 */ { 0, 0, 0, 0, 0, 0 }, /* PB31 */
|
||||
/* PB30 */ { 0, 0, 0, 0, 0, 0 }, /* PB30 */
|
||||
/* PB29 */ { 0, 0, 0, 0, 0, 0 }, /* PB29 */
|
||||
/* PB28 */ { 0, 0, 0, 0, 0, 0 }, /* PB28 */
|
||||
/* PB27 */ { 0, 0, 0, 0, 0, 0 }, /* PB27 */
|
||||
/* PB26 */ { 0, 0, 0, 0, 0, 0 }, /* PB26 */
|
||||
/* PB25 */ { 0, 0, 0, 0, 0, 0 }, /* PB25 */
|
||||
/* PB24 */ { 0, 0, 0, 0, 0, 0 }, /* PB24 */
|
||||
/* PB23 */ { 0, 0, 0, 0, 0, 0 }, /* PB23 */
|
||||
/* PB22 */ { 0, 0, 0, 0, 0, 0 }, /* PB22 */
|
||||
/* PB21 */ { 0, 0, 0, 0, 0, 0 }, /* PB21 */
|
||||
/* PB20 */ { 0, 0, 0, 0, 0, 0 }, /* PB20 */
|
||||
/* PB19 */ { 0, 0, 0, 0, 0, 0 }, /* PB19 */
|
||||
/* PB18 */ { 0, 0, 0, 0, 0, 0 }, /* PB18 */
|
||||
/* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PB31 */ { 0, 0, 0, 0, 0, 0 }, /* PB31 */
|
||||
/* PB30 */ { 0, 0, 0, 0, 0, 0 }, /* PB30 */
|
||||
/* PB29 */ { 0, 0, 0, 0, 0, 0 }, /* PB29 */
|
||||
/* PB28 */ { 0, 0, 0, 0, 0, 0 }, /* PB28 */
|
||||
/* PB27 */ { 0, 0, 0, 0, 0, 0 }, /* PB27 */
|
||||
/* PB26 */ { 0, 0, 0, 0, 0, 0 }, /* PB26 */
|
||||
/* PB25 */ { 0, 0, 0, 0, 0, 0 }, /* PB25 */
|
||||
/* PB24 */ { 0, 0, 0, 0, 0, 0 }, /* PB24 */
|
||||
/* PB23 */ { 0, 0, 0, 0, 0, 0 }, /* PB23 */
|
||||
/* PB22 */ { 0, 0, 0, 0, 0, 0 }, /* PB22 */
|
||||
/* PB21 */ { 0, 0, 0, 0, 0, 0 }, /* PB21 */
|
||||
/* PB20 */ { 0, 0, 0, 0, 0, 0 }, /* PB20 */
|
||||
/* PB19 */ { 0, 0, 0, 0, 0, 0 }, /* PB19 */
|
||||
/* PB18 */ { 0, 0, 0, 0, 0, 0 }, /* PB18 */
|
||||
/* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
|
||||
},
|
||||
|
||||
/* Port C */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
|
||||
/* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
|
||||
/* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
|
||||
/* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
|
||||
/* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
|
||||
/* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
|
||||
/* PC25 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 RxClk */
|
||||
/* PC24 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 TxClk */
|
||||
/* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
|
||||
/* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */
|
||||
/* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */
|
||||
/* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
|
||||
/* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */
|
||||
/* PC18 */ { 0, 0, 0, 0, 0, 0 }, /* PC18 */
|
||||
/* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
|
||||
/* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
|
||||
/* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
|
||||
/* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
|
||||
/* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
|
||||
/* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
|
||||
/* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
|
||||
/* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
|
||||
/* PC9 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: CTS */
|
||||
/* PC8 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: CD */
|
||||
/* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
|
||||
/* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
|
||||
/* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
|
||||
/* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
|
||||
/* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
|
||||
/* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
|
||||
/* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
|
||||
/* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
|
||||
/* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
|
||||
/* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
|
||||
/* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
|
||||
/* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
|
||||
/* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
|
||||
/* PC25 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 RxClk */
|
||||
/* PC24 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 TxClk */
|
||||
/* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
|
||||
/* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */
|
||||
/* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */
|
||||
/* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
|
||||
/* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */
|
||||
/* PC18 */ { 0, 0, 0, 0, 0, 0 }, /* PC18 */
|
||||
/* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
|
||||
/* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
|
||||
/* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
|
||||
/* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
|
||||
/* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
|
||||
/* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
|
||||
/* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
|
||||
/* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
|
||||
/* PC9 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: CTS */
|
||||
/* PC8 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: CD */
|
||||
/* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
|
||||
/* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
|
||||
/* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
|
||||
/* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
|
||||
/* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
|
||||
/* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
|
||||
/* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
|
||||
/* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
|
||||
},
|
||||
|
||||
/* Port D */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PD31 */ { 0, 0, 0, 0, 0, 0 }, /* PD31 */
|
||||
/* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */
|
||||
/* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
|
||||
/* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
|
||||
/* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
|
||||
/* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
|
||||
/* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
|
||||
/* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
|
||||
/* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
|
||||
/* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: RXD */
|
||||
/* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4: TXD */
|
||||
/* PD20 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4: RTS */
|
||||
/* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
|
||||
/* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
|
||||
/* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
|
||||
/* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PD31 */ { 0, 0, 0, 0, 0, 0 }, /* PD31 */
|
||||
/* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */
|
||||
/* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
|
||||
/* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
|
||||
/* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
|
||||
/* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
|
||||
/* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
|
||||
/* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
|
||||
/* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
|
||||
/* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: RXD */
|
||||
/* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4: TXD */
|
||||
/* PD20 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4: RTS */
|
||||
/* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
|
||||
/* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
|
||||
/* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
|
||||
/* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
|
||||
#if defined(CONFIG_HARD_I2C)
|
||||
/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
|
||||
/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
|
||||
/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
|
||||
/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
|
||||
#else
|
||||
/* PD15 */ { 1, 0, 0, 0, 1, 1 }, /* PD15 */
|
||||
/* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* PD14 */
|
||||
/* PD15 */ { 1, 0, 0, 0, 1, 1 }, /* PD15 */
|
||||
/* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* PD14 */
|
||||
#endif
|
||||
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
|
||||
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
|
||||
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
|
||||
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
|
||||
/* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
|
||||
/* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
|
||||
/* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
|
||||
/* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
|
||||
/* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
|
||||
/* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
|
||||
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
|
||||
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
|
||||
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
|
||||
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
|
||||
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
|
||||
/* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
|
||||
/* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
|
||||
/* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
|
||||
/* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
|
||||
/* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
|
||||
/* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
|
||||
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
||||
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
|
||||
}
|
||||
};
|
||||
|
||||
@ -309,10 +309,10 @@ int hush_init_var (void)
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
|
||||
extern int fdt_set_node_and_value (void *blob,
|
||||
char *nodename,
|
||||
char *regname,
|
||||
void *var,
|
||||
int size);
|
||||
char *nodename,
|
||||
char *regname,
|
||||
void *var,
|
||||
int size);
|
||||
|
||||
/*
|
||||
* update "memory" property in the blob
|
||||
|
@ -151,10 +151,10 @@ int hush_init_var (void)
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
|
||||
extern int fdt_set_node_and_value (void *blob,
|
||||
char *nodename,
|
||||
char *regname,
|
||||
void *var,
|
||||
int size);
|
||||
char *nodename,
|
||||
char *regname,
|
||||
void *var,
|
||||
int size);
|
||||
|
||||
/*
|
||||
* update "memory" property in the blob
|
||||
|
@ -530,7 +530,7 @@ int last_stage_init(void)
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
|
||||
struct pci_controller *hose);
|
||||
struct pci_controller *hose);
|
||||
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
|
@ -322,7 +322,7 @@ void pci_init_board(void)
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
|
||||
struct pci_controller *hose);
|
||||
struct pci_controller *hose);
|
||||
|
||||
void ft_board_setup (void *blob, bd_t *bd)
|
||||
{
|
||||
|
@ -28,7 +28,7 @@ endif
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o flash.o ../tqm8xx/load_sernum_ethaddr.o
|
||||
COBJS = $(BOARD).o ../tqm8xx/load_sernum_ethaddr.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
@ -1,497 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2001, 2002
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Flash Routines for AMD devices on the TQM8260 board
|
||||
*
|
||||
*--------------------------------------------------------------------
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <mpc8xx.h>
|
||||
|
||||
#define V_ULONG(a) (*(volatile unsigned long *)( a ))
|
||||
#define V_BYTE(a) (*(volatile unsigned char *)( a ))
|
||||
|
||||
|
||||
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
void flash_reset (void)
|
||||
{
|
||||
if (flash_info[0].flash_id != FLASH_UNKNOWN) {
|
||||
V_ULONG (flash_info[0].start[0]) = 0x00F000F0;
|
||||
V_ULONG (flash_info[0].start[0] + 4) = 0x00F000F0;
|
||||
}
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
ulong flash_get_size (ulong baseaddr, flash_info_t * info)
|
||||
{
|
||||
short i;
|
||||
unsigned long flashtest_h, flashtest_l;
|
||||
|
||||
/* Write auto select command sequence and test FLASH answer */
|
||||
V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00AA00AA;
|
||||
V_ULONG (baseaddr + ((ulong) 0x02AA << 3)) = 0x00550055;
|
||||
V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00900090;
|
||||
V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00AA00AA;
|
||||
V_ULONG (baseaddr + 4 + ((ulong) 0x02AA << 3)) = 0x00550055;
|
||||
V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00900090;
|
||||
|
||||
flashtest_h = V_ULONG (baseaddr); /* manufacturer ID */
|
||||
flashtest_l = V_ULONG (baseaddr + 4);
|
||||
|
||||
switch ((int) flashtest_h) {
|
||||
case AMD_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_AMD;
|
||||
break;
|
||||
case FUJ_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_FUJ;
|
||||
break;
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
info->sector_count = 0;
|
||||
info->size = 0;
|
||||
return (0); /* no or unknown flash */
|
||||
}
|
||||
|
||||
flashtest_h = V_ULONG (baseaddr + 8); /* device ID */
|
||||
flashtest_l = V_ULONG (baseaddr + 12);
|
||||
if (flashtest_h != flashtest_l) {
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
} else {
|
||||
switch (flashtest_h) {
|
||||
case AMD_ID_LV800T:
|
||||
info->flash_id += FLASH_AM800T;
|
||||
info->sector_count = 19;
|
||||
info->size = 0x00400000;
|
||||
break; /* 4 * 1 MB = 4 MB */
|
||||
case AMD_ID_LV800B:
|
||||
info->flash_id += FLASH_AM800B;
|
||||
info->sector_count = 19;
|
||||
info->size = 0x00400000;
|
||||
break; /* 4 * 1 MB = 4 MB */
|
||||
case AMD_ID_LV160T:
|
||||
info->flash_id += FLASH_AM160T;
|
||||
info->sector_count = 35;
|
||||
info->size = 0x00800000;
|
||||
break; /* 4 * 2 MB = 8 MB */
|
||||
case AMD_ID_LV160B:
|
||||
info->flash_id += FLASH_AM160B;
|
||||
info->sector_count = 35;
|
||||
info->size = 0x00800000;
|
||||
break; /* 4 * 2 MB = 8 MB */
|
||||
case AMD_ID_DL322T:
|
||||
info->flash_id += FLASH_AMDL322T;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x01000000;
|
||||
break; /* 4 * 4 MB = 16 MB */
|
||||
case AMD_ID_DL322B:
|
||||
info->flash_id += FLASH_AMDL322B;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x01000000;
|
||||
break; /* 4 * 4 MB = 16 MB */
|
||||
case AMD_ID_DL323T:
|
||||
info->flash_id += FLASH_AMDL323T;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x01000000;
|
||||
break; /* 4 * 4 MB = 16 MB */
|
||||
case AMD_ID_DL323B:
|
||||
info->flash_id += FLASH_AMDL323B;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x01000000;
|
||||
break; /* 4 * 4 MB = 16 MB */
|
||||
case AMD_ID_LV640U:
|
||||
info->flash_id += FLASH_AM640U;
|
||||
info->sector_count = 128;
|
||||
info->size = 0x02000000;
|
||||
break; /* 4 * 8 MB = 32 MB */
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
return (0); /* no or unknown flash */
|
||||
}
|
||||
}
|
||||
|
||||
if (flashtest_h == AMD_ID_LV640U) {
|
||||
|
||||
/* set up sector start adress table (uniform sector type) */
|
||||
for (i = 0; i < info->sector_count; i++)
|
||||
info->start[i] = baseaddr + (i * 0x00040000);
|
||||
|
||||
} else if (info->flash_id & FLASH_BTYPE) {
|
||||
|
||||
/* set up sector start adress table (bottom sector type) */
|
||||
info->start[0] = baseaddr + 0x00000000;
|
||||
info->start[1] = baseaddr + 0x00010000;
|
||||
info->start[2] = baseaddr + 0x00018000;
|
||||
info->start[3] = baseaddr + 0x00020000;
|
||||
for (i = 4; i < info->sector_count; i++) {
|
||||
info->start[i] = baseaddr + (i * 0x00040000) - 0x000C0000;
|
||||
}
|
||||
|
||||
} else {
|
||||
|
||||
/* set up sector start adress table (top sector type) */
|
||||
i = info->sector_count - 1;
|
||||
info->start[i--] = baseaddr + info->size - 0x00010000;
|
||||
info->start[i--] = baseaddr + info->size - 0x00018000;
|
||||
info->start[i--] = baseaddr + info->size - 0x00020000;
|
||||
for (; i >= 0; i--) {
|
||||
info->start[i] = baseaddr + i * 0x00040000;
|
||||
}
|
||||
}
|
||||
|
||||
/* check for protected sectors */
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
|
||||
if ((V_ULONG (info->start[i] + 16) & 0x00010001) ||
|
||||
(V_ULONG (info->start[i] + 20) & 0x00010001)) {
|
||||
info->protect[i] = 1; /* D0 = 1 if protected */
|
||||
} else {
|
||||
info->protect[i] = 0;
|
||||
}
|
||||
}
|
||||
|
||||
flash_reset ();
|
||||
return (info->size);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
unsigned long size_b0 = 0;
|
||||
int i;
|
||||
|
||||
/* Init: no FLASHes known */
|
||||
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
}
|
||||
|
||||
/* Static FLASH Bank configuration here (only one bank) */
|
||||
|
||||
size_b0 = flash_get_size (CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
|
||||
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
|
||||
size_b0, size_b0 >> 20);
|
||||
}
|
||||
|
||||
/*
|
||||
* protect monitor and environment sectors
|
||||
*/
|
||||
|
||||
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
|
||||
flash_protect (FLAG_PROTECT_SET,
|
||||
CONFIG_SYS_MONITOR_BASE,
|
||||
CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
|
||||
&flash_info[0]);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
|
||||
# ifndef CONFIG_ENV_SIZE
|
||||
# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
|
||||
# endif
|
||||
flash_protect (FLAG_PROTECT_SET,
|
||||
CONFIG_ENV_ADDR,
|
||||
CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
|
||||
&flash_info[0]);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR_REDUND)
|
||||
flash_protect (FLAG_PROTECT_SET,
|
||||
CONFIG_ENV_ADDR_REDUND,
|
||||
CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1,
|
||||
&flash_info[0]);
|
||||
#endif
|
||||
|
||||
return (size_b0);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
void flash_print_info (flash_info_t * info)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("missing or unknown FLASH type\n");
|
||||
return;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) {
|
||||
case FLASH_MAN_AMD:
|
||||
printf ("AMD ");
|
||||
break;
|
||||
case FLASH_MAN_FUJ:
|
||||
printf ("FUJITSU ");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Vendor ");
|
||||
break;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case FLASH_AM800T:
|
||||
printf ("29LV800T (8 M, top sector)\n");
|
||||
break;
|
||||
case FLASH_AM800B:
|
||||
printf ("29LV800T (8 M, bottom sector)\n");
|
||||
break;
|
||||
case FLASH_AM160T:
|
||||
printf ("29LV160T (16 M, top sector)\n");
|
||||
break;
|
||||
case FLASH_AM160B:
|
||||
printf ("29LV160B (16 M, bottom sector)\n");
|
||||
break;
|
||||
case FLASH_AMDL322T:
|
||||
printf ("29DL322T (32 M, top sector)\n");
|
||||
break;
|
||||
case FLASH_AMDL322B:
|
||||
printf ("29DL322B (32 M, bottom sector)\n");
|
||||
break;
|
||||
case FLASH_AMDL323T:
|
||||
printf ("29DL323T (32 M, top sector)\n");
|
||||
break;
|
||||
case FLASH_AMDL323B:
|
||||
printf ("29DL323B (32 M, bottom sector)\n");
|
||||
break;
|
||||
case FLASH_AM640U:
|
||||
printf ("29LV640D (64 M, uniform sector)\n");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Chip Type\n");
|
||||
break;
|
||||
}
|
||||
|
||||
printf (" Size: %ld MB in %d Sectors\n",
|
||||
info->size >> 20, info->sector_count);
|
||||
|
||||
printf (" Sector Start Addresses:");
|
||||
for (i = 0; i < info->sector_count; ++i) {
|
||||
if ((i % 5) == 0)
|
||||
printf ("\n ");
|
||||
printf (" %08lX%s",
|
||||
info->start[i],
|
||||
info->protect[i] ? " (RO)" : " "
|
||||
);
|
||||
}
|
||||
printf ("\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
int flash_erase (flash_info_t * info, int s_first, int s_last)
|
||||
{
|
||||
int flag, prot, sect, l_sect;
|
||||
ulong start, now, last;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("- missing\n");
|
||||
} else {
|
||||
printf ("- no sectors to erase\n");
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect = s_first; sect <= s_last; sect++) {
|
||||
if (info->protect[sect])
|
||||
prot++;
|
||||
}
|
||||
|
||||
if (prot) {
|
||||
printf ("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
} else {
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
l_sect = -1;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts ();
|
||||
|
||||
V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA;
|
||||
V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055;
|
||||
V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00800080;
|
||||
V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA;
|
||||
V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055;
|
||||
V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA;
|
||||
V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055;
|
||||
V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00800080;
|
||||
V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA;
|
||||
V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055;
|
||||
udelay (1000);
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect <= s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
V_ULONG (info->start[sect]) = 0x00300030;
|
||||
V_ULONG (info->start[sect] + 4) = 0x00300030;
|
||||
l_sect = sect;
|
||||
}
|
||||
}
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts ();
|
||||
|
||||
/* wait at least 80us - let's wait 1 ms */
|
||||
udelay (1000);
|
||||
|
||||
/*
|
||||
* We wait for the last triggered sector
|
||||
*/
|
||||
if (l_sect < 0)
|
||||
goto DONE;
|
||||
|
||||
start = get_timer (0);
|
||||
last = start;
|
||||
while ((V_ULONG (info->start[l_sect]) & 0x00800080) != 0x00800080 ||
|
||||
(V_ULONG (info->start[l_sect] + 4) & 0x00800080) != 0x00800080)
|
||||
{
|
||||
if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
|
||||
printf ("Timeout\n");
|
||||
return 1;
|
||||
}
|
||||
/* show that we're waiting */
|
||||
if ((now - last) > 1000) { /* every second */
|
||||
serial_putc ('.');
|
||||
last = now;
|
||||
}
|
||||
}
|
||||
|
||||
DONE:
|
||||
/* reset to read mode */
|
||||
flash_reset ();
|
||||
|
||||
printf (" done\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int write_dword (flash_info_t *, ulong, unsigned char *);
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
|
||||
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong dp;
|
||||
static unsigned char bb[8];
|
||||
int i, l, rc, cc = cnt;
|
||||
|
||||
dp = (addr & ~7); /* get lower dword aligned address */
|
||||
|
||||
/*
|
||||
* handle unaligned start bytes
|
||||
*/
|
||||
if ((l = addr - dp) != 0) {
|
||||
for (i = 0; i < 8; i++)
|
||||
bb[i] = (i < l || (i - l) >= cc) ? V_BYTE (dp + i) : *src++;
|
||||
if ((rc = write_dword (info, dp, bb)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
dp += 8;
|
||||
cc -= 8 - l;
|
||||
}
|
||||
|
||||
/*
|
||||
* handle word aligned part
|
||||
*/
|
||||
while (cc >= 8) {
|
||||
if ((rc = write_dword (info, dp, src)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
dp += 8;
|
||||
src += 8;
|
||||
cc -= 8;
|
||||
}
|
||||
|
||||
if (cc <= 0) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
for (i = 0; i < 8; i++) {
|
||||
bb[i] = (i < cc) ? *src++ : V_BYTE (dp + i);
|
||||
}
|
||||
return (write_dword (info, dp, bb));
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a dword to Flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata)
|
||||
{
|
||||
ulong start, cl, ch;
|
||||
int flag, i;
|
||||
|
||||
for (ch = 0, i = 0; i < 4; i++)
|
||||
ch = (ch << 8) + *pdata++; /* high word */
|
||||
for (cl = 0, i = 0; i < 4; i++)
|
||||
cl = (cl << 8) + *pdata++; /* low word */
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*((vu_long *) dest) & ch) != ch
|
||||
|| (*((vu_long *) (dest + 4)) & cl) != cl) {
|
||||
return (2);
|
||||
}
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts ();
|
||||
|
||||
V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA;
|
||||
V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055;
|
||||
V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00A000A0;
|
||||
V_ULONG (dest) = ch;
|
||||
V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA;
|
||||
V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055;
|
||||
V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00A000A0;
|
||||
V_ULONG (dest + 4) = cl;
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts ();
|
||||
|
||||
/* data polling for D7 */
|
||||
start = get_timer (0);
|
||||
while (((V_ULONG (dest) & 0x00800080) != (ch & 0x00800080)) ||
|
||||
((V_ULONG (dest + 4) & 0x00800080) != (cl & 0x00800080))) {
|
||||
if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
return (0);
|
||||
}
|
@ -23,7 +23,7 @@
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
@ -702,7 +702,7 @@ void pci_init_board (void)
|
||||
|
||||
#ifdef CONFIG_OF_BOARD_SETUP
|
||||
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
|
||||
struct pci_controller *hose);
|
||||
struct pci_controller *hose);
|
||||
|
||||
void ft_board_setup (void *blob, bd_t *bd)
|
||||
{
|
||||
|
@ -37,10 +37,6 @@
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
void flash__init (void);
|
||||
void ether__init (void);
|
||||
void peripheral_power_enable (void);
|
||||
|
||||
#if defined(CONFIG_SHOW_BOOT_PROGRESS)
|
||||
void show_boot_progress(int progress)
|
||||
{
|
||||
@ -82,8 +78,6 @@ int board_init (void)
|
||||
|
||||
icache_enable ();
|
||||
|
||||
flash__init ();
|
||||
ether__init ();
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -94,22 +88,6 @@ int misc_init_r (void)
|
||||
return (0);
|
||||
}
|
||||
|
||||
/******************************
|
||||
Routine:
|
||||
Description:
|
||||
******************************/
|
||||
void flash__init (void)
|
||||
{
|
||||
}
|
||||
/*************************************************************
|
||||
Routine:ether__init
|
||||
Description: take the Ethernet controller out of reset and wait
|
||||
for the EEPROM load to complete.
|
||||
*************************************************************/
|
||||
void ether__init (void)
|
||||
{
|
||||
}
|
||||
|
||||
/******************************
|
||||
Routine:
|
||||
Description:
|
||||
|
@ -46,8 +46,6 @@
|
||||
# define DFC_DEBUG3(fmt, args...)
|
||||
#endif
|
||||
|
||||
#define MIN(x, y) ((x < y) ? x : y)
|
||||
|
||||
/* These really don't belong here, as they are specific to the NAND Model */
|
||||
static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
|
||||
|
||||
|
@ -42,7 +42,7 @@ COBJS-y += s_record.o
|
||||
COBJS-y += serial.o
|
||||
COBJS-y += xyzModem.o
|
||||
|
||||
#core command
|
||||
# core command
|
||||
COBJS-y += cmd_boot.o
|
||||
COBJS-y += cmd_bootm.o
|
||||
COBJS-y += cmd_nvedit.o
|
||||
@ -148,6 +148,9 @@ endif
|
||||
COBJS-$(CONFIG_CMD_XIMG) += cmd_ximg.o
|
||||
COBJS-$(CONFIG_YAFFS2) += cmd_yaffs2.o
|
||||
COBJS-$(CONFIG_VFD) += cmd_vfd.o
|
||||
|
||||
# others
|
||||
COBJS-$(CONFIG_DDR_SPD) += ddr_spd.o
|
||||
COBJS-$(CONFIG_CMD_DOC) += docecc.o
|
||||
COBJS-y += flash.o
|
||||
COBJS-y += kgdb.o
|
||||
@ -155,7 +158,7 @@ COBJS-$(CONFIG_LCD) += lcd.o
|
||||
COBJS-$(CONFIG_LYNXKDI) += lynxkdi.o
|
||||
COBJS-$(CONFIG_UPDATE_TFTP) += update.o
|
||||
COBJS-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
|
||||
COBJS-$(CONFIG_DDR_SPD) += ddr_spd.o
|
||||
|
||||
|
||||
COBJS := $(sort $(COBJS-y))
|
||||
SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
|
@ -13,10 +13,6 @@
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#ifndef MAX
|
||||
#define MAX(a,b) ((a) > (b) ? (a) : (b))
|
||||
#endif
|
||||
|
||||
extern void show_regs __P ((struct pt_regs *));
|
||||
extern int run_command __P ((const char *, int));
|
||||
extern char console_buffer[];
|
||||
|
@ -23,10 +23,6 @@
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
#endif
|
||||
|
||||
#ifndef MAX
|
||||
#define MAX(a,b) ((a) > (b) ? (a) : (b))
|
||||
#endif
|
||||
|
||||
int valid_elf_image (unsigned long addr);
|
||||
unsigned long load_elf_image (unsigned long addr);
|
||||
|
||||
|
@ -249,7 +249,6 @@ int do_i2c_mm ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
return mod_i2c_mem (cmdtp, 1, flag, argc, argv);
|
||||
}
|
||||
|
||||
|
||||
int do_i2c_nm ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
return mod_i2c_mem (cmdtp, 0, flag, argc, argv);
|
||||
@ -339,7 +338,6 @@ int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
/* Calculate a CRC on memory
|
||||
*
|
||||
* Syntax:
|
||||
@ -409,7 +407,6 @@ int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/* Modify memory.
|
||||
*
|
||||
* Syntax:
|
||||
@ -587,7 +584,6 @@ int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Syntax:
|
||||
* iloop {i2c_chip} {addr}{.0, .1, .2} [{length}] [{delay}]
|
||||
@ -658,7 +654,6 @@ int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* The SDRAM command is separately configured because many
|
||||
* (most?) embedded boards don't use SDRAM DIMMs.
|
||||
@ -1601,4 +1596,3 @@ int i2x_mux_select_mux(int bus)
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_I2C_MUX */
|
||||
|
||||
|
@ -23,6 +23,7 @@
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/mx31-regs.h>
|
||||
#include <div64.h>
|
||||
|
||||
#define TIMER_BASE 0x53f90000 /* General purpose timer 1 */
|
||||
|
||||
@ -38,24 +39,55 @@
|
||||
#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */
|
||||
#define GPTCR_TEN 1 /* Timer enable */
|
||||
|
||||
static ulong timestamp;
|
||||
static ulong lastinc;
|
||||
|
||||
/* "time" is measured in 1 / CONFIG_SYS_HZ seconds, "tick" is internal timer period */
|
||||
#ifdef CONFIG_MX31_TIMER_HIGH_PRECISION
|
||||
/* ~0.4% error - measured with stop-watch on 100s boot-delay */
|
||||
#define TICK_TO_TIME(t) ((t) * CONFIG_SYS_HZ / CONFIG_MX31_CLK32)
|
||||
#define TIME_TO_TICK(t) ((unsigned long long)(t) * CONFIG_MX31_CLK32 / CONFIG_SYS_HZ)
|
||||
#define US_TO_TICK(t) (((unsigned long long)(t) * CONFIG_MX31_CLK32 + \
|
||||
999999) / 1000000)
|
||||
static inline unsigned long long tick_to_time(unsigned long long tick)
|
||||
{
|
||||
tick *= CONFIG_SYS_HZ;
|
||||
do_div(tick, CONFIG_MX31_CLK32);
|
||||
return tick;
|
||||
}
|
||||
|
||||
static inline unsigned long long time_to_tick(unsigned long long time)
|
||||
{
|
||||
time *= CONFIG_MX31_CLK32;
|
||||
do_div(time, CONFIG_SYS_HZ);
|
||||
return time;
|
||||
}
|
||||
|
||||
static inline unsigned long long us_to_tick(unsigned long long us)
|
||||
{
|
||||
us = us * CONFIG_MX31_CLK32 + 999999;
|
||||
do_div(us, 1000000);
|
||||
return us;
|
||||
}
|
||||
#else
|
||||
/* ~2% error */
|
||||
#define TICK_PER_TIME ((CONFIG_MX31_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
|
||||
#define US_PER_TICK (1000000 / CONFIG_MX31_CLK32)
|
||||
#define TICK_TO_TIME(t) ((t) / TICK_PER_TIME)
|
||||
#define TIME_TO_TICK(t) ((unsigned long long)(t) * TICK_PER_TIME)
|
||||
#define US_TO_TICK(t) (((t) + US_PER_TICK - 1) / US_PER_TICK)
|
||||
#endif
|
||||
|
||||
static ulong timestamp;
|
||||
static ulong lastinc;
|
||||
static inline unsigned long long tick_to_time(unsigned long long tick)
|
||||
{
|
||||
do_div(tick, TICK_PER_TIME);
|
||||
return tick;
|
||||
}
|
||||
|
||||
static inline unsigned long long time_to_tick(unsigned long long time)
|
||||
{
|
||||
return time * TICK_PER_TIME;
|
||||
}
|
||||
|
||||
static inline unsigned long long us_to_tick(unsigned long long us)
|
||||
{
|
||||
us += US_PER_TICK - 1;
|
||||
do_div(us, US_PER_TICK);
|
||||
return us;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* nothing really to do with interrupts, just starts up a counter. */
|
||||
/* The 32768Hz 32-bit timer overruns in 131072 seconds */
|
||||
@ -107,7 +139,7 @@ ulong get_timer_masked (void)
|
||||
* 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
|
||||
* 5 * 10^6 days - long enough.
|
||||
*/
|
||||
return TICK_TO_TIME(get_ticks());
|
||||
return tick_to_time(get_ticks());
|
||||
}
|
||||
|
||||
ulong get_timer (ulong base)
|
||||
@ -117,7 +149,7 @@ ulong get_timer (ulong base)
|
||||
|
||||
void set_timer (ulong t)
|
||||
{
|
||||
timestamp = TIME_TO_TICK(t);
|
||||
timestamp = time_to_tick(t);
|
||||
}
|
||||
|
||||
/* delay x useconds AND perserve advance timstamp value */
|
||||
@ -126,7 +158,7 @@ void udelay (unsigned long usec)
|
||||
unsigned long long tmp;
|
||||
ulong tmo;
|
||||
|
||||
tmo = US_TO_TICK(usec);
|
||||
tmo = us_to_tick(usec);
|
||||
tmp = get_ticks() + tmo; /* get current timestamp */
|
||||
|
||||
while (get_ticks() < tmp) /* loop till event */
|
||||
|
@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
|
||||
LIB = $(obj)lib$(CPU).a
|
||||
|
||||
START = start.o
|
||||
COBJS = interrupts.o cpu.o cpuinfo.o
|
||||
COBJS = interrupts.o cpu.o
|
||||
|
||||
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
|
||||
|
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(SOC).a
|
||||
|
||||
COBJS = timer.o
|
||||
COBJS = timer.o cpuinfo.o
|
||||
SOBJS = reset.o
|
||||
|
||||
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
|
@ -193,8 +193,6 @@ extern int overflowEvent;
|
||||
#define LEFT (-1)
|
||||
|
||||
/* macros */
|
||||
#define MIN(a, b) ((a) < (b) ? (a) : (b))
|
||||
|
||||
#define IX_ETH_DB_CHECK_PORT_EXISTS(portID) \
|
||||
{ \
|
||||
if ((portID) >= IX_ETH_DB_NUMBER_OF_PORTS) \
|
||||
|
@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
|
||||
LIB = lib$(CPU).a
|
||||
|
||||
START = start.o
|
||||
COBJS = cpu.o speed.o cpu_init.o interrupts.o
|
||||
COBJS = cpu.o speed.o cpu_init.o interrupts.o dspi.o
|
||||
|
||||
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
|
@ -65,12 +65,12 @@ int checkcpu(void)
|
||||
printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
|
||||
ver);
|
||||
printf(" CPU CLK %s MHz BUS CLK %s MHz FLB CLK %s MHz\n",
|
||||
strmhz(buf1, gd->cpu_clk)),
|
||||
strmhz(buf2, gd->bus_clk)),
|
||||
strmhz(buf3, gd->flb_clk)));
|
||||
strmhz(buf1, gd->cpu_clk),
|
||||
strmhz(buf2, gd->bus_clk),
|
||||
strmhz(buf3, gd->flb_clk));
|
||||
printf(" INP CLK %s MHz VCO CLK %s MHz\n",
|
||||
strmhz(buf1, gd->inp_clk)),
|
||||
strmhz(buf2, gd->vco_clk)));
|
||||
strmhz(buf1, gd->inp_clk),
|
||||
strmhz(buf2, gd->vco_clk));
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
@ -45,6 +45,7 @@ void cpu_init_f(void)
|
||||
volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
|
||||
volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
|
||||
|
||||
#if !defined(CONFIG_CF_SBF)
|
||||
/* Workaround, must place before fbcs */
|
||||
pll->psr = 0x12;
|
||||
|
||||
@ -58,37 +59,44 @@ void cpu_init_f(void)
|
||||
scm1->pacrg = 0;
|
||||
scm1->pacri = 0;
|
||||
|
||||
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
|
||||
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
|
||||
&& defined(CONFIG_SYS_CS0_CTRL))
|
||||
fbcs->csar0 = CONFIG_SYS_CS0_BASE;
|
||||
fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
|
||||
fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
|
||||
#endif
|
||||
#endif /* CONFIG_CF_SBF */
|
||||
|
||||
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
|
||||
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
|
||||
&& defined(CONFIG_SYS_CS1_CTRL))
|
||||
fbcs->csar1 = CONFIG_SYS_CS1_BASE;
|
||||
fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
|
||||
fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
|
||||
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
|
||||
&& defined(CONFIG_SYS_CS2_CTRL))
|
||||
fbcs->csar2 = CONFIG_SYS_CS2_BASE;
|
||||
fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
|
||||
fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
|
||||
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
|
||||
&& defined(CONFIG_SYS_CS3_CTRL))
|
||||
fbcs->csar3 = CONFIG_SYS_CS3_BASE;
|
||||
fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
|
||||
fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
|
||||
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
|
||||
&& defined(CONFIG_SYS_CS4_CTRL))
|
||||
fbcs->csar4 = CONFIG_SYS_CS4_BASE;
|
||||
fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
|
||||
fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
|
||||
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
|
||||
&& defined(CONFIG_SYS_CS5_CTRL))
|
||||
fbcs->csar5 = CONFIG_SYS_CS5_BASE;
|
||||
fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
|
||||
fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
|
||||
|
261
cpu/mcf5227x/dspi.c
Normal file
261
cpu/mcf5227x/dspi.c
Normal file
@ -0,0 +1,261 @@
|
||||
/*
|
||||
*
|
||||
* (C) Copyright 2000-2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <spi.h>
|
||||
#include <malloc.h>
|
||||
|
||||
#if defined(CONFIG_CF_DSPI)
|
||||
#include <asm/immap.h>
|
||||
|
||||
void dspi_init(void)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
|
||||
|
||||
gpio->par_dspi =
|
||||
GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
|
||||
GPIO_PAR_DSPI_SCK_SCK;
|
||||
|
||||
dspi->dmcr = DSPI_DMCR_MSTR | DSPI_DMCR_CSIS7 | DSPI_DMCR_CSIS6 |
|
||||
DSPI_DMCR_CSIS5 | DSPI_DMCR_CSIS4 | DSPI_DMCR_CSIS3 |
|
||||
DSPI_DMCR_CSIS2 | DSPI_DMCR_CSIS1 | DSPI_DMCR_CSIS0 |
|
||||
DSPI_DMCR_CRXF | DSPI_DMCR_CTXF;
|
||||
|
||||
#ifdef CONFIG_SYS_DSPI_DCTAR0
|
||||
dspi->dctar0 = CONFIG_SYS_DSPI_DCTAR0;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DSPI_DCTAR1
|
||||
dspi->dctar1 = CONFIG_SYS_DSPI_DCTAR1;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DSPI_DCTAR2
|
||||
dspi->dctar2 = CONFIG_SYS_DSPI_DCTAR2;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DSPI_DCTAR3
|
||||
dspi->dctar3 = CONFIG_SYS_DSPI_DCTAR3;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DSPI_DCTAR4
|
||||
dspi->dctar4 = CONFIG_SYS_DSPI_DCTAR4;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DSPI_DCTAR5
|
||||
dspi->dctar5 = CONFIG_SYS_DSPI_DCTAR5;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DSPI_DCTAR6
|
||||
dspi->dctar6 = CONFIG_SYS_DSPI_DCTAR6;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DSPI_DCTAR7
|
||||
dspi->dctar7 = CONFIG_SYS_DSPI_DCTAR7;
|
||||
#endif
|
||||
}
|
||||
|
||||
void dspi_tx(int chipsel, u8 attrib, u16 data)
|
||||
{
|
||||
volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
|
||||
|
||||
while ((dspi->dsr & 0x0000F000) >= 4) ;
|
||||
|
||||
dspi->dtfr = (attrib << 24) | ((1 << chipsel) << 16) | data;
|
||||
}
|
||||
|
||||
u16 dspi_rx(void)
|
||||
{
|
||||
volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
|
||||
|
||||
while ((dspi->dsr & 0x000000F0) == 0) ;
|
||||
|
||||
return (dspi->drfr & 0xFFFF);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CMD_SPI)
|
||||
void spi_init_f(void)
|
||||
{
|
||||
}
|
||||
|
||||
void spi_init_r(void)
|
||||
{
|
||||
}
|
||||
|
||||
void spi_init(void)
|
||||
{
|
||||
dspi_init();
|
||||
}
|
||||
|
||||
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
|
||||
unsigned int max_hz, unsigned int mode)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
struct spi_slave *slave;
|
||||
|
||||
slave = malloc(sizeof(struct spi_slave));
|
||||
if (!slave)
|
||||
return NULL;
|
||||
|
||||
switch (cs) {
|
||||
case 0:
|
||||
gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
|
||||
gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0;
|
||||
break;
|
||||
case 2:
|
||||
gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK;
|
||||
gpio->par_timer |= GPIO_PAR_TIMER_T2IN_DSPIPCS2;
|
||||
break;
|
||||
}
|
||||
|
||||
slave->bus = bus;
|
||||
slave->cs = cs;
|
||||
|
||||
return slave;
|
||||
}
|
||||
|
||||
void spi_free_slave(struct spi_slave *slave)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
|
||||
switch (slave->cs) {
|
||||
case 0:
|
||||
gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
|
||||
break;
|
||||
case 2:
|
||||
gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK;
|
||||
break;
|
||||
}
|
||||
|
||||
free(slave);
|
||||
}
|
||||
|
||||
int spi_claim_bus(struct spi_slave *slave)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
void spi_release_bus(struct spi_slave *slave)
|
||||
{
|
||||
}
|
||||
|
||||
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
|
||||
void *din, unsigned long flags)
|
||||
{
|
||||
static int bWrite = 0;
|
||||
u8 *spi_rd, *spi_wr;
|
||||
int len = bitlen >> 3;
|
||||
|
||||
spi_rd = (u8 *) din;
|
||||
spi_wr = (u8 *) dout;
|
||||
|
||||
/* command handling */
|
||||
if (((len == 4) || (len == 1) || (len == 5)) && (dout != NULL)) {
|
||||
switch (*spi_wr) {
|
||||
case 0x02: /* Page Prog */
|
||||
bWrite = 1;
|
||||
dspi_tx(slave->cs, 0x80, spi_wr[0]);
|
||||
dspi_rx();
|
||||
dspi_tx(slave->cs, 0x80, spi_wr[1]);
|
||||
dspi_rx();
|
||||
dspi_tx(slave->cs, 0x80, spi_wr[2]);
|
||||
dspi_rx();
|
||||
dspi_tx(slave->cs, 0x80, spi_wr[3]);
|
||||
dspi_rx();
|
||||
return 0;
|
||||
case 0x05: /* Read Status */
|
||||
if (len == 4)
|
||||
if ((spi_wr[1] == 0xFF) && (spi_wr[2] == 0xFF)
|
||||
&& (spi_wr[3] == 0xFF)) {
|
||||
dspi_tx(slave->cs, 0x80, *spi_wr);
|
||||
dspi_rx();
|
||||
}
|
||||
return 0;
|
||||
case 0x06: /* WREN */
|
||||
dspi_tx(slave->cs, 0x00, *spi_wr);
|
||||
dspi_rx();
|
||||
return 0;
|
||||
case 0x0B: /* Fast read */
|
||||
if ((len == 5) && (spi_wr[4] == 0)) {
|
||||
dspi_tx(slave->cs, 0x80, spi_wr[0]);
|
||||
dspi_rx();
|
||||
dspi_tx(slave->cs, 0x80, spi_wr[1]);
|
||||
dspi_rx();
|
||||
dspi_tx(slave->cs, 0x80, spi_wr[2]);
|
||||
dspi_rx();
|
||||
dspi_tx(slave->cs, 0x80, spi_wr[3]);
|
||||
dspi_rx();
|
||||
dspi_tx(slave->cs, 0x80, spi_wr[4]);
|
||||
dspi_rx();
|
||||
}
|
||||
return 0;
|
||||
case 0x9F: /* RDID */
|
||||
dspi_tx(slave->cs, 0x80, *spi_wr);
|
||||
dspi_rx();
|
||||
return 0;
|
||||
case 0xD8: /* Sector erase */
|
||||
if (len == 4)
|
||||
if ((spi_wr[2] == 0) && (spi_wr[3] == 0)) {
|
||||
dspi_tx(slave->cs, 0x80, spi_wr[0]);
|
||||
dspi_rx();
|
||||
dspi_tx(slave->cs, 0x80, spi_wr[1]);
|
||||
dspi_rx();
|
||||
dspi_tx(slave->cs, 0x80, spi_wr[2]);
|
||||
dspi_rx();
|
||||
dspi_tx(slave->cs, 0x00, spi_wr[3]);
|
||||
dspi_rx();
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
if (bWrite)
|
||||
len--;
|
||||
|
||||
while (len--) {
|
||||
if (dout != NULL) {
|
||||
dspi_tx(slave->cs, 0x80, *spi_wr);
|
||||
dspi_rx();
|
||||
spi_wr++;
|
||||
}
|
||||
|
||||
if (din != NULL) {
|
||||
dspi_tx(slave->cs, 0x80, 0);
|
||||
*spi_rd = dspi_rx();
|
||||
spi_rd++;
|
||||
}
|
||||
}
|
||||
|
||||
if (flags == SPI_XFER_END) {
|
||||
if (bWrite) {
|
||||
dspi_tx(slave->cs, 0x00, *spi_wr);
|
||||
dspi_rx();
|
||||
bWrite = 0;
|
||||
} else {
|
||||
dspi_tx(slave->cs, 0x00, 0);
|
||||
dspi_rx();
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_CMD_SPI */
|
||||
|
||||
#endif /* CONFIG_CF_DSPI */
|
@ -90,17 +90,33 @@ int get_clocks(void)
|
||||
int vco, temp, pcrvalue, pfdr;
|
||||
u8 bootmode;
|
||||
|
||||
bootmode = (ccm->ccr & 0x000C) >> 2;
|
||||
|
||||
pcrvalue = pll->pcr & 0xFF0F0FFF;
|
||||
pfdr = pcrvalue >> 24;
|
||||
|
||||
if (pfdr != 0x1E) {
|
||||
if (pfdr == 0x1E)
|
||||
bootmode = 0; /* Normal Mode */
|
||||
|
||||
#ifdef CONFIG_CF_SBF
|
||||
bootmode = 3; /* Serial Mode */
|
||||
#endif
|
||||
|
||||
if (bootmode == 0) {
|
||||
/* Normal mode */
|
||||
vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
|
||||
if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
|
||||
/* Default value */
|
||||
pcrvalue = (pll->pcr & 0x00FFFFFF);
|
||||
pcrvalue |= 0x1E << 24;
|
||||
pll->pcr = pcrvalue;
|
||||
vco =
|
||||
((pll->pcr & 0xFF000000) >> 24) *
|
||||
CONFIG_SYS_INPUT_CLKSRC;
|
||||
}
|
||||
gd->vco_clk = vco; /* Vco clock */
|
||||
} else if (bootmode == 3) {
|
||||
/* serial mode */
|
||||
} else {
|
||||
/* Normal Mode */
|
||||
vco = pfdr * CONFIG_SYS_INPUT_CLKSRC;
|
||||
gd->vco_clk = vco;
|
||||
vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
|
||||
gd->vco_clk = vco; /* Vco clock */
|
||||
}
|
||||
|
||||
if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
|
||||
|
@ -46,6 +46,11 @@
|
||||
addl #60,%sp; /* space for 15 regs */ \
|
||||
rte;
|
||||
|
||||
#if defined(CONFIG_CF_SBF)
|
||||
#define ASM_DRAMINIT (asm_dram_init - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
|
||||
#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
|
||||
#endif
|
||||
|
||||
.text
|
||||
/*
|
||||
* Vector table. This is used for initial platform startup.
|
||||
@ -53,8 +58,14 @@
|
||||
*/
|
||||
_vectors:
|
||||
|
||||
INITSP: .long 0x00000000 /* Initial SP */
|
||||
INITPC: .long _START /* Initial PC */
|
||||
#if defined(CONFIG_CF_SBF)
|
||||
INITSP: .long 0 /* Initial SP */
|
||||
INITPC: .long ASM_DRAMINIT /* Initial PC */
|
||||
#else
|
||||
INITSP: .long 0 /* Initial SP */
|
||||
INITPC: .long _START /* Initial PC */
|
||||
#endif
|
||||
|
||||
vector02: .long _FAULT /* Access Error */
|
||||
vector03: .long _FAULT /* Address Error */
|
||||
vector04: .long _FAULT /* Illegal Instruction */
|
||||
@ -83,6 +94,7 @@ vector1D: .long _FAULT /* Autovector Level 5 */
|
||||
vector1E: .long _FAULT /* Autovector Level 6 */
|
||||
vector1F: .long _FAULT /* Autovector Level 7 */
|
||||
|
||||
#if !defined(CONFIG_CF_SBF)
|
||||
/* TRAP #0 - #15 */
|
||||
vector20_2F:
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
@ -122,9 +134,231 @@ vector192_255:
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CF_SBF)
|
||||
/* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
|
||||
asm_sbf_img_hdr:
|
||||
.long 0x00000000 /* checksum, not yet implemented */
|
||||
.long 0x00020000 /* image length */
|
||||
.long TEXT_BASE /* image to be relocated at */
|
||||
|
||||
asm_dram_init:
|
||||
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
|
||||
movec %d0, %RAMBAR1 /* init Rambar */
|
||||
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
|
||||
clr.l %sp@-
|
||||
|
||||
/* Must disable global address */
|
||||
move.l #0xFC008000, %a1
|
||||
move.l #(CONFIG_SYS_CS0_BASE), (%a1)
|
||||
move.l #0xFC008008, %a1
|
||||
move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
|
||||
move.l #0xFC008004, %a1
|
||||
move.l #(CONFIG_SYS_CS0_MASK), (%a1)
|
||||
|
||||
/*
|
||||
* Dram Initialization
|
||||
* a1, a2, and d0
|
||||
*/
|
||||
/* mscr sdram */
|
||||
move.l #0xFC0A4074, %a1
|
||||
move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
|
||||
nop
|
||||
|
||||
/* SDRAM Chip 0 and 1 */
|
||||
move.l #0xFC0B8110, %a1
|
||||
move.l #0xFC0B8114, %a2
|
||||
|
||||
/* calculate the size */
|
||||
move.l #0x13, %d1
|
||||
move.l #(CONFIG_SYS_SDRAM_SIZE), %d2
|
||||
#ifdef CONFIG_SYS_SDRAM_BASE1
|
||||
lsr.l #1, %d2
|
||||
#endif
|
||||
|
||||
dramsz_loop:
|
||||
lsr.l #1, %d2
|
||||
add.l #1, %d1
|
||||
cmp.l #1, %d2
|
||||
bne dramsz_loop
|
||||
|
||||
/* SDRAM Chip 0 and 1 */
|
||||
move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
|
||||
or.l %d1, (%a1)
|
||||
#ifdef CONFIG_SYS_SDRAM_BASE1
|
||||
move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2)
|
||||
or.l %d1, (%a2)
|
||||
#endif
|
||||
nop
|
||||
|
||||
/* dram cfg1 and cfg2 */
|
||||
move.l #0xFC0B8008, %a1
|
||||
move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
|
||||
nop
|
||||
move.l #0xFC0B800C, %a2
|
||||
move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2)
|
||||
nop
|
||||
|
||||
move.l #0xFC0B8000, %a1 /* Mode */
|
||||
move.l #0xFC0B8004, %a2 /* Ctrl */
|
||||
|
||||
/* Issue PALL */
|
||||
move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
|
||||
nop
|
||||
|
||||
/* Issue LEMR */
|
||||
move.l #(CONFIG_SYS_SDRAM_MODE), (%a1)
|
||||
nop
|
||||
move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1)
|
||||
nop
|
||||
|
||||
move.l #1000, %d0
|
||||
wait1000:
|
||||
nop
|
||||
subq.l #1, %d0
|
||||
bne wait1000
|
||||
|
||||
/* Issue PALL */
|
||||
move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
|
||||
nop
|
||||
|
||||
/* Perform two refresh cycles */
|
||||
move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
|
||||
nop
|
||||
move.l %d0, (%a2)
|
||||
move.l %d0, (%a2)
|
||||
nop
|
||||
|
||||
move.l #(CONFIG_SYS_SDRAM_CTRL), %d0
|
||||
and.l #0x7FFFFFFF, %d0
|
||||
or.l #0x10000c00, %d0
|
||||
move.l %d0, (%a2)
|
||||
nop
|
||||
|
||||
/*
|
||||
* DSPI Initialization
|
||||
* a0 - general, sram - 0x80008000 - 32, see M52277EVB.h
|
||||
* a1 - dspi status
|
||||
* a2 - dtfr
|
||||
* a3 - drfr
|
||||
* a4 - Dst addr
|
||||
*/
|
||||
|
||||
/* Enable pins for DSPI mode - chip-selects are enabled later */
|
||||
move.l #0xFC0A4036, %a0
|
||||
move.b #0x3F, %d0
|
||||
move.b %d0, (%a0)
|
||||
|
||||
/* DSPI CS */
|
||||
#ifdef CONFIG_SYS_DSPI_CS0
|
||||
move.b (%a0), %d0
|
||||
or.l #0xC0, %d0
|
||||
move.b %d0, (%a0)
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DSPI_CS2
|
||||
move.l #0xFC0A4037, %a0
|
||||
move.b (%a0), %d0
|
||||
or.l #0x10, %d0
|
||||
move.b %d0, (%a0)
|
||||
#endif
|
||||
nop
|
||||
|
||||
/* Configure DSPI module */
|
||||
move.l #0xFC05C000, %a0
|
||||
move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
|
||||
|
||||
move.l #0xFC05C00C, %a0
|
||||
move.l #0x3E000011, (%a0)
|
||||
|
||||
move.l #0xFC05C034, %a2 /* dtfr */
|
||||
move.l #0xFC05C03B, %a3 /* drfr */
|
||||
|
||||
move.l #(ASM_SBF_IMG_HDR + 4), %a1
|
||||
move.l (%a1)+, %d5
|
||||
move.l (%a1), %a4
|
||||
|
||||
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
|
||||
move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4
|
||||
|
||||
move.l #0xFC05C02C, %a1 /* dspi status */
|
||||
|
||||
/* Issue commands and address */
|
||||
move.l #0x8004000B, %d2 /* Fast Read Cmd */
|
||||
jsr asm_dspi_wr_status
|
||||
jsr asm_dspi_rd_status
|
||||
|
||||
move.l #0x80040000, %d2 /* Address byte 2 */
|
||||
jsr asm_dspi_wr_status
|
||||
jsr asm_dspi_rd_status
|
||||
|
||||
move.l #0x80040000, %d2 /* Address byte 1 */
|
||||
jsr asm_dspi_wr_status
|
||||
jsr asm_dspi_rd_status
|
||||
|
||||
move.l #0x80040000, %d2 /* Address byte 0 */
|
||||
jsr asm_dspi_wr_status
|
||||
jsr asm_dspi_rd_status
|
||||
|
||||
move.l #0x80040000, %d2 /* Dummy Wr and Rd */
|
||||
jsr asm_dspi_wr_status
|
||||
jsr asm_dspi_rd_status
|
||||
|
||||
/* Transfer serial boot header to sram */
|
||||
asm_dspi_rd_loop1:
|
||||
move.l #0x80040000, %d2
|
||||
jsr asm_dspi_wr_status
|
||||
jsr asm_dspi_rd_status
|
||||
|
||||
move.b %d1, (%a0) /* read, copy to dst */
|
||||
|
||||
add.l #1, %a0 /* inc dst by 1 */
|
||||
sub.l #1, %d4 /* dec cnt by 1 */
|
||||
bne asm_dspi_rd_loop1
|
||||
|
||||
/* Transfer u-boot from serial flash to memory */
|
||||
asm_dspi_rd_loop2:
|
||||
move.l #0x80040000, %d2
|
||||
jsr asm_dspi_wr_status
|
||||
jsr asm_dspi_rd_status
|
||||
|
||||
move.b %d1, (%a4) /* read, copy to dst */
|
||||
|
||||
add.l #1, %a4 /* inc dst by 1 */
|
||||
sub.l #1, %d5 /* dec cnt by 1 */
|
||||
bne asm_dspi_rd_loop2
|
||||
|
||||
move.l #0x00040000, %d2 /* Terminate */
|
||||
jsr asm_dspi_wr_status
|
||||
jsr asm_dspi_rd_status
|
||||
|
||||
/* jump to memory and execute */
|
||||
move.l #(TEXT_BASE + 0x400), %a0
|
||||
move.l %a0, (%a1)
|
||||
jmp (%a0)
|
||||
|
||||
asm_dspi_wr_status:
|
||||
move.l (%a1), %d0 /* status */
|
||||
and.l #0x0000F000, %d0
|
||||
cmp.l #0x00003000, %d0
|
||||
bgt asm_dspi_wr_status
|
||||
|
||||
move.l %d2, (%a2)
|
||||
rts
|
||||
|
||||
asm_dspi_rd_status:
|
||||
move.l (%a1), %d0 /* status */
|
||||
and.l #0x000000F0, %d0
|
||||
lsr.l #4, %d0
|
||||
cmp.l #0, %d0
|
||||
beq asm_dspi_rd_status
|
||||
|
||||
move.b (%a3), %d1
|
||||
rts
|
||||
#endif /* CONFIG_CF_SBF */
|
||||
|
||||
.text
|
||||
|
||||
. = 0x400
|
||||
.globl _start
|
||||
_start:
|
||||
nop
|
||||
@ -132,11 +366,16 @@ _start:
|
||||
move.w #0x2700,%sr /* Mask off Interrupt */
|
||||
|
||||
/* Set vector base register at the beginning of the Flash */
|
||||
#if defined(CONFIG_CF_SBF)
|
||||
move.l #TEXT_BASE, %d0
|
||||
movec %d0, %VBR
|
||||
#else
|
||||
move.l #CONFIG_SYS_FLASH_BASE, %d0
|
||||
movec %d0, %VBR
|
||||
|
||||
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
|
||||
movec %d0, %RAMBAR1
|
||||
#endif
|
||||
|
||||
/* initialize general use internal ram */
|
||||
move.l #0, %d0
|
||||
|
@ -65,8 +65,8 @@ int checkcpu(void)
|
||||
printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
|
||||
ver);
|
||||
printf(" CPU CLK %s MHz BUS CLK %s MHz\n",
|
||||
strmhz(buf1, gd->cpu_clk)),
|
||||
strmhz(buf2, gd->bus_clk)));
|
||||
strmhz(buf1, gd->cpu_clk),
|
||||
strmhz(buf2, gd->bus_clk));
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
@ -27,9 +27,14 @@
|
||||
|
||||
#include <common.h>
|
||||
#include <watchdog.h>
|
||||
|
||||
#include <asm/immap.h>
|
||||
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
#include <asm/fec.h>
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Breath some life into the CPU...
|
||||
*
|
||||
@ -143,3 +148,20 @@ void uart_port_conf(void)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
|
||||
if (setclear) {
|
||||
gpio->par_feci2c |=
|
||||
(GPIO_PAR_FECI2C_EMDC_FECEMDC | GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
|
||||
} else {
|
||||
gpio->par_feci2c &=
|
||||
~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
@ -36,6 +36,71 @@
|
||||
#include <watchdog.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
#include <asm/fec.h>
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_M5272
|
||||
/* Only 5272 Flexbus chipselect is different from the rest */
|
||||
void init_fbcs(void)
|
||||
{
|
||||
volatile fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
|
||||
|
||||
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
|
||||
&& defined(CONFIG_SYS_CS0_CTRL))
|
||||
fbcs->csar0 = CONFIG_SYS_CS0_BASE;
|
||||
fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
|
||||
fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
|
||||
#else
|
||||
#warning "Chip Select 0 are not initialized/used"
|
||||
#endif
|
||||
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
|
||||
&& defined(CONFIG_SYS_CS1_CTRL))
|
||||
fbcs->csar1 = CONFIG_SYS_CS1_BASE;
|
||||
fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
|
||||
fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
|
||||
#endif
|
||||
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
|
||||
&& defined(CONFIG_SYS_CS2_CTRL))
|
||||
fbcs->csar2 = CONFIG_SYS_CS2_BASE;
|
||||
fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
|
||||
fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
|
||||
#endif
|
||||
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
|
||||
&& defined(CONFIG_SYS_CS3_CTRL))
|
||||
fbcs->csar3 = CONFIG_SYS_CS3_BASE;
|
||||
fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
|
||||
fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
|
||||
#endif
|
||||
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
|
||||
&& defined(CONFIG_SYS_CS4_CTRL))
|
||||
fbcs->csar4 = CONFIG_SYS_CS4_BASE;
|
||||
fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
|
||||
fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
|
||||
#endif
|
||||
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
|
||||
&& defined(CONFIG_SYS_CS5_CTRL))
|
||||
fbcs->csar5 = CONFIG_SYS_CS5_BASE;
|
||||
fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
|
||||
fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
|
||||
#endif
|
||||
#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \
|
||||
&& defined(CONFIG_SYS_CS6_CTRL))
|
||||
fbcs->csar6 = CONFIG_SYS_CS6_BASE;
|
||||
fbcs->cscr6 = CONFIG_SYS_CS6_CTRL;
|
||||
fbcs->csmr6 = CONFIG_SYS_CS6_MASK;
|
||||
#endif
|
||||
#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \
|
||||
&& defined(CONFIG_SYS_CS7_CTRL))
|
||||
fbcs->csar7 = CONFIG_SYS_CS7_BASE;
|
||||
fbcs->cscr7 = CONFIG_SYS_CS7_CTRL;
|
||||
fbcs->csmr7 = CONFIG_SYS_CS7_MASK;
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_M5253)
|
||||
/*
|
||||
* Breath some life into the CPU...
|
||||
@ -66,22 +131,14 @@ void cpu_init_f(void)
|
||||
mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
|
||||
mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
|
||||
|
||||
/*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
|
||||
/*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); *//* Enable a 1 cycle pre-drive cycle on CS1 */
|
||||
|
||||
/*
|
||||
* Setup chip selects...
|
||||
*/
|
||||
|
||||
mbar_writeShort(MCFSIM_CSAR1, CONFIG_SYS_CSAR1);
|
||||
mbar_writeShort(MCFSIM_CSCR1, CONFIG_SYS_CSCR1);
|
||||
mbar_writeLong(MCFSIM_CSMR1, CONFIG_SYS_CSMR1);
|
||||
|
||||
mbar_writeShort(MCFSIM_CSAR0, CONFIG_SYS_CSAR0);
|
||||
mbar_writeShort(MCFSIM_CSCR0, CONFIG_SYS_CSCR0);
|
||||
mbar_writeLong(MCFSIM_CSMR0, CONFIG_SYS_CSMR0);
|
||||
/* FlexBus Chipselect */
|
||||
init_fbcs();
|
||||
|
||||
#ifdef CONFIG_FSL_I2C
|
||||
CONFIG_SYS_I2C_PINMUX_REG = CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
|
||||
CONFIG_SYS_I2C_PINMUX_REG =
|
||||
CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
|
||||
CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
|
||||
#ifdef CONFIG_SYS_I2C2_OFFSET
|
||||
CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR;
|
||||
@ -121,6 +178,9 @@ void cpu_init_f(void)
|
||||
mbar_writeShort(MCF_WTM_WCR, 0);
|
||||
#endif
|
||||
|
||||
/* FlexBus Chipselect */
|
||||
init_fbcs();
|
||||
|
||||
/* Set clockspeed to 100MHz */
|
||||
mbar_writeShort(MCF_FMPLL_SYNCR,
|
||||
MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
|
||||
@ -153,6 +213,19 @@ void uart_port_conf(void)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
if (setclear) {
|
||||
/* Enable Ethernet pins */
|
||||
mbar_writeByte(MCF_GPIO_PAR_FECI2C, CONFIG_SYS_FECI2C);
|
||||
} else {
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_CMD_NET */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_M5272)
|
||||
@ -255,6 +328,22 @@ void uart_port_conf(void)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
|
||||
if (setclear) {
|
||||
gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER |
|
||||
GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 |
|
||||
GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 |
|
||||
GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
|
||||
} else {
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_CMD_NET */
|
||||
#endif /* #if defined(CONFIG_M5272) */
|
||||
|
||||
#if defined(CONFIG_M5275)
|
||||
@ -268,66 +357,20 @@ void uart_port_conf(void)
|
||||
*/
|
||||
void cpu_init_f(void)
|
||||
{
|
||||
/* if we come from RAM we assume the CPU is
|
||||
/*
|
||||
* if we come from RAM we assume the CPU is
|
||||
* already initialized.
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_MONITOR_IS_IN_RAM
|
||||
volatile wdog_t *wdog_reg = (wdog_t *)(MMAP_WDOG);
|
||||
volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
|
||||
volatile csctrl_t *csctrl_reg = (csctrl_t *)(MMAP_FBCS);
|
||||
volatile wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
|
||||
volatile gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
|
||||
|
||||
/* Kill watchdog so we can initialize the PLL */
|
||||
wdog_reg->wcr = 0;
|
||||
|
||||
/* Memory Controller: */
|
||||
/* Flash */
|
||||
csctrl_reg->ar0 = CONFIG_SYS_AR0_PRELIM;
|
||||
csctrl_reg->cr0 = CONFIG_SYS_CR0_PRELIM;
|
||||
csctrl_reg->mr0 = CONFIG_SYS_MR0_PRELIM;
|
||||
|
||||
#if (defined(CONFIG_SYS_AR1_PRELIM) && defined(CONFIG_SYS_CR1_PRELIM) && defined(CONFIG_SYS_MR1_PRELIM))
|
||||
csctrl_reg->ar1 = CONFIG_SYS_AR1_PRELIM;
|
||||
csctrl_reg->cr1 = CONFIG_SYS_CR1_PRELIM;
|
||||
csctrl_reg->mr1 = CONFIG_SYS_MR1_PRELIM;
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_SYS_AR2_PRELIM) && defined(CONFIG_SYS_CR2_PRELIM) && defined(CONFIG_SYS_MR2_PRELIM))
|
||||
csctrl_reg->ar2 = CONFIG_SYS_AR2_PRELIM;
|
||||
csctrl_reg->cr2 = CONFIG_SYS_CR2_PRELIM;
|
||||
csctrl_reg->mr2 = CONFIG_SYS_MR2_PRELIM;
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_SYS_AR3_PRELIM) && defined(CONFIG_SYS_CR3_PRELIM) && defined(CONFIG_SYS_MR3_PRELIM))
|
||||
csctrl_reg->ar3 = CONFIG_SYS_AR3_PRELIM;
|
||||
csctrl_reg->cr3 = CONFIG_SYS_CR3_PRELIM;
|
||||
csctrl_reg->mr3 = CONFIG_SYS_MR3_PRELIM;
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_SYS_AR4_PRELIM) && defined(CONFIG_SYS_CR4_PRELIM) && defined(CONFIG_SYS_MR4_PRELIM))
|
||||
csctrl_reg->ar4 = CONFIG_SYS_AR4_PRELIM;
|
||||
csctrl_reg->cr4 = CONFIG_SYS_CR4_PRELIM;
|
||||
csctrl_reg->mr4 = CONFIG_SYS_MR4_PRELIM;
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_SYS_AR5_PRELIM) && defined(CONFIG_SYS_CR5_PRELIM) && defined(CONFIG_SYS_MR5_PRELIM))
|
||||
csctrl_reg->ar5 = CONFIG_SYS_AR5_PRELIM;
|
||||
csctrl_reg->cr5 = CONFIG_SYS_CR5_PRELIM;
|
||||
csctrl_reg->mr5 = CONFIG_SYS_MR5_PRELIM;
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_SYS_AR6_PRELIM) && defined(CONFIG_SYS_CR6_PRELIM) && defined(CONFIG_SYS_MR6_PRELIM))
|
||||
csctrl_reg->ar6 = CONFIG_SYS_AR6_PRELIM;
|
||||
csctrl_reg->cr6 = CONFIG_SYS_CR6_PRELIM;
|
||||
csctrl_reg->mr6 = CONFIG_SYS_MR6_PRELIM;
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_SYS_AR7_PRELIM) && defined(CONFIG_SYS_CR7_PRELIM) && defined(CONFIG_SYS_MR7_PRELIM))
|
||||
csctrl_reg->ar7 = CONFIG_SYS_AR7_PRELIM;
|
||||
csctrl_reg->cr7 = CONFIG_SYS_CR7_PRELIM;
|
||||
csctrl_reg->mr7 = CONFIG_SYS_MR7_PRELIM;
|
||||
#endif
|
||||
|
||||
/* FlexBus Chipselect */
|
||||
init_fbcs();
|
||||
#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
|
||||
|
||||
#ifdef CONFIG_FSL_I2C
|
||||
@ -349,7 +392,7 @@ int cpu_init_r(void)
|
||||
|
||||
void uart_port_conf(void)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
|
||||
/* Setup Ports: */
|
||||
switch (CONFIG_SYS_UART_PORT) {
|
||||
@ -364,6 +407,35 @@ void uart_port_conf(void)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
struct fec_info_s *info = (struct fec_info_s *) dev->priv;
|
||||
volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
|
||||
|
||||
if (setclear) {
|
||||
/* Enable Ethernet pins */
|
||||
if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
|
||||
gpio->par_feci2c |= 0x0F00;
|
||||
gpio->par_fec0hl |= 0xC0;
|
||||
} else {
|
||||
gpio->par_feci2c |= 0x00A0;
|
||||
gpio->par_fec1hl |= 0xC0;
|
||||
}
|
||||
} else {
|
||||
if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
|
||||
gpio->par_feci2c &= ~0x0F00;
|
||||
gpio->par_fec0hl &= ~0xC0;
|
||||
} else {
|
||||
gpio->par_feci2c &= ~0x00A0;
|
||||
gpio->par_fec1hl &= ~0xC0;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_CMD_NET */
|
||||
#endif /* #if defined(CONFIG_M5275) */
|
||||
|
||||
#if defined(CONFIG_M5282)
|
||||
@ -384,7 +456,8 @@ void cpu_init_f(void)
|
||||
#ifndef CONFIG_MONITOR_IS_IN_RAM
|
||||
/* Set speed /PLL */
|
||||
MCFCLOCK_SYNCR =
|
||||
MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) | MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
|
||||
MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) |
|
||||
MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
|
||||
while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
|
||||
|
||||
MCFGPIO_PBCDPAR = 0xc0;
|
||||
@ -425,119 +498,8 @@ void cpu_init_f(void)
|
||||
MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
|
||||
#endif
|
||||
|
||||
/* This is probably a bad place to setup chip selects, but everyone
|
||||
else is doing it! */
|
||||
|
||||
#if defined(CONFIG_SYS_CS0_BASE) & defined(CONFIG_SYS_CS0_SIZE) & \
|
||||
defined(CONFIG_SYS_CS0_WIDTH) & defined(CONFIG_SYS_CS0_WS)
|
||||
|
||||
MCFCSM_CSAR0 = (CONFIG_SYS_CS0_BASE >> 16) & 0xFFFF;
|
||||
|
||||
#if (CONFIG_SYS_CS0_WIDTH == 8)
|
||||
#define CONFIG_SYS_CS0_PS MCFCSM_CSCR_PS_8
|
||||
#elif (CONFIG_SYS_CS0_WIDTH == 16)
|
||||
#define CONFIG_SYS_CS0_PS MCFCSM_CSCR_PS_16
|
||||
#elif (CONFIG_SYS_CS0_WIDTH == 32)
|
||||
#define CONFIG_SYS_CS0_PS MCFCSM_CSCR_PS_32
|
||||
#else
|
||||
#error "CONFIG_SYS_CS0_WIDTH: Fault - wrong bus with for CS0"
|
||||
#endif
|
||||
MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CONFIG_SYS_CS0_WS)
|
||||
| CONFIG_SYS_CS0_PS | MCFCSM_CSCR_AA;
|
||||
|
||||
#if (CONFIG_SYS_CS0_RO != 0)
|
||||
MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS0_SIZE - 1)
|
||||
| MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
|
||||
#else
|
||||
MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS0_SIZE - 1) | MCFCSM_CSMR_V;
|
||||
#endif
|
||||
#else
|
||||
#warning "Chip Select 0 are not initialized/used"
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SYS_CS1_BASE) & defined(CONFIG_SYS_CS1_SIZE) & \
|
||||
defined(CONFIG_SYS_CS1_WIDTH) & defined(CONFIG_SYS_CS1_WS)
|
||||
|
||||
MCFCSM_CSAR1 = (CONFIG_SYS_CS1_BASE >> 16) & 0xFFFF;
|
||||
|
||||
#if (CONFIG_SYS_CS1_WIDTH == 8)
|
||||
#define CONFIG_SYS_CS1_PS MCFCSM_CSCR_PS_8
|
||||
#elif (CONFIG_SYS_CS1_WIDTH == 16)
|
||||
#define CONFIG_SYS_CS1_PS MCFCSM_CSCR_PS_16
|
||||
#elif (CONFIG_SYS_CS1_WIDTH == 32)
|
||||
#define CONFIG_SYS_CS1_PS MCFCSM_CSCR_PS_32
|
||||
#else
|
||||
#error "CONFIG_SYS_CS1_WIDTH: Fault - wrong bus with for CS1"
|
||||
#endif
|
||||
MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CONFIG_SYS_CS1_WS)
|
||||
| CONFIG_SYS_CS1_PS | MCFCSM_CSCR_AA;
|
||||
|
||||
#if (CONFIG_SYS_CS1_RO != 0)
|
||||
MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS1_SIZE - 1)
|
||||
| MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
|
||||
#else
|
||||
MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS1_SIZE - 1)
|
||||
| MCFCSM_CSMR_V;
|
||||
#endif
|
||||
#else
|
||||
#warning "Chip Select 1 are not initialized/used"
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SYS_CS2_BASE) & defined(CONFIG_SYS_CS2_SIZE) & \
|
||||
defined(CONFIG_SYS_CS2_WIDTH) & defined(CONFIG_SYS_CS2_WS)
|
||||
|
||||
MCFCSM_CSAR2 = (CONFIG_SYS_CS2_BASE >> 16) & 0xFFFF;
|
||||
|
||||
#if (CONFIG_SYS_CS2_WIDTH == 8)
|
||||
#define CONFIG_SYS_CS2_PS MCFCSM_CSCR_PS_8
|
||||
#elif (CONFIG_SYS_CS2_WIDTH == 16)
|
||||
#define CONFIG_SYS_CS2_PS MCFCSM_CSCR_PS_16
|
||||
#elif (CONFIG_SYS_CS2_WIDTH == 32)
|
||||
#define CONFIG_SYS_CS2_PS MCFCSM_CSCR_PS_32
|
||||
#else
|
||||
#error "CONFIG_SYS_CS2_WIDTH: Fault - wrong bus with for CS2"
|
||||
#endif
|
||||
MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CONFIG_SYS_CS2_WS)
|
||||
| CONFIG_SYS_CS2_PS | MCFCSM_CSCR_AA;
|
||||
|
||||
#if (CONFIG_SYS_CS2_RO != 0)
|
||||
MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS2_SIZE - 1)
|
||||
| MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
|
||||
#else
|
||||
MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS2_SIZE - 1)
|
||||
| MCFCSM_CSMR_V;
|
||||
#endif
|
||||
#else
|
||||
#warning "Chip Select 2 are not initialized/used"
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SYS_CS3_BASE) & defined(CONFIG_SYS_CS3_SIZE) & \
|
||||
defined(CONFIG_SYS_CS3_WIDTH) & defined(CONFIG_SYS_CS3_WS)
|
||||
|
||||
MCFCSM_CSAR3 = (CONFIG_SYS_CS3_BASE >> 16) & 0xFFFF;
|
||||
|
||||
#if (CONFIG_SYS_CS3_WIDTH == 8)
|
||||
#define CONFIG_SYS_CS3_PS MCFCSM_CSCR_PS_8
|
||||
#elif (CONFIG_SYS_CS3_WIDTH == 16)
|
||||
#define CONFIG_SYS_CS3_PS MCFCSM_CSCR_PS_16
|
||||
#elif (CONFIG_SYS_CS3_WIDTH == 32)
|
||||
#define CONFIG_SYS_CS3_PS MCFCSM_CSCR_PS_32
|
||||
#else
|
||||
#error "CONFIG_SYS_CS3_WIDTH: Fault - wrong bus with for CS1"
|
||||
#endif
|
||||
MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CONFIG_SYS_CS3_WS)
|
||||
| CONFIG_SYS_CS3_PS | MCFCSM_CSCR_AA;
|
||||
|
||||
#if (CONFIG_SYS_CS3_RO != 0)
|
||||
MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS3_SIZE - 1)
|
||||
| MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
|
||||
#else
|
||||
MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS3_SIZE - 1)
|
||||
| MCFCSM_CSMR_V;
|
||||
#endif
|
||||
#else
|
||||
#warning "Chip Select 3 are not initialized/used"
|
||||
#endif
|
||||
/* FlexBus Chipselect */
|
||||
init_fbcs();
|
||||
|
||||
#endif /* CONFIG_MONITOR_IS_IN_RAM */
|
||||
|
||||
@ -571,6 +533,20 @@ void uart_port_conf(void)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
if (setclear) {
|
||||
MCFGPIO_PASPAR |= 0x0F00;
|
||||
MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
|
||||
} else {
|
||||
MCFGPIO_PASPAR &= 0xF0FF;
|
||||
MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_CMD_NET */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_M5249)
|
||||
@ -632,17 +608,8 @@ void cpu_init_f(void)
|
||||
mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
|
||||
mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
|
||||
|
||||
/*
|
||||
* Setup chip selects...
|
||||
*/
|
||||
|
||||
mbar_writeShort(MCFSIM_CSAR1, CONFIG_SYS_CSAR1);
|
||||
mbar_writeShort(MCFSIM_CSCR1, CONFIG_SYS_CSCR1);
|
||||
mbar_writeLong(MCFSIM_CSMR1, CONFIG_SYS_CSMR1);
|
||||
|
||||
mbar_writeShort(MCFSIM_CSAR0, CONFIG_SYS_CSAR0);
|
||||
mbar_writeShort(MCFSIM_CSCR0, CONFIG_SYS_CSCR0);
|
||||
mbar_writeLong(MCFSIM_CSMR0, CONFIG_SYS_CSMR0);
|
||||
/* FlexBus Chipselect */
|
||||
init_fbcs();
|
||||
|
||||
/* enable instruction cache now */
|
||||
icache_enable();
|
||||
|
@ -3,7 +3,7 @@
|
||||
* (C) Copyright 2000-2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
@ -56,6 +56,24 @@ int checkcpu(void)
|
||||
msk = (ccm->cir >> 6);
|
||||
ver = (ccm->cir & 0x003f);
|
||||
switch (msk) {
|
||||
#ifdef CONFIG_MCF5301x
|
||||
case 0x78:
|
||||
id = 53010;
|
||||
break;
|
||||
case 0x77:
|
||||
id = 53012;
|
||||
break;
|
||||
case 0x76:
|
||||
id = 53015;
|
||||
break;
|
||||
case 0x74:
|
||||
id = 53011;
|
||||
break;
|
||||
case 0x73:
|
||||
id = 53013;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_MCF532x
|
||||
case 0x54:
|
||||
id = 5329;
|
||||
break;
|
||||
@ -77,6 +95,7 @@ int checkcpu(void)
|
||||
case 0x6B:
|
||||
id = 5372;
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
|
||||
if (id) {
|
||||
@ -85,8 +104,8 @@ int checkcpu(void)
|
||||
printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
|
||||
ver);
|
||||
printf(" CPU CLK %s MHz BUS CLK %s MHz\n",
|
||||
strmhz(buf1, gd->cpu_clk)),
|
||||
strmhz(buf2, gd->bus_clk)));
|
||||
strmhz(buf1, gd->cpu_clk),
|
||||
strmhz(buf2, gd->bus_clk));
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
@ -3,7 +3,7 @@
|
||||
* (C) Copyright 2000-2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* (C) Copyright 2007 Freescale Semiconductor, Inc.
|
||||
* (C) Copyright 2004-2008 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
@ -27,16 +27,188 @@
|
||||
|
||||
#include <common.h>
|
||||
#include <watchdog.h>
|
||||
|
||||
#include <asm/immap.h>
|
||||
|
||||
/*
|
||||
* Breath some life into the CPU...
|
||||
*
|
||||
* Set up the memory map,
|
||||
* initialize a bunch of registers,
|
||||
* initialize the UPM's
|
||||
*/
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
#include <asm/fec.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MCF5301x
|
||||
void cpu_init_f(void)
|
||||
{
|
||||
volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
|
||||
volatile scm2_t *scm2 = (scm2_t *) MMAP_SCM2;
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
|
||||
|
||||
/* watchdog is enabled by default - disable the watchdog */
|
||||
#ifndef CONFIG_WATCHDOG
|
||||
/*wdog->cr = 0; */
|
||||
#endif
|
||||
|
||||
scm1->mpr = 0x77777777;
|
||||
scm1->pacra = 0;
|
||||
scm1->pacrb = 0;
|
||||
scm1->pacrc = 0;
|
||||
scm1->pacrd = 0;
|
||||
scm1->pacre = 0;
|
||||
scm1->pacrf = 0;
|
||||
scm1->pacrg = 0;
|
||||
|
||||
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
|
||||
&& defined(CONFIG_SYS_CS0_CTRL))
|
||||
gpio->par_cs |= GPIO_PAR_CS0_CS0;
|
||||
fbcs->csar0 = CONFIG_SYS_CS0_BASE;
|
||||
fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
|
||||
fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
|
||||
&& defined(CONFIG_SYS_CS1_CTRL))
|
||||
gpio->par_cs |= GPIO_PAR_CS1_CS1;
|
||||
fbcs->csar1 = CONFIG_SYS_CS1_BASE;
|
||||
fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
|
||||
fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
|
||||
&& defined(CONFIG_SYS_CS2_CTRL))
|
||||
fbcs->csar2 = CONFIG_SYS_CS2_BASE;
|
||||
fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
|
||||
fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
|
||||
&& defined(CONFIG_SYS_CS3_CTRL))
|
||||
fbcs->csar3 = CONFIG_SYS_CS3_BASE;
|
||||
fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
|
||||
fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
|
||||
&& defined(CONFIG_SYS_CS4_CTRL))
|
||||
gpio->par_cs |= GPIO_PAR_CS4;
|
||||
fbcs->csar4 = CONFIG_SYS_CS4_BASE;
|
||||
fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
|
||||
fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
|
||||
&& defined(CONFIG_SYS_CS5_CTRL))
|
||||
gpio->par_cs |= GPIO_PAR_CS5;
|
||||
fbcs->csar5 = CONFIG_SYS_CS5_BASE;
|
||||
fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
|
||||
fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_I2C
|
||||
gpio->par_feci2c = GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL;
|
||||
#endif
|
||||
|
||||
icache_enable();
|
||||
}
|
||||
|
||||
/* initialize higher level parts of CPU like timers */
|
||||
int cpu_init_r(void)
|
||||
{
|
||||
#ifdef CONFIG_MCFFEC
|
||||
volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
|
||||
#endif
|
||||
#ifdef CONFIG_MCFRTC
|
||||
volatile rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE);
|
||||
volatile rtcex_t *rtcex = (rtcex_t *) & rtc->extended;
|
||||
|
||||
rtcex->gocu = CONFIG_SYS_RTC_CNT;
|
||||
rtcex->gocl = CONFIG_SYS_RTC_SETUP;
|
||||
|
||||
#endif
|
||||
#ifdef CONFIG_MCFFEC
|
||||
if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE)
|
||||
ccm->misccr |= CCM_MISCCR_FECM;
|
||||
else
|
||||
ccm->misccr &= ~CCM_MISCCR_FECM;
|
||||
#endif
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
void uart_port_conf(void)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
|
||||
/* Setup Ports: */
|
||||
switch (CONFIG_SYS_UART_PORT) {
|
||||
case 0:
|
||||
gpio->par_uart = (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
|
||||
break;
|
||||
case 1:
|
||||
#ifdef CONFIG_SYS_UART1_ALT1_GPIO
|
||||
gpio->par_simp1h &=
|
||||
~(GPIO_PAR_SIMP1H_DATA1_MASK | GPIO_PAR_SIMP1H_VEN1_MASK);
|
||||
gpio->par_simp1h |=
|
||||
(GPIO_PAR_SIMP1H_DATA1_U1TXD | GPIO_PAR_SIMP1H_VEN1_U1RXD);
|
||||
#elif defined(CONFIG_SYS_UART1_ALT2_GPIO)
|
||||
gpio->par_ssih &=
|
||||
~(GPIO_PAR_SSIH_RXD_MASK | GPIO_PAR_SSIH_TXD_MASK);
|
||||
gpio->par_ssih |=
|
||||
(GPIO_PAR_SSIH_RXD_U1RXD | GPIO_PAR_SSIH_TXD_U1TXD);
|
||||
#endif
|
||||
break;
|
||||
case 2:
|
||||
#ifdef CONFIG_SYS_UART2_PRI_GPIO
|
||||
gpio->par_uart |= (GPIO_PAR_UART_U2TXD | GPIO_PAR_UART_U2RXD);
|
||||
#elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
|
||||
gpio->par_dspih &=
|
||||
~(GPIO_PAR_DSPIH_SIN_MASK | GPIO_PAR_DSPIH_SOUT_MASK);
|
||||
gpio->par_dspih |=
|
||||
(GPIO_PAR_DSPIH_SIN_U2RXD | GPIO_PAR_DSPIH_SOUT_U2TXD);
|
||||
#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
|
||||
gpio->par_feci2c &=
|
||||
~(GPIO_PAR_FECI2C_SDA_MASK | GPIO_PAR_FECI2C_SCL_MASK);
|
||||
gpio->par_feci2c |=
|
||||
(GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
struct fec_info_s *info = (struct fec_info_s *)dev->priv;
|
||||
|
||||
if (setclear) {
|
||||
if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
|
||||
gpio->par_fec |=
|
||||
GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC;
|
||||
gpio->par_feci2c |=
|
||||
GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0;
|
||||
} else {
|
||||
gpio->par_fec |=
|
||||
GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC;
|
||||
gpio->par_feci2c |=
|
||||
GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1;
|
||||
}
|
||||
} else {
|
||||
if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
|
||||
gpio->par_fec &=
|
||||
~(GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
|
||||
gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII0_MASK;
|
||||
} else {
|
||||
gpio->par_fec &=
|
||||
~(GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC);
|
||||
gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII1_MASK;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_CMD_NET */
|
||||
#endif /* CONFIG_MCF5301x */
|
||||
|
||||
#ifdef CONFIG_MCF532x
|
||||
void cpu_init_f(void)
|
||||
{
|
||||
volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
|
||||
@ -63,13 +235,15 @@ void cpu_init_f(void)
|
||||
/* Port configuration */
|
||||
gpio->par_cs = 0;
|
||||
|
||||
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
|
||||
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
|
||||
&& defined(CONFIG_SYS_CS0_CTRL))
|
||||
fbcs->csar0 = CONFIG_SYS_CS0_BASE;
|
||||
fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
|
||||
fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
|
||||
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
|
||||
&& defined(CONFIG_SYS_CS1_CTRL))
|
||||
/* Latch chipselect */
|
||||
gpio->par_cs |= GPIO_PAR_CS1;
|
||||
fbcs->csar1 = CONFIG_SYS_CS1_BASE;
|
||||
@ -77,28 +251,32 @@ void cpu_init_f(void)
|
||||
fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
|
||||
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
|
||||
&& defined(CONFIG_SYS_CS2_CTRL))
|
||||
gpio->par_cs |= GPIO_PAR_CS2;
|
||||
fbcs->csar2 = CONFIG_SYS_CS2_BASE;
|
||||
fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
|
||||
fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
|
||||
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
|
||||
&& defined(CONFIG_SYS_CS3_CTRL))
|
||||
gpio->par_cs |= GPIO_PAR_CS3;
|
||||
fbcs->csar3 = CONFIG_SYS_CS3_BASE;
|
||||
fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
|
||||
fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
|
||||
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
|
||||
&& defined(CONFIG_SYS_CS4_CTRL))
|
||||
gpio->par_cs |= GPIO_PAR_CS4;
|
||||
fbcs->csar4 = CONFIG_SYS_CS4_BASE;
|
||||
fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
|
||||
fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
|
||||
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
|
||||
&& defined(CONFIG_SYS_CS5_CTRL))
|
||||
gpio->par_cs |= GPIO_PAR_CS5;
|
||||
fbcs->csar5 = CONFIG_SYS_CS5_BASE;
|
||||
fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
|
||||
@ -139,3 +317,22 @@ void uart_port_conf(void)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
|
||||
if (setclear) {
|
||||
gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
|
||||
gpio->par_feci2c |=
|
||||
GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO;
|
||||
} else {
|
||||
gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
|
||||
gpio->par_feci2c &=
|
||||
~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
#endif /* CONFIG_MCF532x */
|
||||
|
@ -3,7 +3,7 @@
|
||||
* (C) Copyright 2000-2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
@ -36,26 +36,33 @@ DECLARE_GLOBAL_DATA_PTR;
|
||||
#define MAX_FVCO 500000 /* KHz */
|
||||
#define MAX_FSYS 80000 /* KHz */
|
||||
#define MIN_FSYS 58333 /* KHz */
|
||||
|
||||
#ifdef CONFIG_MCF5301x
|
||||
#define FREF 20000 /* KHz */
|
||||
#define MAX_MFD 63 /* Multiplier */
|
||||
#define MIN_MFD 0 /* Multiplier */
|
||||
#define USBDIV 8
|
||||
|
||||
/* Low Power Divider specifications */
|
||||
#define MIN_LPD (0) /* Divider (not encoded) */
|
||||
#define MAX_LPD (15) /* Divider (not encoded) */
|
||||
#define DEFAULT_LPD (0) /* Divider (not encoded) */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MCF532x
|
||||
#define FREF 16000 /* KHz */
|
||||
#define MAX_MFD 135 /* Multiplier */
|
||||
#define MIN_MFD 88 /* Multiplier */
|
||||
#define BUSDIV 6 /* Divider */
|
||||
/*
|
||||
* Low Power Divider specifications
|
||||
*/
|
||||
|
||||
/* Low Power Divider specifications */
|
||||
#define MIN_LPD (1 << 0) /* Divider (not encoded) */
|
||||
#define MAX_LPD (1 << 15) /* Divider (not encoded) */
|
||||
#define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Get the value of the current system clock
|
||||
*
|
||||
* Parameters:
|
||||
* none
|
||||
*
|
||||
* Return Value:
|
||||
* The current output system frequency
|
||||
*/
|
||||
#define BUSDIV 6 /* Divider */
|
||||
|
||||
/* Get the value of the current system clock */
|
||||
int get_sys_clock(void)
|
||||
{
|
||||
volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
|
||||
@ -65,9 +72,23 @@ int get_sys_clock(void)
|
||||
/* Test to see if device is in LIMP mode */
|
||||
if (ccm->misccr & CCM_MISCCR_LIMP) {
|
||||
divider = ccm->cdr & CCM_CDR_LPDIV(0xF);
|
||||
#ifdef CONFIG_MCF5301x
|
||||
return (FREF / (3 * (1 << divider)));
|
||||
#endif
|
||||
#ifdef CONFIG_MCF532x
|
||||
return (FREF / (2 << divider));
|
||||
#endif
|
||||
} else {
|
||||
#ifdef CONFIG_MCF5301x
|
||||
u32 pfdr = (pll->pcr & 0x3F) + 1;
|
||||
u32 refdiv = (1 << ((pll->pcr & PLL_PCR_REFDIV(7)) >> 8));
|
||||
u32 busdiv = ((pll->pdr & 0x00F0) >> 4) + 1;
|
||||
|
||||
return (((FREF * pfdr) / refdiv) / busdiv);
|
||||
#endif
|
||||
#ifdef CONFIG_MCF532x
|
||||
return ((FREF * pll->pfdr) / (BUSDIV * 4));
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
@ -92,7 +113,7 @@ int clock_limp(int div)
|
||||
div = MAX_LPD;
|
||||
|
||||
/* Save of the current value of the SSIDIV so we don't overwrite the value */
|
||||
temp = (ccm->cdr & CCM_CDR_SSIDIV(0xF));
|
||||
temp = (ccm->cdr & CCM_CDR_SSIDIV(0xFF));
|
||||
|
||||
/* Apply the divider to the system clock */
|
||||
ccm->cdr = (CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp));
|
||||
@ -102,15 +123,7 @@ int clock_limp(int div)
|
||||
return (FREF / (3 * (1 << div)));
|
||||
}
|
||||
|
||||
/*
|
||||
* Exit low power LIMP mode
|
||||
*
|
||||
* Parameters:
|
||||
* div Desired system frequency divider
|
||||
*
|
||||
* Return Value:
|
||||
* The resulting output system frequency
|
||||
*/
|
||||
/* Exit low power LIMP mode */
|
||||
int clock_exit_limp(void)
|
||||
{
|
||||
volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
|
||||
@ -139,7 +152,10 @@ int clock_exit_limp(void)
|
||||
*/
|
||||
int clock_pll(int fsys, int flags)
|
||||
{
|
||||
#ifdef CONFIG_MCF532x
|
||||
volatile u32 *sdram_workaround = (volatile u32 *)(MMAP_SDRAM + 0x80);
|
||||
#endif
|
||||
volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
|
||||
volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
|
||||
int fref, temp, fout, mfd;
|
||||
u32 i;
|
||||
@ -148,9 +164,17 @@ int clock_pll(int fsys, int flags)
|
||||
|
||||
if (fsys == 0) {
|
||||
/* Return current PLL output */
|
||||
#ifdef CONFIG_MCF5301x
|
||||
u32 busdiv = ((pll->pdr >> 4) & 0x0F) + 1;
|
||||
mfd = (pll->pcr & 0x3F) + 1;
|
||||
|
||||
return (fref * mfd) / busdiv;
|
||||
#endif
|
||||
#ifdef CONFIG_MCF532x
|
||||
mfd = pll->pfdr;
|
||||
|
||||
return (fref * mfd / (BUSDIV * 4));
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Check bounds of requested system clock */
|
||||
@ -160,21 +184,33 @@ int clock_pll(int fsys, int flags)
|
||||
if (fsys < MIN_FSYS)
|
||||
fsys = MIN_FSYS;
|
||||
|
||||
/* Multiplying by 100 when calculating the temp value,
|
||||
and then dividing by 100 to calculate the mfd allows
|
||||
for exact values without needing to include floating
|
||||
point libraries. */
|
||||
/*
|
||||
* Multiplying by 100 when calculating the temp value,
|
||||
* and then dividing by 100 to calculate the mfd allows
|
||||
* for exact values without needing to include floating
|
||||
* point libraries.
|
||||
*/
|
||||
temp = (100 * fsys) / fref;
|
||||
#ifdef CONFIG_MCF5301x
|
||||
mfd = (BUSDIV * temp) / 100;
|
||||
|
||||
/* Determine the output frequency for selected values */
|
||||
fout = ((fref * mfd) / BUSDIV);
|
||||
#endif
|
||||
#ifdef CONFIG_MCF532x
|
||||
mfd = (4 * BUSDIV * temp) / 100;
|
||||
|
||||
/* Determine the output frequency for selected values */
|
||||
fout = ((fref * mfd) / (BUSDIV * 4));
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Check to see if the SDRAM has already been initialized.
|
||||
* If it has then the SDRAM needs to be put into self refresh
|
||||
* mode before reprogramming the PLL.
|
||||
*/
|
||||
if (sdram->ctrl & SDRAMC_SDCR_REF)
|
||||
sdram->ctrl &= ~SDRAMC_SDCR_CKE;
|
||||
|
||||
/*
|
||||
* Initialize the PLL to generate the new system clock frequency.
|
||||
@ -184,20 +220,37 @@ int clock_pll(int fsys, int flags)
|
||||
/* Enter LIMP mode */
|
||||
clock_limp(DEFAULT_LPD);
|
||||
|
||||
#ifdef CONFIG_MCF5301x
|
||||
pll->pdr =
|
||||
PLL_PDR_OUTDIV1((BUSDIV / 3) - 1) |
|
||||
PLL_PDR_OUTDIV2(BUSDIV - 1) |
|
||||
PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) |
|
||||
PLL_PDR_OUTDIV4(USBDIV - 1);
|
||||
|
||||
pll->pcr &= PLL_PCR_FBDIV_MASK;
|
||||
pll->pcr |= PLL_PCR_FBDIV(mfd - 1);
|
||||
#endif
|
||||
#ifdef CONFIG_MCF532x
|
||||
/* Reprogram PLL for desired fsys */
|
||||
pll->podr = (PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV));
|
||||
|
||||
pll->pfdr = mfd;
|
||||
#endif
|
||||
|
||||
/* Exit LIMP mode */
|
||||
clock_exit_limp();
|
||||
|
||||
/*
|
||||
* Return the SDRAM to normal operation if it is in use.
|
||||
*/
|
||||
/* Return the SDRAM to normal operation if it is in use. */
|
||||
if (sdram->ctrl & SDRAMC_SDCR_REF)
|
||||
sdram->ctrl |= SDRAMC_SDCR_CKE;
|
||||
|
||||
/* software workaround for SDRAM opeartion after exiting LIMP mode errata */
|
||||
#ifdef CONFIG_MCF532x
|
||||
/*
|
||||
* software workaround for SDRAM opeartion after exiting LIMP
|
||||
* mode errata
|
||||
*/
|
||||
*sdram_workaround = CONFIG_SYS_SDRAM_BASE;
|
||||
#endif
|
||||
|
||||
/* wait for DQS logic to relock */
|
||||
for (i = 0; i < 0x200; i++) ;
|
||||
@ -205,9 +258,7 @@ int clock_pll(int fsys, int flags)
|
||||
return fout;
|
||||
}
|
||||
|
||||
/*
|
||||
* get_clocks() fills in gd->cpu_clock and gd->bus_clk
|
||||
*/
|
||||
/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
|
||||
int get_clocks(void)
|
||||
{
|
||||
gd->bus_clk = clock_pll(CONFIG_SYS_CLK / 1000, 0) * 1000;
|
||||
|
@ -2,6 +2,9 @@
|
||||
* Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
|
||||
* Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
|
||||
*
|
||||
* (C) Copyright 2004-2008 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
@ -140,6 +143,14 @@ _start:
|
||||
movec %d0, %ACR0
|
||||
movec %d0, %ACR1
|
||||
|
||||
#ifdef CONFIG_MCF5301x
|
||||
move.l #(0xFC0a0010), %a0
|
||||
move.w (%a0), %d0
|
||||
and.l %d0, 0xEFFF
|
||||
|
||||
move.w %d0, (%a0)
|
||||
#endif
|
||||
|
||||
/* initialize general use internal ram */
|
||||
move.l #0, %d0
|
||||
move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
|
||||
|
@ -27,10 +27,15 @@
|
||||
|
||||
#include <common.h>
|
||||
#include <watchdog.h>
|
||||
|
||||
#include <asm/immap.h>
|
||||
#include <asm/rtc.h>
|
||||
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
#include <asm/fec.h>
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Breath some life into the CPU...
|
||||
*
|
||||
@ -139,3 +144,30 @@ void uart_port_conf(void)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
struct fec_info_s *info = (struct fec_info_s *)dev->priv;
|
||||
|
||||
if (setclear) {
|
||||
gpio->par_feci2c |=
|
||||
(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
|
||||
|
||||
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
|
||||
gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
|
||||
else
|
||||
gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA;
|
||||
} else {
|
||||
gpio->par_feci2c &=
|
||||
~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
|
||||
|
||||
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
|
||||
gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK;
|
||||
else
|
||||
gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
@ -29,6 +29,12 @@
|
||||
#include <MCD_dma.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
#include <asm/fsl_mcdmafec.h>
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Breath some life into the CPU...
|
||||
*
|
||||
@ -130,3 +136,24 @@ void uart_port_conf(void)
|
||||
|
||||
*pscsicr &= 0xF8;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
struct fec_info_dma *info = (struct fec_info_dma *)dev->priv;
|
||||
|
||||
if (setclear) {
|
||||
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
|
||||
gpio->par_feci2cirq |= 0xF000;
|
||||
else
|
||||
gpio->par_feci2cirq |= 0x0FC0;
|
||||
} else {
|
||||
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
|
||||
gpio->par_feci2cirq &= 0x0FFF;
|
||||
else
|
||||
gpio->par_feci2cirq &= 0xF03F;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
@ -43,33 +43,33 @@
|
||||
#define GPT_ENTRY_NAME "gpt"
|
||||
|
||||
#define EFI_GUID(a,b,c,d0,d1,d2,d3,d4,d5,d6,d7) \
|
||||
((efi_guid_t) \
|
||||
{{ (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, ((a) >> 24) & 0xff, \
|
||||
(b) & 0xff, ((b) >> 8) & 0xff, \
|
||||
(c) & 0xff, ((c) >> 8) & 0xff, \
|
||||
(d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }})
|
||||
((efi_guid_t) \
|
||||
{{ (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, ((a) >> 24) & 0xff, \
|
||||
(b) & 0xff, ((b) >> 8) & 0xff, \
|
||||
(c) & 0xff, ((c) >> 8) & 0xff, \
|
||||
(d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }})
|
||||
|
||||
#define PARTITION_SYSTEM_GUID \
|
||||
EFI_GUID( 0xC12A7328, 0xF81F, 0x11d2, \
|
||||
0xBA, 0x4B, 0x00, 0xA0, 0xC9, 0x3E, 0xC9, 0x3B)
|
||||
EFI_GUID( 0xC12A7328, 0xF81F, 0x11d2, \
|
||||
0xBA, 0x4B, 0x00, 0xA0, 0xC9, 0x3E, 0xC9, 0x3B)
|
||||
#define LEGACY_MBR_PARTITION_GUID \
|
||||
EFI_GUID( 0x024DEE41, 0x33E7, 0x11d3, \
|
||||
0x9D, 0x69, 0x00, 0x08, 0xC7, 0x81, 0xF3, 0x9F)
|
||||
EFI_GUID( 0x024DEE41, 0x33E7, 0x11d3, \
|
||||
0x9D, 0x69, 0x00, 0x08, 0xC7, 0x81, 0xF3, 0x9F)
|
||||
#define PARTITION_MSFT_RESERVED_GUID \
|
||||
EFI_GUID( 0xE3C9E316, 0x0B5C, 0x4DB8, \
|
||||
0x81, 0x7D, 0xF9, 0x2D, 0xF0, 0x02, 0x15, 0xAE)
|
||||
EFI_GUID( 0xE3C9E316, 0x0B5C, 0x4DB8, \
|
||||
0x81, 0x7D, 0xF9, 0x2D, 0xF0, 0x02, 0x15, 0xAE)
|
||||
#define PARTITION_BASIC_DATA_GUID \
|
||||
EFI_GUID( 0xEBD0A0A2, 0xB9E5, 0x4433, \
|
||||
0x87, 0xC0, 0x68, 0xB6, 0xB7, 0x26, 0x99, 0xC7)
|
||||
EFI_GUID( 0xEBD0A0A2, 0xB9E5, 0x4433, \
|
||||
0x87, 0xC0, 0x68, 0xB6, 0xB7, 0x26, 0x99, 0xC7)
|
||||
#define PARTITION_LINUX_RAID_GUID \
|
||||
EFI_GUID( 0xa19d880f, 0x05fc, 0x4d3b, \
|
||||
0xa0, 0x06, 0x74, 0x3f, 0x0f, 0x84, 0x91, 0x1e)
|
||||
EFI_GUID( 0xa19d880f, 0x05fc, 0x4d3b, \
|
||||
0xa0, 0x06, 0x74, 0x3f, 0x0f, 0x84, 0x91, 0x1e)
|
||||
#define PARTITION_LINUX_SWAP_GUID \
|
||||
EFI_GUID( 0x0657fd6d, 0xa4ab, 0x43c4, \
|
||||
0x84, 0xe5, 0x09, 0x33, 0xc8, 0x4b, 0x4f, 0x4f)
|
||||
EFI_GUID( 0x0657fd6d, 0xa4ab, 0x43c4, \
|
||||
0x84, 0xe5, 0x09, 0x33, 0xc8, 0x4b, 0x4f, 0x4f)
|
||||
#define PARTITION_LINUX_LVM_GUID \
|
||||
EFI_GUID( 0xe6d6d379, 0xf507, 0x44c2, \
|
||||
0xa2, 0x3c, 0x23, 0x8f, 0x2a, 0x3d, 0xf9, 0x28)
|
||||
EFI_GUID( 0xe6d6d379, 0xf507, 0x44c2, \
|
||||
0xa2, 0x3c, 0x23, 0x8f, 0x2a, 0x3d, 0xf9, 0x28)
|
||||
|
||||
/* linux/include/efi.h */
|
||||
typedef unsigned short efi_char16_t;
|
||||
@ -80,14 +80,14 @@ typedef struct {
|
||||
|
||||
/* based on linux/include/genhd.h */
|
||||
struct partition {
|
||||
unsigned char boot_ind; /* 0x80 - active */
|
||||
unsigned char head; /* starting head */
|
||||
unsigned char sector; /* starting sector */
|
||||
unsigned char cyl; /* starting cylinder */
|
||||
unsigned char sys_ind; /* What partition type */
|
||||
unsigned char end_head; /* end head */
|
||||
unsigned char boot_ind; /* 0x80 - active */
|
||||
unsigned char head; /* starting head */
|
||||
unsigned char sector; /* starting sector */
|
||||
unsigned char cyl; /* starting cylinder */
|
||||
unsigned char sys_ind; /* What partition type */
|
||||
unsigned char end_head; /* end head */
|
||||
unsigned char end_sector; /* end sector */
|
||||
unsigned char end_cyl; /* end cylinder */
|
||||
unsigned char end_cyl; /* end cylinder */
|
||||
unsigned char start_sect[4]; /* starting sector counting from 0 */
|
||||
unsigned char nr_sects[4]; /* nr of sectors in partition */
|
||||
} __attribute__ ((packed));
|
||||
@ -135,4 +135,4 @@ typedef struct _legacy_mbr {
|
||||
unsigned char signature[2];
|
||||
} __attribute__ ((packed)) legacy_mbr;
|
||||
|
||||
#endif /* _DISK_PART_EFI_H */
|
||||
#endif /* _DISK_PART_EFI_H */
|
||||
|
181
doc/README.m53017evb
Normal file
181
doc/README.m53017evb
Normal file
@ -0,0 +1,181 @@
|
||||
Freescale MCF53017EVB ColdFire Development Board
|
||||
================================================
|
||||
|
||||
TsiChung Liew(Tsi-Chung.Liew@freescale.com)
|
||||
Created 10/22/08
|
||||
===========================================
|
||||
|
||||
|
||||
Changed files:
|
||||
==============
|
||||
|
||||
- board/freescale/m53017evb/m53017evb.c Dram setup
|
||||
- board/freescale/m53017evb/mii.c Mii access
|
||||
- board/freescale/m53017evb/Makefile Makefile
|
||||
- board/freescale/m53017evb/config.mk config make
|
||||
- board/freescale/m53017evb/u-boot.lds Linker description
|
||||
|
||||
- cpu/mcf532x/cpu.c cpu specific code
|
||||
- cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs
|
||||
- cpu/mcf532x/interrupts.c cpu specific interrupt support
|
||||
- cpu/mcf532x/speed.c system, flexbus, and cpu clock
|
||||
- cpu/mcf532x/Makefile Makefile
|
||||
- cpu/mcf532x/config.mk config make
|
||||
- cpu/mcf532x/start.S start up assembly code
|
||||
|
||||
- doc/README.m53017evb This readme file
|
||||
|
||||
- drivers/net/mcffec.c ColdFire common FEC driver
|
||||
- drivers/net/mcfmii.c ColdFire common Mii driver
|
||||
- drivers/serial/mcfuart.c ColdFire common UART driver
|
||||
- drivers/rtc/mcfrtc.c Realtime clock Driver
|
||||
|
||||
- include/asm-m68k/bitops.h Bit operation function export
|
||||
- include/asm-m68k/byteorder.h Byte order functions
|
||||
- include/asm-m68k/fec.h FEC structure and definition
|
||||
- include/asm-m68k/fsl_i2c.h I2C structure and definition
|
||||
- include/asm-m68k/global_data.h Global data structure
|
||||
- include/asm-m68k/immap.h ColdFire specific header file and driver macros
|
||||
- include/asm-m68k/immap_5301x.h mcf5301x specific header file
|
||||
- include/asm-m68k/io.h io functions
|
||||
- include/asm-m68k/m532x.h mcf5301x specific header file
|
||||
- include/asm-m68k/posix_types.h Posix
|
||||
- include/asm-m68k/processor.h header file
|
||||
- include/asm-m68k/ptrace.h Exception structure
|
||||
- include/asm-m68k/rtc.h Realtime clock header file
|
||||
- include/asm-m68k/string.h String function export
|
||||
- include/asm-m68k/timer.h Timer structure and definition
|
||||
- include/asm-m68k/types.h Data types definition
|
||||
- include/asm-m68k/uart.h Uart structure and definition
|
||||
- include/asm-m68k/u-boot.h u-boot structure
|
||||
|
||||
- include/configs/M53017EVB.h Board specific configuration file
|
||||
|
||||
- lib_m68k/board.c board init function
|
||||
- lib_m68k/cache.c
|
||||
- lib_m68k/interrupts Coldfire common interrupt functions
|
||||
- lib_m68k/m68k_linux.c
|
||||
- lib_m68k/time.c Timer functions (Dma timer and PIT)
|
||||
- lib_m68k/traps.c Exception init code
|
||||
|
||||
1 MCF5301x specific Options/Settings
|
||||
====================================
|
||||
1.1 pre-loader is no longer suppoer in thie coldfire family
|
||||
|
||||
1.2 Configuration settings for M53017EVB Development Board
|
||||
CONFIG_MCF5301x -- define for all MCF5301x CPUs
|
||||
CONFIG_M53015 -- define for MCF53015 CPUs
|
||||
CONFIG_M53017EVB -- define for M53017EVB board
|
||||
|
||||
CONFIG_MCFUART -- define to use common CF Uart driver
|
||||
CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2
|
||||
CONFIG_BAUDRATE -- define UART baudrate
|
||||
|
||||
CONFIG_MCFRTC -- define to use common CF RTC driver
|
||||
CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h
|
||||
CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency
|
||||
RTC_DEBUG -- define to show RTC debug message
|
||||
CONFIG_CMD_DATE -- enable to use date feature in u-boot
|
||||
|
||||
CONFIG_MCFFEC -- define to use common CF FEC driver
|
||||
CONFIG_NET_MULTI -- define to use multi FEC in u-boot
|
||||
CONFIG_MII -- enable to use MII driver
|
||||
CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c
|
||||
CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery
|
||||
CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer
|
||||
CONFIG_SYS_FAULT_ECHO_LINK_DOWN --
|
||||
CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration
|
||||
CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register
|
||||
MCFFEC_TOUT_LOOP -- set FEC timeout loop
|
||||
|
||||
CONFIG_MCFTMR -- define to use DMA timer
|
||||
CONFIG_MCFPIT -- define to use PIT timer
|
||||
|
||||
CONFIG_FSL_I2C -- define to use FSL common I2C driver
|
||||
CONFIG_HARD_I2C -- define for I2C hardware support
|
||||
CONFIG_SOFT_I2C -- define for I2C bit-banged
|
||||
CONFIG_SYS_I2C_SPEED -- define for I2C speed
|
||||
CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
|
||||
CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset
|
||||
CONFIG_SYS_IMMR -- define for MBAR offset
|
||||
|
||||
CONFIG_SYS_MBAR -- define MBAR offset
|
||||
|
||||
CONFIG_MONITOR_IS_IN_RAM -- Not support
|
||||
|
||||
CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5301x internal SRAM
|
||||
|
||||
CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register
|
||||
CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
|
||||
CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
|
||||
|
||||
CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base
|
||||
|
||||
2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
|
||||
===========================================
|
||||
2.1. System memory map:
|
||||
Flash: 0x00000000-0x3FFFFFFF (1024MB)
|
||||
DDR: 0x40000000-0x7FFFFFFF (1024MB)
|
||||
SRAM: 0x80000000-0x8FFFFFFF (256MB)
|
||||
IP: 0xFC000000-0xFFFFFFFF (256MB)
|
||||
|
||||
2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and
|
||||
linux kernel, you can customize it based on your system requirements:
|
||||
Flash0: 0x00000000-0x00FFFFFF (16MB)
|
||||
DDR: 0x40000000-0x4FFFFFFF (256MB)
|
||||
SRAM: 0x80000000-0x80007FFF (32KB)
|
||||
IP: 0xFC000000-0xFC0FFFFF (64KB)
|
||||
|
||||
3. COMPILATION
|
||||
==============
|
||||
3.1 To create U-Boot the gcc-4.x-xx compiler set (ColdFire ELF or
|
||||
uClinux version) from codesourcery.com was used. Download it from:
|
||||
http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
|
||||
|
||||
3.2 Compilation
|
||||
export CROSS_COMPILE=cross-compile-prefix
|
||||
cd u-boot
|
||||
make distclean
|
||||
make M53017EVB_config
|
||||
make
|
||||
|
||||
4. SCREEN DUMP
|
||||
==============
|
||||
4.1 M53017EVB Development board
|
||||
(NOTE: May not show exactly the same)
|
||||
|
||||
U-Boot 2008.10 (Oct 22 2007 - 11:07:57)
|
||||
|
||||
CPU: Freescale MCF53015 (Mask:76 Version:0)
|
||||
CPU CLK 240 Mhz BUS CLK 80 Mhz
|
||||
Board: Freescale M53017EVB
|
||||
I2C: ready
|
||||
DRAM: 64 MB
|
||||
FLASH: 16 MB
|
||||
In: serial
|
||||
Out: serial
|
||||
Err: serial
|
||||
NAND: 16 MiB
|
||||
Net: FEC0, FEC1
|
||||
-> print
|
||||
bootdelay=1
|
||||
baudrate=115200
|
||||
ethaddr=00:e0:0c:bc:e5:60
|
||||
hostname=M53017EVB
|
||||
netdev=eth0
|
||||
loadaddr=40010000
|
||||
u-boot=u-boot.bin
|
||||
load=tftp ${loadaddr) ${u-boot}
|
||||
upd=run load; run prog
|
||||
prog=prot off 0 3ffff;era 0 3ffff;cp.b ${loadaddr} 0 ${filesize};save
|
||||
gatewayip=192.168.1.1
|
||||
netmask=255.255.255.0
|
||||
ipaddr=192.168.1.3
|
||||
serverip=192.168.1.2
|
||||
stdin=serial
|
||||
stdout=serial
|
||||
stderr=serial
|
||||
mem=65024k
|
||||
|
||||
Environment size: 437/4092 bytes
|
||||
->
|
@ -20,7 +20,6 @@
|
||||
#include <asm/arch/at91rm9200.h>
|
||||
#elif defined(CONFIG_AT91SAM9260)
|
||||
#include <asm/arch/at91sam9260.h>
|
||||
#define AT91_BASE_EMAC AT91SAM9260_BASE_EMAC
|
||||
#define AT91_BASE_SPI AT91SAM9260_BASE_SPI0
|
||||
#define AT91_ID_UHP AT91SAM9260_ID_UHP
|
||||
#define AT91_PMC_UHP AT91SAM926x_PMC_UHP
|
||||
@ -31,7 +30,6 @@
|
||||
#define AT91_PMC_UHP AT91SAM926x_PMC_UHP
|
||||
#elif defined(CONFIG_AT91SAM9263)
|
||||
#include <asm/arch/at91sam9263.h>
|
||||
#define AT91_BASE_EMAC AT91SAM9263_BASE_EMAC
|
||||
#define AT91_BASE_SPI AT91SAM9263_BASE_SPI0
|
||||
#define AT91_ID_UHP AT91SAM9263_ID_UHP
|
||||
#define AT91_PMC_UHP AT91SAM926x_PMC_UHP
|
||||
@ -41,7 +39,6 @@
|
||||
#define AT91_ID_UHP AT91SAM9RL_ID_UHP
|
||||
#elif defined(CONFIG_AT91CAP9)
|
||||
#include <asm/arch/at91cap9.h>
|
||||
#define AT91_BASE_EMAC AT91CAP9_BASE_EMAC
|
||||
#define AT91_BASE_SPI AT91CAP9_BASE_SPI0
|
||||
#define AT91_ID_UHP AT91CAP9_ID_UHP
|
||||
#define AT91_PMC_UHP AT91CAP9_PMC_UHP
|
||||
|
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue
Block a user