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ppc: Remove ARCH_P1022 support 

With the last of the ARCH_P1022 platforms removed, finish removing the
rest of the platform support.

Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Tom Rini 2021-02-20 20:06:26 -05:00
parent a84ea228bc
commit 3238d9340e
6 changed files with 2 additions and 171 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
arch/powerpc/cpu/mpc85xx/Kconfig
View File

@ -564,23 +564,6 @@ config ARCH_P1021
imply CMD_REGINFO
imply SATA_SIL
config ARCH_P1022
bool
select FSL_LAW
select SYS_FSL_ERRATUM_A004477
select SYS_FSL_ERRATUM_A004508
select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_ELBC_A001
select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_ERRATUM_SATA_A001
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
select FSL_ELBC
config ARCH_P1023
bool
select FSL_LAW
@ -1023,7 +1006,6 @@ config MAX_CPUS
ARCH_MPC8572 || \
ARCH_P1020 || \
ARCH_P1021 || \
ARCH_P1022 || \
ARCH_P1023 || \
ARCH_P1024 || \
ARCH_P1025 || \
@ -1057,7 +1039,6 @@ config SYS_CCSRBAR_DEFAULT
ARCH_P1011 || \
ARCH_P1020 || \
ARCH_P1021 || \
ARCH_P1022 || \
ARCH_P1024 || \
ARCH_P1025 || \
ARCH_P2020
@ -1275,7 +1256,6 @@ config SYS_FSL_NUM_LAWS
ARCH_P1011 || \
ARCH_P1020 || \
ARCH_P1021 || \
ARCH_P1022 || \
ARCH_P1023 || \
ARCH_P1024 || \
ARCH_P1025 || \
@ -1325,7 +1305,6 @@ config SYS_PPC_E500_DEBUG_TLB
ARCH_P1011 || \
ARCH_P1020 || \
ARCH_P1021 || \
ARCH_P1022 || \
ARCH_P1024 || \
ARCH_P1025 || \
ARCH_P2020

1
arch/powerpc/cpu/mpc85xx/Makefile
View File

@ -69,7 +69,6 @@ obj-$(CONFIG_ARCH_P1010) += p1010_serdes.o
obj-$(CONFIG_ARCH_P1011) += p1021_serdes.o
obj-$(CONFIG_ARCH_P1020) += p1021_serdes.o
obj-$(CONFIG_ARCH_P1021) += p1021_serdes.o
obj-$(CONFIG_ARCH_P1022) += p1022_serdes.o
obj-$(CONFIG_ARCH_P1023) += p1023_serdes.o
obj-$(CONFIG_ARCH_P1024) += p1021_serdes.o
obj-$(CONFIG_ARCH_P1025) += p1021_serdes.o

129
arch/powerpc/cpu/mpc85xx/p1022_serdes.c
View File

@ -1,129 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2010 Freescale Semiconductor, Inc.
* Author: Timur Tabi <timur@freescale.com>
*/
#include <config.h>
#include <common.h>
#include <log.h>
#include <asm/io.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
#define SRDS1_MAX_LANES 4
#define SRDS2_MAX_LANES 2
static u32 serdes1_prtcl_map, serdes2_prtcl_map;
static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
[0x00] = {NONE, NONE, NONE, NONE},
[0x01] = {NONE, NONE, NONE, NONE},
[0x02] = {NONE, NONE, NONE, NONE},
[0x03] = {NONE, NONE, NONE, NONE},
[0x04] = {NONE, NONE, NONE, NONE},
[0x06] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2},
[0x07] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2},
[0x09] = {PCIE1, NONE, NONE, NONE},
[0x0a] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2},
[0x0b] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2},
[0x0d] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
[0x0e] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
[0x0f] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
[0x15] = {PCIE1, PCIE3, PCIE2, PCIE2},
[0x16] = {PCIE1, PCIE3, PCIE2, PCIE2},
[0x17] = {PCIE1, PCIE3, PCIE2, PCIE2},
[0x18] = {PCIE1, PCIE1, PCIE2, PCIE2},
[0x19] = {PCIE1, PCIE1, PCIE2, PCIE2},
[0x1a] = {PCIE1, PCIE1, PCIE2, PCIE2},
[0x1b] = {PCIE1, PCIE1, PCIE2, PCIE2},
[0x1c] = {PCIE1, PCIE1, PCIE1, PCIE1},
[0x1d] = {PCIE1, PCIE1, PCIE2, PCIE2},
[0x1e] = {PCIE1, PCIE1, PCIE2, PCIE2},
[0x1f] = {PCIE1, PCIE1, PCIE2, PCIE2},
};
static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
[0x00] = {PCIE3, PCIE3},
[0x01] = {PCIE2, PCIE3},
[0x02] = {SATA1, SATA2},
[0x03] = {SGMII_TSEC1, SGMII_TSEC2},
[0x04] = {NONE, NONE},
[0x06] = {SATA1, SATA2},
[0x07] = {NONE, NONE},
[0x09] = {PCIE3, PCIE2},
[0x0a] = {SATA1, SATA2},
[0x0b] = {NONE, NONE},
[0x0d] = {PCIE3, PCIE2},
[0x0e] = {SATA1, SATA2},
[0x0f] = {NONE, NONE},
[0x15] = {SGMII_TSEC1, SGMII_TSEC2},
[0x16] = {SATA1, SATA2},
[0x17] = {NONE, NONE},
[0x18] = {PCIE3, PCIE3},
[0x19] = {SGMII_TSEC1, SGMII_TSEC2},
[0x1a] = {SATA1, SATA2},
[0x1b] = {NONE, NONE},
[0x1c] = {PCIE3, PCIE3},
[0x1d] = {SGMII_TSEC1, SGMII_TSEC2},
[0x1e] = {SATA1, SATA2},
[0x1f] = {NONE, NONE},
};
int is_serdes_configured(enum srds_prtcl device)
{
int ret;
if (!(serdes1_prtcl_map & (1 << NONE)))
fsl_serdes_init();
ret = (1 << device) & serdes1_prtcl_map;
if (ret)
return ret;
if (!(serdes2_prtcl_map & (1 << NONE)))
fsl_serdes_init();
return (1 << device) & serdes2_prtcl_map;
}
void fsl_serdes_init(void)
{
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
int lane;
if (serdes1_prtcl_map & (1 << NONE) &&
serdes2_prtcl_map & (1 << NONE))
return;
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
serdes1_prtcl_map |= (1 << lane_prtcl);
}
/* Set the first bit to indicate serdes has been initialized */
serdes1_prtcl_map |= (1 << NONE);
if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
serdes2_prtcl_map |= (1 << lane_prtcl);
}
/* Set the first bit to indicate serdes has been initialized */
serdes2_prtcl_map |= (1 << NONE);
}

3
arch/powerpc/cpu/mpc85xx/speed.c
View File

@ -608,8 +608,7 @@ int get_clocks(void)
* AN2919.
*/
#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
defined(CONFIG_ARCH_MPC8560) || defined(CONFIG_ARCH_MPC8555) || \
defined(CONFIG_ARCH_P1022)
defined(CONFIG_ARCH_MPC8560) || defined(CONFIG_ARCH_MPC8555)
gd->arch.i2c1_clk = sys_info.freq_systembus;
#elif defined(CONFIG_ARCH_MPC8544)
/*

4
arch/powerpc/include/asm/config_mpc85xx.h
View File

@ -66,10 +66,6 @@
#define QE_NUM_OF_SNUM 28
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#elif defined(CONFIG_ARCH_P1022)
#define CONFIG_TSECV2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#elif defined(CONFIG_ARCH_P1023)
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 2

15
arch/powerpc/include/asm/immap_85xx.h
View File

@ -2157,10 +2157,7 @@ typedef struct ccsr_gur {
#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
#define MPC85xx_PORDEVSR_PCI1 0x00800000
#if defined(CONFIG_ARCH_P1022)
#define MPC85xx_PORDEVSR_IO_SEL 0x007c0000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18
#elif defined(CONFIG_ARCH_P1023)
#if defined(CONFIG_ARCH_P1023)
#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
#else
@ -2278,12 +2275,6 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR_QE11 0x00000010
#define MPC85xx_PMUXCR_QE12 0x00000008
#endif
#if defined(CONFIG_ARCH_P1022)
#define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00
#define MPC85xx_PMUXCR_TDM 0x00014800
#define MPC85xx_PMUXCR_SPI_MASK 0x00600000
#define MPC85xx_PMUXCR_SPI 0x00000000
#endif
#if defined(CONFIG_ARCH_BSC9131)
#define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000
#define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000
@ -2363,10 +2354,6 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000
#define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000
#endif
#if defined(CONFIG_ARCH_P1022)
#define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000
#define MPC85xx_PMUXCR2_USB 0x00150000
#endif
#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
#if defined(CONFIG_ARCH_BSC9131)
#define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000