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https://github.com/brain-hackers/u-boot-brain
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ARM: dts: uniphier: update PXs3 SoC/board DT
Support PXs3 SoC and its reference development board. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Masahiro Yamada
parent
6c9e46efae
commit
31c86aa7fd
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@ -4,13 +4,12 @@
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* Copyright (C) 2017 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+ X11
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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*/
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/dts-v1/;
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/include/ "uniphier-pxs3.dtsi"
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/include/ "uniphier-ref-daughter.dtsi"
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/include/ "uniphier-support-card.dtsi"
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#include "uniphier-pxs3.dtsi"
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#include "uniphier-support-card.dtsi"
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/ {
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model = "UniPhier PXs3 Reference Board";
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@ -39,7 +38,7 @@
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};
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ðsc {
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interrupts = <0 48 4>;
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interrupts = <0 52 4>;
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};
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&serial0 {
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@ -49,3 +48,23 @@
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&i2c0 {
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status = "okay";
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};
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&i2c1 {
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status = "okay";
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};
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&i2c2 {
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status = "okay";
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};
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&i2c3 {
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status = "okay";
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};
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&usb0 {
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status = "okay";
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};
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&usb1 {
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status = "okay";
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};
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@ -4,46 +4,10 @@
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* Copyright (C) 2017 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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*/
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/memreserve/ 0x80000000 0x00080000;
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/memreserve/ 0x80000000 0x02000000;
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/ {
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compatible = "socionext,uniphier-pxs3";
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@ -76,28 +40,74 @@
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0 0x000>;
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clocks = <&sys_clk 33>;
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enable-method = "psci";
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operating-points-v2 = <&cluster0_opp>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0 0x001>;
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clocks = <&sys_clk 33>;
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enable-method = "psci";
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operating-points-v2 = <&cluster0_opp>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0 0x002>;
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clocks = <&sys_clk 33>;
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enable-method = "psci";
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operating-points-v2 = <&cluster0_opp>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0 0x003>;
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clocks = <&sys_clk 33>;
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enable-method = "psci";
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operating-points-v2 = <&cluster0_opp>;
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};
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};
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cluster0_opp: opp_table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-250000000 {
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opp-hz = /bits/ 64 <250000000>;
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clock-latency-ns = <300>;
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};
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opp-325000000 {
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opp-hz = /bits/ 64 <325000000>;
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clock-latency-ns = <300>;
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};
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opp-500000000 {
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opp-hz = /bits/ 64 <500000000>;
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clock-latency-ns = <300>;
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};
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opp-650000000 {
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opp-hz = /bits/ 64 <650000000>;
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clock-latency-ns = <300>;
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};
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opp-666667000 {
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opp-hz = /bits/ 64 <666667000>;
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clock-latency-ns = <300>;
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};
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opp-866667000 {
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opp-hz = /bits/ 64 <866667000>;
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clock-latency-ns = <300>;
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};
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opp-1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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clock-latency-ns = <300>;
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};
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opp-1300000000 {
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opp-hz = /bits/ 64 <1300000000>;
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clock-latency-ns = <300>;
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};
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};
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@ -172,6 +182,22 @@
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clock-frequency = <58820000>;
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};
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gpio: gpio@55000000 {
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compatible = "socionext,uniphier-pxs3-gpio";
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reg = <0x55000000 0x200>;
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interrupt-parent = <&aidet>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 0 0>,
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<&pinctrl 96 0 0>,
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<&pinctrl 160 0 0>;
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gpio-ranges-group-names = "gpio_range0",
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"gpio_range1",
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"gpio_range2";
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};
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i2c0: i2c@58780000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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@ -205,6 +231,8 @@
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 43 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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clocks = <&peri_clk 6>;
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clock-frequency = <100000>;
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};
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@ -251,7 +279,7 @@
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sdctrl@59810000 {
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compatible = "socionext,uniphier-pxs3-sdctrl",
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"simple-mfd", "syscon";
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reg = <0x59810000 0x800>;
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reg = <0x59810000 0x400>;
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sd_clk: clock {
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compatible = "socionext,uniphier-pxs3-sd-clock";
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@ -282,7 +310,6 @@
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emmc: sdhc@5a000000 {
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compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
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status = "disabled";
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reg = <0x5a000000 0x400>;
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interrupts = <0 78 4>;
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pinctrl-names = "default";
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@ -291,6 +318,11 @@
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bus-width = <8>;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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cdns,phy-input-delay-legacy = <4>;
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cdns,phy-input-delay-mmc-highspeed = <2>;
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cdns,phy-input-delay-mmc-ddr = <3>;
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cdns,phy-dll-delay-sdclk = <21>;
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cdns,phy-dll-delay-sdclk-hsmmc = <21>;
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};
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sd: sdhc@5a400000 {
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@ -317,9 +349,11 @@
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};
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};
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aidet@5fc20000 {
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compatible = "simple-mfd", "syscon";
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aidet: aidet@5fc20000 {
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compatible = "socionext,uniphier-pxs3-aidet";
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reg = <0x5fc20000 0x200>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gic: interrupt-controller@5fe00000 {
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@ -345,10 +379,50 @@
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compatible = "socionext,uniphier-pxs3-reset";
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#reset-cells = <1>;
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};
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watchdog {
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compatible = "socionext,uniphier-wdt";
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};
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};
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usb0: usb@65b00000 {
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compatible = "socionext,uniphier-pxs3-dwc3";
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status = "disabled";
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reg = <0x65b00000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
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dwc3@65a00000 {
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compatible = "snps,dwc3";
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reg = <0x65a00000 0x10000>;
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interrupts = <0 134 4>;
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dr_mode = "host";
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tx-fifo-resize;
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};
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};
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usb1: usb@65d00000 {
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compatible = "socionext,uniphier-pxs3-dwc3";
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status = "disabled";
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reg = <0x65d00000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
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dwc3@65c00000 {
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compatible = "snps,dwc3";
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reg = <0x65c00000 0x10000>;
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interrupts = <0 137 4>;
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dr_mode = "host";
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tx-fifo-resize;
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};
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};
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nand: nand@68000000 {
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compatible = "socionext,denali-nand-v5b";
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compatible = "socionext,uniphier-denali-nand-v5b";
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status = "disabled";
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reg-names = "nand_data", "denali_reg";
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reg = <0x68000000 0x20>, <0x68100000 0x1000>;
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@ -356,9 +430,8 @@
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_nand>;
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clocks = <&sys_clk 2>;
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nand-ecc-strength = <8>;
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};
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};
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};
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/include/ "uniphier-pinctrl.dtsi"
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#include "uniphier-pinctrl.dtsi"
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