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Merge branch 'remove-config-nr-dram-banks-v9-2020-08-26' of https://gitlab.denx.de/u-boot/custodians/u-boot-marvell into next

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This commit is contained in:
Tom Rini 2020-09-07 14:31:00 -04:00
commit 314b9b4a38
37 changed files with 40 additions and 141 deletions
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3
api/api_platform-mips.c
View File

@ -24,8 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
int platform_sys_info(struct sys_info *si)
{
platform_set_mr(si, gd->bd->bi_memstart,
gd->bd->bi_memsize, MR_ATTR_DRAM);
platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM);
return 1;
}

2
api/api_platform-powerpc.c
View File

@ -42,7 +42,7 @@ int platform_sys_info(struct sys_info *si)
si->bar = 0;
#endif
platform_set_mr(si, gd->bd->bi_memstart, gd->bd->bi_memsize, MR_ATTR_DRAM);
platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM);
platform_set_mr(si, gd->bd->bi_flashstart, gd->bd->bi_flashsize, MR_ATTR_FLASH);
platform_set_mr(si, gd->bd->bi_sramstart, gd->bd->bi_sramsize, MR_ATTR_SRAM);

2
arch/mips/lib/boot.c
View File

@ -17,7 +17,7 @@ unsigned long do_go_exec(ulong (*entry)(int, char * const []),
* whole SDRAM area, since we don't know the size of the image
* that was loaded.
*/
flush_cache(gd->bd->bi_memstart, gd->ram_top - gd->bd->bi_memstart);
flush_cache(gd->ram_base, gd->ram_top - gd->ram_base);
return entry(argc, argv);
}

2
arch/mips/lib/bootm.c
View File

@ -242,7 +242,7 @@ static int boot_reloc_fdt(bootm_headers_t *images)
#if CONFIG_IS_ENABLED(MIPS_BOOT_FDT) && CONFIG_IS_ENABLED(OF_LIBFDT)
int arch_fixup_fdt(void *blob)
{
u64 mem_start = virt_to_phys((void *)gd->bd->bi_memstart);
u64 mem_start = virt_to_phys((void *)gd->ram_base);
u64 mem_size = gd->ram_size;
return fdt_fixup_memory_banks(blob, &mem_start, &mem_size, 1);

2
arch/powerpc/cpu/mpc83xx/fdt.c
View File

@ -121,7 +121,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
"clock-frequency", get_serial_clock(), 1);
#endif
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size);
#if defined(CONFIG_BOOTCOUNT_LIMIT) && \
(defined(CONFIG_QE) && !defined(CONFIG_ARCH_MPC831X))

2
arch/powerpc/cpu/mpc83xx/traps.c
View File

@ -23,7 +23,7 @@ DECLARE_GLOBAL_DATA_PTR;
/* Returns 0 if exception not found and fixup otherwise. */
extern unsigned long search_exception_table(unsigned long);
#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize)
#define END_OF_MEM (gd->ram_base + gd->ram_size)
/*
* Trap & Exception support

4
arch/powerpc/cpu/mpc85xx/fdt.c
View File

@ -672,10 +672,10 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
"clock-frequency", get_bus_freq(0), 1);
#endif
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size);
#ifdef CONFIG_MP
ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
ft_fixup_cpu(blob, (u64)gd->ram_base + (u64)gd->ram_size);
ft_fixup_num_cores(blob);
#endif

2
arch/powerpc/cpu/mpc85xx/traps.c
View File

@ -37,7 +37,7 @@ extern unsigned long search_exception_table(unsigned long);
* amount of memory on the system if we're unable to keep all
* the memory mapped in.
*/
#define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize())
#define END_OF_MEM (gd->ram_base + get_effective_memsize())
static __inline__ void set_tsr(unsigned long val)
{

4
arch/powerpc/cpu/mpc86xx/fdt.c
View File

@ -8,6 +8,8 @@
#include <fdt_support.h>
#include <asm/mp.h>
DECLARE_GLOBAL_DATA_PTR;
extern void ft_fixup_num_cores(void *blob);
extern void ft_srio_setup(void *blob);
@ -27,7 +29,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
"bus-frequency", bd->bi_busfreq, 1);
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size);
#ifdef CONFIG_SYS_NS16550
do_fixup_by_compat_u32(blob, "ns16550",

2
arch/powerpc/cpu/mpc86xx/traps.c
View File

@ -30,7 +30,7 @@ extern unsigned long search_exception_table(unsigned long);
* amount of memory on the system if we're unable to keep all
* the memory mapped in.
*/
#define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize())
#define END_OF_MEM (gd->ram_base + get_effective_memsize())
/*
* Trap & Exception support

2
arch/powerpc/cpu/mpc8xx/fdt.c
View File

@ -25,5 +25,5 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency",
gd->arch.brg_clk, 1);
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size);
}

4
arch/powerpc/lib/bootm.c
View File

@ -298,8 +298,8 @@ void boot_prep_vxworks(bootm_headers_t *images)
if (!images->ft_addr)
return;
base = (u64)gd->bd->bi_memstart;
size = (u64)gd->bd->bi_memsize;
base = (u64)gd->ram_base;
size = (u64)gd->ram_size;
off = fdt_path_offset(images->ft_addr, "/memory");
if (off < 0)

2
arch/x86/cpu/broadwell/cpu_from_spl.c
View File

@ -53,14 +53,12 @@ void board_debug_uart_init(void)
int dram_init_banksize(void)
{
#ifdef CONFIG_NR_DRAM_BANKS
struct spl_handoff *ho;
ho = bloblist_find(BLOBLISTT_SPL_HANDOFF, sizeof(*ho));
if (!ho)
return log_msg_ret("Missing SPL hand-off info", -ENOENT);
handoff_load_dram_banks(ho);
#endif
return 0;
}

2
arch/xtensa/lib/Makefile
View File

@ -5,4 +5,4 @@
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-y += cache.o misc.o relocate.o time.o bdinfo.o
obj-y += cache.o misc.o relocate.o time.o

22
arch/xtensa/lib/bdinfo.c
View File

@ -1,22 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* XTENSA-specific information for the 'bd' command
*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
#include <common.h>
#include <init.h>
DECLARE_GLOBAL_DATA_PTR;
int arch_setup_bdinfo(void)
{
struct bd_info *bd = gd->bd;
bd->bi_memstart = PHYSADDR(CONFIG_SYS_SDRAM_BASE);
bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
return 0;
}

5
arch/xtensa/lib/bootm.c
View File

@ -41,15 +41,14 @@ static struct bp_tag *setup_last_tag(struct bp_tag *params)
static struct bp_tag *setup_memory_tag(struct bp_tag *params)
{
struct bd_info *bd = gd->bd;
struct meminfo *mem;
params->id = BP_TAG_MEMORY;
params->size = sizeof(struct meminfo);
mem = (struct meminfo *)params->data;
mem->type = MEMORY_TYPE_CONVENTIONAL;
mem->start = bd->bi_memstart;
mem->end = bd->bi_memstart + bd->bi_memsize;
mem->start = PHYSADDR(gd->ram_base);
mem->end = PHYSADDR(gd->ram_base + gd->ram_size);
printf(" MEMORY: tag:0x%04x, type:0X%lx, start:0X%lx, end:0X%lx\n",
BP_TAG_MEMORY, mem->type, mem->start, mem->end);

2
board/Arcturus/ucp1020/spl.c
View File

@ -83,8 +83,6 @@ void board_init_r(gd_t *gd, ulong dest_addr)
bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
memset(bd, 0, sizeof(struct bd_info));
gd->bd = bd;
bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
bd->bi_memsize = CONFIG_SYS_L2_SIZE;
arch_cpu_init();
get_clocks();

5
board/cadence/xtfpga/xtfpga.c
View File

@ -49,11 +49,6 @@ int checkboard(void)
return 0;
}
int dram_init_banksize(void)
{
return 0;
}
int board_postclk_init(void)
{
/*

2
board/freescale/p1010rdb/spl.c
View File

@ -69,8 +69,6 @@ void board_init_r(gd_t *gd, ulong dest_addr)
bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
memset(bd, 0, sizeof(struct bd_info));
gd->bd = bd;
bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
bd->bi_memsize = CONFIG_SYS_L2_SIZE;
arch_cpu_init();
get_clocks();

2
board/freescale/p1_p2_rdb_pc/spl.c
View File

@ -75,8 +75,6 @@ void board_init_r(gd_t *gd, ulong dest_addr)
bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
memset(bd, 0, sizeof(struct bd_info));
gd->bd = bd;
bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
bd->bi_memsize = CONFIG_SYS_L2_SIZE;
arch_cpu_init();
get_clocks();

2
board/freescale/t102xrdb/spl.c
View File

@ -103,8 +103,6 @@ void board_init_r(gd_t *gd, ulong dest_addr)
bd = (struct bd_info *)(gd + sizeof(gd_t));
memset(bd, 0, sizeof(struct bd_info));
gd->bd = bd;
bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
bd->bi_memsize = CONFIG_SYS_L3_SIZE;
arch_cpu_init();
get_clocks();

2
board/freescale/t104xrdb/spl.c
View File

@ -94,8 +94,6 @@ void board_init_r(gd_t *gd, ulong dest_addr)
bd = (struct bd_info *)(gd + sizeof(gd_t));
memset(bd, 0, sizeof(struct bd_info));
gd->bd = bd;
bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
bd->bi_memsize = CONFIG_SYS_L3_SIZE;
arch_cpu_init();
get_clocks();

2
board/freescale/t208xqds/spl.c
View File

@ -102,8 +102,6 @@ void board_init_r(gd_t *gd, ulong dest_addr)
bd = (struct bd_info *)(gd + sizeof(gd_t));
memset(bd, 0, sizeof(struct bd_info));
gd->bd = bd;
bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
bd->bi_memsize = CONFIG_SYS_L3_SIZE;
arch_cpu_init();
get_clocks();

2
board/freescale/t208xrdb/spl.c
View File

@ -72,8 +72,6 @@ void board_init_r(gd_t *gd, ulong dest_addr)
bd = (struct bd_info *)(gd + sizeof(gd_t));
memset(bd, 0, sizeof(struct bd_info));
gd->bd = bd;
bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
bd->bi_memsize = CONFIG_SYS_L3_SIZE;
arch_cpu_init();
get_clocks();

2
board/freescale/t4rdb/spl.c
View File

@ -75,8 +75,6 @@ void board_init_r(gd_t *gd, ulong dest_addr)
bd = (struct bd_info *)(gd + sizeof(gd_t));
memset(bd, 0, sizeof(struct bd_info));
gd->bd = bd;
bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
bd->bi_memsize = CONFIG_SYS_L3_SIZE;
arch_cpu_init();
get_clocks();

2
board/xilinx/zynqmp/zynqmp.c
View File

@ -423,10 +423,8 @@ int dram_init(void)
#else
int dram_init_banksize(void)
{
#if defined(CONFIG_NR_DRAM_BANKS)
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = get_effective_memsize();
#endif
mem_map_fill();

10
cmd/bdinfo.c
View File

@ -34,12 +34,6 @@ static void print_eth(int idx)
printf("%-12s= %s\n", name, val);
}
static void print_phys_addr(const char *name, phys_addr_t value)
{
printf("%-12s= 0x%.*llx\n", name, 2 * (int)sizeof(ulong),
(unsigned long long)value);
}
void bdinfo_print_mhz(const char *name, unsigned long hz)
{
char buf[32];
@ -49,7 +43,6 @@ void bdinfo_print_mhz(const char *name, unsigned long hz)
static void print_bi_dram(const struct bd_info *bd)
{
#ifdef CONFIG_NR_DRAM_BANKS
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
@ -59,7 +52,6 @@ static void print_bi_dram(const struct bd_info *bd)
bdinfo_print_num("-> size", bd->bi_dram[i].size);
}
}
#endif
}
__weak void arch_print_bdinfo(void)
@ -75,8 +67,6 @@ int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
#endif
bdinfo_print_num("boot_params", (ulong)bd->bi_boot_params);
print_bi_dram(bd);
bdinfo_print_num("memstart", (ulong)bd->bi_memstart);
print_phys_addr("memsize", bd->bi_memsize);
if (IS_ENABLED(CONFIG_SYS_HAS_SRAM)) {
bdinfo_print_num("sramstart", (ulong)bd->bi_sramstart);
bdinfo_print_num("sramsize", (ulong)bd->bi_sramsize);

2
cmd/bedbug.c
View File

@ -348,7 +348,7 @@ int do_bedbug_stack(struct cmd_tbl *cmdtp, int flag, int argc,
return 1;
}
top = gd->bd->bi_memstart + gd->bd->bi_memsize;
top = gd->ram_start + gd->ram_size;
depth = 0;
printf ("Depth PC\n");

12
common/board_f.c
View File

@ -215,8 +215,6 @@ static int announce_dram_init(void)
static int show_dram_config(void)
{
unsigned long long size;
#ifdef CONFIG_NR_DRAM_BANKS
int i;
debug("\nRAM Configuration:\n");
@ -229,9 +227,6 @@ static int show_dram_config(void)
#endif
}
debug("\nDRAM: ");
#else
size = gd->ram_size;
#endif
print_size(size, "");
board_add_ram_info(0);
@ -242,10 +237,8 @@ static int show_dram_config(void)
__weak int dram_init_banksize(void)
{
#if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].start = gd->ram_base;
gd->bd->bi_dram[0].size = get_effective_memsize();
#endif
return 0;
}
@ -603,9 +596,6 @@ int setup_bdinfo(void)
{
struct bd_info *bd = gd->bd;
bd->bi_memstart = gd->ram_base; /* start of memory */
bd->bi_memsize = gd->ram_size; /* size in bytes */
if (IS_ENABLED(CONFIG_SYS_HAS_SRAM)) {
bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */

10
common/image.c
View File

@ -685,14 +685,8 @@ phys_size_t env_get_bootm_size(void)
return tmp;
}
#if (defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE)) && \
defined(CONFIG_NR_DRAM_BANKS)
start = gd->bd->bi_dram[0].start;
size = gd->bd->bi_dram[0].size;
#else
start = gd->bd->bi_memstart;
size = gd->bd->bi_memsize;
#endif
start = gd->ram_base;
size = gd->ram_size;
if (start + size > gd->ram_top)
size = gd->ram_top - start;

31
common/init/handoff.c
View File

@ -12,18 +12,15 @@ DECLARE_GLOBAL_DATA_PTR;
void handoff_save_dram(struct spl_handoff *ho)
{
ho->ram_size = gd->ram_size;
#ifdef CONFIG_NR_DRAM_BANKS
{
struct bd_info *bd = gd->bd;
int i;
struct bd_info *bd = gd->bd;
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
ho->ram_bank[i].start = bd->bi_dram[i].start;
ho->ram_bank[i].size = bd->bi_dram[i].size;
}
ho->ram_size = gd->ram_size;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
ho->ram_bank[i].start = bd->bi_dram[i].start;
ho->ram_bank[i].size = bd->bi_dram[i].size;
}
#endif
}
void handoff_load_dram_size(struct spl_handoff *ho)
@ -33,15 +30,11 @@ void handoff_load_dram_size(struct spl_handoff *ho)
void handoff_load_dram_banks(struct spl_handoff *ho)
{
#ifdef CONFIG_NR_DRAM_BANKS
{
struct bd_info *bd = gd->bd;
int i;
struct bd_info *bd = gd->bd;
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
bd->bi_dram[i].start = ho->ram_bank[i].start;
bd->bi_dram[i].size = ho->ram_bank[i].size;
}
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
bd->bi_dram[i].start = ho->ram_bank[i].start;
bd->bi_dram[i].size = ho->ram_bank[i].size;
}
#endif
}

3
drivers/pci/pci-uclass.c
View File

@ -911,8 +911,8 @@ static void decode_regions(struct pci_controller *hose, ofnode parent_node,
ofnode node)
{
int pci_addr_cells, addr_cells, size_cells;
struct bd_info *bd = gd->bd;
int cells_per_record;
struct bd_info *bd;
const u32 *prop;
int max_regions;
int len;
@ -989,6 +989,7 @@ static void decode_regions(struct pci_controller *hose, ofnode parent_node,
}
/* Add a region for our local memory */
bd = gd->bd;
if (!bd)
return;

8
drivers/video/cfb_console.c
View File

@ -1983,8 +1983,6 @@ static void *video_logo(void)
static int cfb_fb_is_in_dram(void)
{
struct bd_info *bd = gd->bd;
#if defined(CONFIG_ARM) || defined(CONFIG_NDS32) || \
defined(CONFIG_SANDBOX) || defined(CONFIG_X86)
ulong start, end;
int i;
@ -1995,11 +1993,7 @@ defined(CONFIG_SANDBOX) || defined(CONFIG_X86)
(ulong)video_fb_address < end)
return 1;
}
#else
if ((ulong)video_fb_address >= bd->bi_memstart &&
(ulong)video_fb_address < bd->bi_memstart + bd->bi_memsize)
return 1;
#endif
return 0;
}

4
include/asm-generic/u-boot.h
View File

@ -27,8 +27,6 @@
#include <linux/types.h>
struct bd_info {
unsigned long bi_memstart; /* start of DRAM memory */
phys_size_t bi_memsize; /* size of DRAM memory in bytes */
unsigned long bi_flashstart; /* start of FLASH memory */
unsigned long bi_flashsize; /* size of FLASH memory */
unsigned long bi_flashoffset; /* reserved area for startup monitor */
@ -70,12 +68,10 @@ struct bd_info {
#endif
ulong bi_arch_number; /* unique id for this board */
ulong bi_boot_params; /* where this board expects params */
#ifdef CONFIG_NR_DRAM_BANKS
struct { /* RAM configuration */
phys_addr_t start;
phys_size_t size;
} bi_dram[CONFIG_NR_DRAM_BANKS];
#endif /* CONFIG_NR_DRAM_BANKS */
};
#endif /* __ASSEMBLY__ */

2
include/handoff.h
View File

@ -20,12 +20,10 @@
struct spl_handoff {
struct arch_spl_handoff arch;
u64 ram_size;
#ifdef CONFIG_NR_DRAM_BANKS
struct {
u64 start;
u64 size;
} ram_bank[CONFIG_NR_DRAM_BANKS];
#endif
};
void handoff_save_dram(struct spl_handoff *ho);

5
lib/fdtdec.c
View File

@ -1073,8 +1073,6 @@ int fdtdec_setup_mem_size_base(void)
return 0;
}
#if defined(CONFIG_NR_DRAM_BANKS)
ofnode get_next_memory_node(ofnode mem)
{
do {
@ -1170,7 +1168,6 @@ int fdtdec_setup_mem_size_base_lowest(void)
return 0;
}
#endif
#if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
# if CONFIG_IS_ENABLED(MULTI_DTB_FIT_GZIP) ||\
@ -1633,7 +1630,6 @@ int fdtdec_resetup(int *rescan)
}
#endif
#ifdef CONFIG_NR_DRAM_BANKS
int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id,
phys_addr_t *basep, phys_size_t *sizep,
struct bd_info *bd)
@ -1739,6 +1735,5 @@ int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id,
return 0;
}
#endif /* CONFIG_NR_DRAM_BANKS */
#endif /* !USE_HOSTCC */

9
lib/lmb.c
View File

@ -117,22 +117,17 @@ static void lmb_reserve_common(struct lmb *lmb, void *fdt_blob)
/* Initialize the struct, add memory and call arch/board reserve functions */
void lmb_init_and_reserve(struct lmb *lmb, struct bd_info *bd, void *fdt_blob)
{
#ifdef CONFIG_NR_DRAM_BANKS
int i;
#endif
lmb_init(lmb);
#ifdef CONFIG_NR_DRAM_BANKS
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
if (bd->bi_dram[i].size) {
lmb_add(lmb, bd->bi_dram[i].start,
bd->bi_dram[i].size);
}
}
#else
if (bd->bi_memsize)
lmb_add(lmb, bd->bi_memstart, bd->bi_memsize);
#endif
lmb_reserve_common(lmb, fdt_blob);
}