mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
- add support for PCI and XHCI for RPi4 (64 bit only)
- optionally reset XHCI device on registration - enable USB_KEYBOARD for rpi_4_defconfig -----BEGIN PGP SIGNATURE----- iQJGBAABCAAwFiEEUdvKHhzqrUYPB/u8L21+TfbCqH4FAl8Ifk0SHG1icnVnZ2Vy QHN1c2UuY29tAAoJEC9tfk32wqh+160QAK85hENUpOft76dZ+SwKp1EF4K6yn7Uq 7OuO3k9PlzYamWDrJuRlvUp2ZkQPU0umT7NA+DfIOCrcXpdU/nltlhZMlaSXIXIp NbsoSLZxGz1xKdKITZJupCMTj+rHP4/ZO96EQ9ajuNQ56TLmxSbbU6rpJtwm98Gx mXOUTSx3UOHRyRv7R1U/LGNfxHnXwK8tpP+sCppHGRkl2ypkKSM9mjPRmBfPLGgM s0TDm2XcPtiTK/YOR5FpuXsjlg+eUxhpSkH9Tvj49BkGPgIUeGYgWkc/1d6Aip1E liuQYvRtK/cZLhtaWPyW8JPentyv54rIbFQ7weZbsTMDGUfX4k5VJC+ucsWiG3aa XaWO83woOG+nYIv6hNodXT9i5TmfOJYHHC64nqMMGx0n5Ouz3oQ2UhXVLMFihyG0 xgOprEVqMBvgxdOGVyEyFO3qtut2zPQTkFTZZoUNrEYcGO3rtrhAMI2KY4TVMfQe CyZ4DMMMAC3aSvL2VD5s3YkD//j8sXdt75qnSeS3AVbEKJgmcWP6A59FFDZ6cCmY Nturw8Cfn8axvQAkR9v7yhX2HeItO6n5YWhayoxa+Bo5mjjEZEMT5mrZhKAWposl XBZgb4Xr6fp1N2AZf7/b60jxwD0ogTIjxX4Ez2d43ehhHqPNZ5sGrC6kIrpu0U9U NKcCxgGjlQBA =2aS6 -----END PGP SIGNATURE----- Merge tag 'rpi-next-2020.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-raspberrypi - add support for PCI and XHCI for RPi4 (64 bit only) - optionally reset XHCI device on registration - enable USB_KEYBOARD for rpi_4_defconfig
This commit is contained in:
Tom Rini
commit
3113c84ba2
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@ -491,6 +491,19 @@ struct bcm2835_mbox_tag_set_palette {
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} body;
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};
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#define BCM2835_MBOX_TAG_NOTIFY_XHCI_RESET 0x00030058
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struct bcm2835_mbox_tag_pci_dev_addr {
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struct bcm2835_mbox_tag_hdr tag_hdr;
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union {
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struct {
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u32 dev_addr;
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} req;
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struct {
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} resp;
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} body;
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};
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/*
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* Pass a raw u32 message to the VC, and receive a raw u32 back.
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*
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|
|
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@ -48,4 +48,11 @@ int bcm2835_set_video_params(int *widthp, int *heightp, int depth_bpp,
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int pixel_order, int alpha_mode, ulong *fb_basep,
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ulong *fb_sizep, int *pitchp);
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/**
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* bcm2711_load_vl805_firmware() - get vl805's firmware loaded
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*
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* @return 0 if OK, -EIO on error
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*/
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int bcm2711_notify_vl805_reset(void);
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#endif
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@ -12,10 +12,15 @@
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#include <dm/device.h>
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#include <fdt_support.h>
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#define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS 0x600000000UL
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#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE 0x800000UL
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#ifdef CONFIG_ARM64
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#include <asm/armv8/mmu.h>
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static struct mm_region bcm283x_mem_map[] = {
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#define MEM_MAP_MAX_ENTRIES (4)
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static struct mm_region bcm283x_mem_map[MEM_MAP_MAX_ENTRIES] = {
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{
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.virt = 0x00000000UL,
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.phys = 0x00000000UL,
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@ -35,11 +40,11 @@ static struct mm_region bcm283x_mem_map[] = {
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}
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};
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static struct mm_region bcm2711_mem_map[] = {
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static struct mm_region bcm2711_mem_map[MEM_MAP_MAX_ENTRIES] = {
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{
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.virt = 0x00000000UL,
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.phys = 0x00000000UL,
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.size = 0xfe000000UL,
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.size = 0xfc000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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@ -49,6 +54,13 @@ static struct mm_region bcm2711_mem_map[] = {
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.virt = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
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.phys = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
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.size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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@ -72,7 +84,7 @@ static void _rpi_update_mem_map(struct mm_region *pd)
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{
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int i;
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for (i = 0; i < 2; i++) {
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for (i = 0; i < MEM_MAP_MAX_ENTRIES; i++) {
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mem_map[i].virt = pd[i].virt;
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mem_map[i].phys = pd[i].phys;
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mem_map[i].size = pd[i].size;
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@ -7,6 +7,7 @@
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#include <memalign.h>
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#include <phys2bus.h>
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#include <asm/arch/mbox.h>
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#include <linux/delay.h>
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struct msg_set_power_state {
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struct bcm2835_mbox_hdr hdr;
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@ -40,6 +41,12 @@ struct msg_setup {
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u32 end_tag;
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};
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struct msg_notify_vl805_reset {
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struct bcm2835_mbox_hdr hdr;
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struct bcm2835_mbox_tag_pci_dev_addr dev_addr;
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u32 end_tag;
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};
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int bcm2835_power_on_module(u32 module)
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{
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ALLOC_CACHE_ALIGN_BUFFER(struct msg_set_power_state, msg_pwr, 1);
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@ -151,3 +158,42 @@ int bcm2835_set_video_params(int *widthp, int *heightp, int depth_bpp,
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return 0;
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}
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/*
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* On the Raspberry Pi 4, after a PCI reset, VL805's (the xHCI chip) firmware
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* may either be loaded directly from an EEPROM or, if not present, by the
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* SoC's VideoCore. This informs VideoCore that VL805 needs its firmware
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* loaded.
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*/
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int bcm2711_notify_vl805_reset(void)
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{
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ALLOC_CACHE_ALIGN_BUFFER(struct msg_notify_vl805_reset,
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msg_notify_vl805_reset, 1);
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int ret;
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BCM2835_MBOX_INIT_HDR(msg_notify_vl805_reset);
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BCM2835_MBOX_INIT_TAG(&msg_notify_vl805_reset->dev_addr,
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NOTIFY_XHCI_RESET);
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/*
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* The pci device address is expected like this:
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*
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* PCI_BUS << 20 | PCI_SLOT << 15 | PCI_FUNC << 12
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*
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* But since RPi4's PCIe setup is hardwired, we know the address in
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* advance.
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*/
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msg_notify_vl805_reset->dev_addr.body.req.dev_addr = 0x100000;
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ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN,
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&msg_notify_vl805_reset->hdr);
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if (ret) {
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printf("bcm2711: Faild to load vl805's firmware, %d\n", ret);
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return -EIO;
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}
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udelay(200);
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return 0;
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}
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@ -35,6 +35,7 @@ CONFIG_DM_PCI=y
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CONFIG_PCI_BRCMSTB=y
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CONFIG_PINCTRL=y
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# CONFIG_PINCTRL_GENERIC is not set
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CONFIG_DM_RESET=y
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# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
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CONFIG_USB=y
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CONFIG_DM_USB=y
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@ -6,6 +6,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
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CONFIG_ENV_SIZE=0x4000
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_USE_PREBOOT=y
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CONFIG_PREBOOT="pci enum; usb start;"
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CONFIG_MISC_INIT_R=y
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# CONFIG_DISPLAY_CPUINFO is not set
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# CONFIG_DISPLAY_BOARDINFO is not set
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@ -13,6 +15,8 @@ CONFIG_SYS_PROMPT="U-Boot> "
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CONFIG_CMD_DFU=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_PCI=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_FS_UUID=y
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CONFIG_OF_BOARD=y
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CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
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@ -26,12 +30,19 @@ CONFIG_MMC_SDHCI_SDMA=y
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CONFIG_MMC_SDHCI_BCM2835=y
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CONFIG_DM_ETH=y
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CONFIG_BCMGENET=y
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CONFIG_PCI=y
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CONFIG_DM_PCI=y
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CONFIG_PCI_BRCMSTB=y
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CONFIG_PINCTRL=y
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# CONFIG_PINCTRL_GENERIC is not set
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CONFIG_DM_RESET=y
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# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
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CONFIG_USB=y
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CONFIG_DM_USB=y
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CONFIG_DM_USB_GADGET=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_XHCI_PCI=y
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CONFIG_USB_KEYBOARD=y
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CONFIG_USB_GADGET=y
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CONFIG_USB_GADGET_MANUFACTURER="FSL"
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CONFIG_USB_GADGET_VENDOR_NUM=0x0525
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@ -7,13 +7,14 @@ CONFIG_ENV_SIZE=0x4000
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_USE_PREBOOT=y
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CONFIG_PREBOOT="usb start"
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CONFIG_PREBOOT="pci enum; usb start;"
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CONFIG_MISC_INIT_R=y
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# CONFIG_DISPLAY_CPUINFO is not set
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# CONFIG_DISPLAY_BOARDINFO is not set
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CONFIG_SYS_PROMPT="U-Boot> "
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_PCI=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_FS_UUID=y
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CONFIG_OF_BOARD=y
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@ -26,11 +27,17 @@ CONFIG_MMC_SDHCI_SDMA=y
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CONFIG_MMC_SDHCI_BCM2835=y
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CONFIG_DM_ETH=y
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CONFIG_BCMGENET=y
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CONFIG_PCI=y
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CONFIG_DM_PCI=y
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CONFIG_PCI_BRCMSTB=y
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CONFIG_PINCTRL=y
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# CONFIG_PINCTRL_GENERIC is not set
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CONFIG_DM_RESET=y
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# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
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CONFIG_USB=y
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CONFIG_DM_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_XHCI_PCI=y
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CONFIG_USB_DWC2=y
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CONFIG_USB_KEYBOARD=y
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CONFIG_USB_HOST_ETHER=y
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@ -205,4 +205,13 @@ config PCIE_ROCKCHIP
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Say Y here if you want to enable PCIe controller support on
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Rockchip SoCs.
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config PCI_BRCMSTB
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bool "Broadcom STB PCIe controller"
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depends on DM_PCI
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depends on ARCH_BCM283X
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help
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Say Y here if you want to enable support for PCIe controller
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on Broadcom set-top-box (STB) SoCs.
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This driver currently supports only BCM2711 SoC and RC mode
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of the controller.
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endif
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@ -44,3 +44,4 @@ obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
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obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o
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obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o
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obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o pcie_rockchip_phy.o
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obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o
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@ -118,14 +118,6 @@
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#define RCAR_PCI_MAX_RESOURCES 4
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#define MAX_NR_INBOUND_MAPS 6
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#define PCI_EXP_FLAGS 2 /* Capabilities register */
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#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
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#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
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#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
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#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */
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#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
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#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
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enum {
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RCAR_PCI_ACCESS_READ,
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RCAR_PCI_ACCESS_WRITE,
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|
|
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623
drivers/pci/pcie_brcmstb.c
Normal file
623
drivers/pci/pcie_brcmstb.c
Normal file
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@ -0,0 +1,623 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Broadcom STB PCIe controller driver
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*
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* Copyright (C) 2020 Samsung Electronics Co., Ltd.
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*
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* Based on upstream Linux kernel driver:
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* drivers/pci/controller/pcie-brcmstb.c
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* Copyright (C) 2009 - 2017 Broadcom
|
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*
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* Based driver by Nicolas Saenz Julienne
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* Copyright (C) 2020 Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
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*/
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#include <common.h>
|
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#include <errno.h>
|
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#include <dm.h>
|
||||
#include <dm/ofnode.h>
|
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#include <pci.h>
|
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#include <asm/io.h>
|
||||
#include <linux/bitfield.h>
|
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#include <linux/log2.h>
|
||||
#include <linux/iopoll.h>
|
||||
|
||||
/* Offset of the mandatory PCIe capability config registers */
|
||||
#define BRCM_PCIE_CAP_REGS 0x00ac
|
||||
|
||||
/* The PCIe controller register offsets */
|
||||
#define PCIE_RC_CFG_VENDOR_SPECIFIC_REG1 0x0188
|
||||
#define VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
|
||||
#define VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN 0x0
|
||||
|
||||
#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
|
||||
#define CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
|
||||
|
||||
#define PCIE_RC_DL_MDIO_ADDR 0x1100
|
||||
#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
|
||||
#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
|
||||
|
||||
#define PCIE_MISC_MISC_CTRL 0x4008
|
||||
#define MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
|
||||
#define MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
|
||||
#define MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
|
||||
#define MISC_CTRL_MAX_BURST_SIZE_128 0x0
|
||||
#define MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
|
||||
|
||||
#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
|
||||
#define PCIE_MEM_WIN0_LO(win) \
|
||||
PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4)
|
||||
|
||||
#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
|
||||
#define PCIE_MEM_WIN0_HI(win) \
|
||||
PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4)
|
||||
|
||||
#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
|
||||
#define RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
|
||||
|
||||
#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
|
||||
#define RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
|
||||
#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
|
||||
|
||||
#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
|
||||
#define RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
|
||||
|
||||
#define PCIE_MISC_PCIE_STATUS 0x4068
|
||||
#define STATUS_PCIE_PORT_MASK 0x80
|
||||
#define STATUS_PCIE_PORT_SHIFT 7
|
||||
#define STATUS_PCIE_DL_ACTIVE_MASK 0x20
|
||||
#define STATUS_PCIE_DL_ACTIVE_SHIFT 5
|
||||
#define STATUS_PCIE_PHYLINKUP_MASK 0x10
|
||||
#define STATUS_PCIE_PHYLINKUP_SHIFT 4
|
||||
|
||||
#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
|
||||
#define MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
|
||||
#define MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
|
||||
#define MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT 12
|
||||
#define PCIE_MEM_WIN0_BASE_LIMIT(win) \
|
||||
PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4)
|
||||
|
||||
#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
|
||||
#define MEM_WIN0_BASE_HI_BASE_MASK 0xff
|
||||
#define PCIE_MEM_WIN0_BASE_HI(win) \
|
||||
PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8)
|
||||
|
||||
#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
|
||||
#define PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
|
||||
#define PCIE_MEM_WIN0_LIMIT_HI(win) \
|
||||
PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)
|
||||
|
||||
#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
|
||||
#define PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
|
||||
#define PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
|
||||
|
||||
#define PCIE_MSI_INTR2_CLR 0x4508
|
||||
#define PCIE_MSI_INTR2_MASK_SET 0x4510
|
||||
|
||||
#define PCIE_EXT_CFG_DATA 0x8000
|
||||
|
||||
#define PCIE_EXT_CFG_INDEX 0x9000
|
||||
#define PCIE_EXT_BUSNUM_SHIFT 20
|
||||
#define PCIE_EXT_SLOT_SHIFT 15
|
||||
#define PCIE_EXT_FUNC_SHIFT 12
|
||||
|
||||
#define PCIE_RGR1_SW_INIT_1 0x9210
|
||||
#define RGR1_SW_INIT_1_PERST_MASK 0x1
|
||||
#define RGR1_SW_INIT_1_INIT_MASK 0x2
|
||||
|
||||
/* PCIe parameters */
|
||||
#define BRCM_NUM_PCIE_OUT_WINS 4
|
||||
|
||||
/* MDIO registers */
|
||||
#define MDIO_PORT0 0x0
|
||||
#define MDIO_DATA_MASK 0x7fffffff
|
||||
#define MDIO_DATA_SHIFT 0
|
||||
#define MDIO_PORT_MASK 0xf0000
|
||||
#define MDIO_PORT_SHIFT 16
|
||||
#define MDIO_REGAD_MASK 0xffff
|
||||
#define MDIO_REGAD_SHIFT 0
|
||||
#define MDIO_CMD_MASK 0xfff00000
|
||||
#define MDIO_CMD_SHIFT 20
|
||||
#define MDIO_CMD_READ 0x1
|
||||
#define MDIO_CMD_WRITE 0x0
|
||||
#define MDIO_DATA_DONE_MASK 0x80000000
|
||||
#define SSC_REGS_ADDR 0x1100
|
||||
#define SET_ADDR_OFFSET 0x1f
|
||||
#define SSC_CNTL_OFFSET 0x2
|
||||
#define SSC_CNTL_OVRD_EN_MASK 0x8000
|
||||
#define SSC_CNTL_OVRD_VAL_MASK 0x4000
|
||||
#define SSC_STATUS_OFFSET 0x1
|
||||
#define SSC_STATUS_SSC_MASK 0x400
|
||||
#define SSC_STATUS_SSC_SHIFT 10
|
||||
#define SSC_STATUS_PLL_LOCK_MASK 0x800
|
||||
#define SSC_STATUS_PLL_LOCK_SHIFT 11
|
||||
|
||||
/**
|
||||
* struct brcm_pcie - the PCIe controller state
|
||||
* @base: Base address of memory mapped IO registers of the controller
|
||||
* @gen: Non-zero value indicates limitation of the PCIe controller operation
|
||||
* to a specific generation (1, 2 or 3)
|
||||
* @ssc: true indicates active Spread Spectrum Clocking operation
|
||||
*/
|
||||
struct brcm_pcie {
|
||||
void __iomem *base;
|
||||
|
||||
int gen;
|
||||
bool ssc;
|
||||
};
|
||||
|
||||
/**
|
||||
* brcm_pcie_encode_ibar_size() - Encode the inbound "BAR" region size
|
||||
* @size: The inbound region size
|
||||
*
|
||||
* This function converts size of the inbound "BAR" region to the non-linear
|
||||
* values of the PCIE_MISC_RC_BAR[123]_CONFIG_LO register SIZE field.
|
||||
*
|
||||
* Return: The encoded inbound region size
|
||||
*/
|
||||
static int brcm_pcie_encode_ibar_size(u64 size)
|
||||
{
|
||||
int log2_in = ilog2(size);
|
||||
|
||||
if (log2_in >= 12 && log2_in <= 15)
|
||||
/* Covers 4KB to 32KB (inclusive) */
|
||||
return (log2_in - 12) + 0x1c;
|
||||
else if (log2_in >= 16 && log2_in <= 37)
|
||||
/* Covers 64KB to 32GB, (inclusive) */
|
||||
return log2_in - 15;
|
||||
|
||||
/* Something is awry so disable */
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* brcm_pcie_rc_mode() - Check if PCIe controller is in RC mode
|
||||
* @pcie: Pointer to the PCIe controller state
|
||||
*
|
||||
* The controller is capable of serving in both RC and EP roles.
|
||||
*
|
||||
* Return: true for RC mode, false for EP mode.
|
||||
*/
|
||||
static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = readl(pcie->base + PCIE_MISC_PCIE_STATUS);
|
||||
|
||||
return (val & STATUS_PCIE_PORT_MASK) >> STATUS_PCIE_PORT_SHIFT;
|
||||
}
|
||||
|
||||
/**
|
||||
* brcm_pcie_link_up() - Check whether the PCIe link is up
|
||||
* @pcie: Pointer to the PCIe controller state
|
||||
*
|
||||
* Return: true if the link is up, false otherwise.
|
||||
*/
|
||||
static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
|
||||
{
|
||||
u32 val, dla, plu;
|
||||
|
||||
val = readl(pcie->base + PCIE_MISC_PCIE_STATUS);
|
||||
dla = (val & STATUS_PCIE_DL_ACTIVE_MASK) >> STATUS_PCIE_DL_ACTIVE_SHIFT;
|
||||
plu = (val & STATUS_PCIE_PHYLINKUP_MASK) >> STATUS_PCIE_PHYLINKUP_SHIFT;
|
||||
|
||||
return dla && plu;
|
||||
}
|
||||
|
||||
static int brcm_pcie_config_address(const struct udevice *dev, pci_dev_t bdf,
|
||||
uint offset, void **paddress)
|
||||
{
|
||||
struct brcm_pcie *pcie = dev_get_priv(dev);
|
||||
unsigned int pci_bus = PCI_BUS(bdf);
|
||||
unsigned int pci_dev = PCI_DEV(bdf);
|
||||
unsigned int pci_func = PCI_FUNC(bdf);
|
||||
int idx;
|
||||
|
||||
/*
|
||||
* Busses 0 (host PCIe bridge) and 1 (its immediate child)
|
||||
* are limited to a single device each
|
||||
*/
|
||||
if (pci_bus < 2 && pci_dev > 0)
|
||||
return -EINVAL;
|
||||
|
||||
/* Accesses to the RC go right to the RC registers */
|
||||
if (pci_bus == 0) {
|
||||
*paddress = pcie->base + offset;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* For devices, write to the config space index register */
|
||||
idx = (pci_bus << PCIE_EXT_BUSNUM_SHIFT)
|
||||
| (pci_dev << PCIE_EXT_SLOT_SHIFT)
|
||||
| (pci_func << PCIE_EXT_FUNC_SHIFT);
|
||||
|
||||
writel(idx, pcie->base + PCIE_EXT_CFG_INDEX);
|
||||
*paddress = pcie->base + PCIE_EXT_CFG_DATA + offset;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int brcm_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
|
||||
uint offset, ulong *valuep,
|
||||
enum pci_size_t size)
|
||||
{
|
||||
return pci_generic_mmap_read_config(bus, brcm_pcie_config_address,
|
||||
bdf, offset, valuep, size);
|
||||
}
|
||||
|
||||
static int brcm_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
|
||||
uint offset, ulong value,
|
||||
enum pci_size_t size)
|
||||
{
|
||||
return pci_generic_mmap_write_config(bus, brcm_pcie_config_address,
|
||||
bdf, offset, value, size);
|
||||
}
|
||||
|
||||
static const char *link_speed_to_str(unsigned int cls)
|
||||
{
|
||||
switch (cls) {
|
||||
case PCI_EXP_LNKSTA_CLS_2_5GB: return "2.5";
|
||||
case PCI_EXP_LNKSTA_CLS_5_0GB: return "5.0";
|
||||
case PCI_EXP_LNKSTA_CLS_8_0GB: return "8.0";
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return "??";
|
||||
}
|
||||
|
||||
static u32 brcm_pcie_mdio_form_pkt(unsigned int port, unsigned int regad,
|
||||
unsigned int cmd)
|
||||
{
|
||||
u32 pkt;
|
||||
|
||||
pkt = (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK;
|
||||
pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK;
|
||||
pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK;
|
||||
|
||||
return pkt;
|
||||
}
|
||||
|
||||
/**
|
||||
* brcm_pcie_mdio_read() - Perform a register read on the internal MDIO bus
|
||||
* @base: Pointer to the PCIe controller IO registers
|
||||
* @port: The MDIO port number
|
||||
* @regad: The register address
|
||||
* @val: A pointer at which to store the read value
|
||||
*
|
||||
* Return: 0 on success and register value in @val, negative error value
|
||||
* on failure.
|
||||
*/
|
||||
static int brcm_pcie_mdio_read(void __iomem *base, unsigned int port,
|
||||
unsigned int regad, u32 *val)
|
||||
{
|
||||
u32 data, addr;
|
||||
int ret;
|
||||
|
||||
addr = brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_READ);
|
||||
writel(addr, base + PCIE_RC_DL_MDIO_ADDR);
|
||||
readl(base + PCIE_RC_DL_MDIO_ADDR);
|
||||
|
||||
ret = readl_poll_timeout(base + PCIE_RC_DL_MDIO_RD_DATA, data,
|
||||
(data & MDIO_DATA_DONE_MASK), 100);
|
||||
|
||||
*val = data & MDIO_DATA_MASK;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* brcm_pcie_mdio_write() - Perform a register write on the internal MDIO bus
|
||||
* @base: Pointer to the PCIe controller IO registers
|
||||
* @port: The MDIO port number
|
||||
* @regad: Address of the register
|
||||
* @wrdata: The value to write
|
||||
*
|
||||
* Return: 0 on success, negative error value on failure.
|
||||
*/
|
||||
static int brcm_pcie_mdio_write(void __iomem *base, unsigned int port,
|
||||
unsigned int regad, u16 wrdata)
|
||||
{
|
||||
u32 data, addr;
|
||||
|
||||
addr = brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_WRITE);
|
||||
writel(addr, base + PCIE_RC_DL_MDIO_ADDR);
|
||||
readl(base + PCIE_RC_DL_MDIO_ADDR);
|
||||
writel(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA);
|
||||
|
||||
return readl_poll_timeout(base + PCIE_RC_DL_MDIO_WR_DATA, data,
|
||||
!(data & MDIO_DATA_DONE_MASK), 100);
|
||||
}
|
||||
|
||||
/**
|
||||
* brcm_pcie_set_ssc() - Configure the controller for Spread Spectrum Clocking
|
||||
* @base: pointer to the PCIe controller IO registers
|
||||
*
|
||||
* Return: 0 on success, negative error value on failure.
|
||||
*/
|
||||
static int brcm_pcie_set_ssc(void __iomem *base)
|
||||
{
|
||||
int pll, ssc;
|
||||
int ret;
|
||||
u32 tmp;
|
||||
|
||||
ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET,
|
||||
SSC_REGS_ADDR);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
tmp |= (SSC_CNTL_OVRD_EN_MASK | SSC_CNTL_OVRD_VAL_MASK);
|
||||
|
||||
ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
udelay(1000);
|
||||
ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ssc = (tmp & SSC_STATUS_SSC_MASK) >> SSC_STATUS_SSC_SHIFT;
|
||||
pll = (tmp & SSC_STATUS_PLL_LOCK_MASK) >> SSC_STATUS_PLL_LOCK_SHIFT;
|
||||
|
||||
return ssc && pll ? 0 : -EIO;
|
||||
}
|
||||
|
||||
/**
|
||||
* brcm_pcie_set_gen() - Limits operation to a specific generation (1, 2 or 3)
|
||||
* @pcie: pointer to the PCIe controller state
|
||||
* @gen: PCIe generation to limit the controller's operation to
|
||||
*/
|
||||
static void brcm_pcie_set_gen(struct brcm_pcie *pcie, unsigned int gen)
|
||||
{
|
||||
void __iomem *cap_base = pcie->base + BRCM_PCIE_CAP_REGS;
|
||||
|
||||
u16 lnkctl2 = readw(cap_base + PCI_EXP_LNKCTL2);
|
||||
u32 lnkcap = readl(cap_base + PCI_EXP_LNKCAP);
|
||||
|
||||
lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
|
||||
writel(lnkcap, cap_base + PCI_EXP_LNKCAP);
|
||||
|
||||
lnkctl2 = (lnkctl2 & ~0xf) | gen;
|
||||
writew(lnkctl2, cap_base + PCI_EXP_LNKCTL2);
|
||||
}
|
||||
|
||||
static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
|
||||
unsigned int win, u64 phys_addr,
|
||||
u64 pcie_addr, u64 size)
|
||||
{
|
||||
void __iomem *base = pcie->base;
|
||||
u32 phys_addr_mb_high, limit_addr_mb_high;
|
||||
phys_addr_t phys_addr_mb, limit_addr_mb;
|
||||
int high_addr_shift;
|
||||
u32 tmp;
|
||||
|
||||
/* Set the base of the pcie_addr window */
|
||||
writel(lower_32_bits(pcie_addr), base + PCIE_MEM_WIN0_LO(win));
|
||||
writel(upper_32_bits(pcie_addr), base + PCIE_MEM_WIN0_HI(win));
|
||||
|
||||
/* Write the addr base & limit lower bits (in MBs) */
|
||||
phys_addr_mb = phys_addr / SZ_1M;
|
||||
limit_addr_mb = (phys_addr + size - 1) / SZ_1M;
|
||||
|
||||
tmp = readl(base + PCIE_MEM_WIN0_BASE_LIMIT(win));
|
||||
u32p_replace_bits(&tmp, phys_addr_mb,
|
||||
MEM_WIN0_BASE_LIMIT_BASE_MASK);
|
||||
u32p_replace_bits(&tmp, limit_addr_mb,
|
||||
MEM_WIN0_BASE_LIMIT_LIMIT_MASK);
|
||||
writel(tmp, base + PCIE_MEM_WIN0_BASE_LIMIT(win));
|
||||
|
||||
/* Write the cpu & limit addr upper bits */
|
||||
high_addr_shift = MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT;
|
||||
phys_addr_mb_high = phys_addr_mb >> high_addr_shift;
|
||||
tmp = readl(base + PCIE_MEM_WIN0_BASE_HI(win));
|
||||
u32p_replace_bits(&tmp, phys_addr_mb_high,
|
||||
MEM_WIN0_BASE_HI_BASE_MASK);
|
||||
writel(tmp, base + PCIE_MEM_WIN0_BASE_HI(win));
|
||||
|
||||
limit_addr_mb_high = limit_addr_mb >> high_addr_shift;
|
||||
tmp = readl(base + PCIE_MEM_WIN0_LIMIT_HI(win));
|
||||
u32p_replace_bits(&tmp, limit_addr_mb_high,
|
||||
PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK);
|
||||
writel(tmp, base + PCIE_MEM_WIN0_LIMIT_HI(win));
|
||||
}
|
||||
|
||||
static int brcm_pcie_probe(struct udevice *dev)
|
||||
{
|
||||
struct udevice *ctlr = pci_get_controller(dev);
|
||||
struct pci_controller *hose = dev_get_uclass_priv(ctlr);
|
||||
struct brcm_pcie *pcie = dev_get_priv(dev);
|
||||
void __iomem *base = pcie->base;
|
||||
bool ssc_good = false;
|
||||
int num_out_wins = 0;
|
||||
u64 rc_bar2_offset, rc_bar2_size;
|
||||
unsigned int scb_size_val;
|
||||
int i, ret;
|
||||
u16 nlw, cls, lnksta;
|
||||
u32 tmp;
|
||||
|
||||
/*
|
||||
* Reset the bridge, assert the fundamental reset. Note for some SoCs,
|
||||
* e.g. BCM7278, the fundamental reset should not be asserted here.
|
||||
* This will need to be changed when support for other SoCs is added.
|
||||
*/
|
||||
setbits_le32(base + PCIE_RGR1_SW_INIT_1,
|
||||
RGR1_SW_INIT_1_INIT_MASK | RGR1_SW_INIT_1_PERST_MASK);
|
||||
/*
|
||||
* The delay is a safety precaution to preclude the reset signal
|
||||
* from looking like a glitch.
|
||||
*/
|
||||
udelay(100);
|
||||
|
||||
/* Take the bridge out of reset */
|
||||
clrbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_INIT_MASK);
|
||||
|
||||
clrbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG,
|
||||
PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
|
||||
|
||||
/* Wait for SerDes to be stable */
|
||||
udelay(100);
|
||||
|
||||
/* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
|
||||
clrsetbits_le32(base + PCIE_MISC_MISC_CTRL,
|
||||
MISC_CTRL_MAX_BURST_SIZE_MASK,
|
||||
MISC_CTRL_SCB_ACCESS_EN_MASK |
|
||||
MISC_CTRL_CFG_READ_UR_MODE_MASK |
|
||||
MISC_CTRL_MAX_BURST_SIZE_128);
|
||||
/*
|
||||
* TODO: When support for other SoCs than BCM2711 is added we may
|
||||
* need to use the base address and size(s) provided in the dma-ranges
|
||||
* property.
|
||||
*/
|
||||
rc_bar2_offset = 0;
|
||||
rc_bar2_size = 0xc0000000;
|
||||
|
||||
tmp = lower_32_bits(rc_bar2_offset);
|
||||
u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size),
|
||||
RC_BAR2_CONFIG_LO_SIZE_MASK);
|
||||
writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
|
||||
writel(upper_32_bits(rc_bar2_offset),
|
||||
base + PCIE_MISC_RC_BAR2_CONFIG_HI);
|
||||
|
||||
scb_size_val = rc_bar2_size ?
|
||||
ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */
|
||||
|
||||
tmp = readl(base + PCIE_MISC_MISC_CTRL);
|
||||
u32p_replace_bits(&tmp, scb_size_val,
|
||||
MISC_CTRL_SCB0_SIZE_MASK);
|
||||
writel(tmp, base + PCIE_MISC_MISC_CTRL);
|
||||
|
||||
/* Disable the PCIe->GISB memory window (RC_BAR1) */
|
||||
clrbits_le32(base + PCIE_MISC_RC_BAR1_CONFIG_LO,
|
||||
RC_BAR1_CONFIG_LO_SIZE_MASK);
|
||||
|
||||
/* Disable the PCIe->SCB memory window (RC_BAR3) */
|
||||
clrbits_le32(base + PCIE_MISC_RC_BAR3_CONFIG_LO,
|
||||
RC_BAR3_CONFIG_LO_SIZE_MASK);
|
||||
|
||||
/* Mask all interrupts since we are not handling any yet */
|
||||
writel(0xffffffff, base + PCIE_MSI_INTR2_MASK_SET);
|
||||
|
||||
/* Clear any interrupts we find on boot */
|
||||
writel(0xffffffff, base + PCIE_MSI_INTR2_CLR);
|
||||
|
||||
if (pcie->gen)
|
||||
brcm_pcie_set_gen(pcie, pcie->gen);
|
||||
|
||||
/* Unassert the fundamental reset */
|
||||
clrbits_le32(pcie->base + PCIE_RGR1_SW_INIT_1,
|
||||
RGR1_SW_INIT_1_PERST_MASK);
|
||||
|
||||
/* Give the RC/EP time to wake up, before trying to configure RC.
|
||||
* Intermittently check status for link-up, up to a total of 100ms.
|
||||
*/
|
||||
for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5)
|
||||
mdelay(5);
|
||||
|
||||
if (!brcm_pcie_link_up(pcie)) {
|
||||
printf("PCIe BRCM: link down\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (!brcm_pcie_rc_mode(pcie)) {
|
||||
printf("PCIe misconfigured; is in EP mode\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
for (i = 0; i < hose->region_count; i++) {
|
||||
struct pci_region *reg = &hose->regions[i];
|
||||
|
||||
if (reg->flags != PCI_REGION_MEM)
|
||||
continue;
|
||||
|
||||
if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS)
|
||||
return -EINVAL;
|
||||
|
||||
brcm_pcie_set_outbound_win(pcie, num_out_wins, reg->phys_start,
|
||||
reg->bus_start, reg->size);
|
||||
|
||||
num_out_wins++;
|
||||
}
|
||||
|
||||
/*
|
||||
* For config space accesses on the RC, show the right class for
|
||||
* a PCIe-PCIe bridge (the default setting is to be EP mode).
|
||||
*/
|
||||
clrsetbits_le32(base + PCIE_RC_CFG_PRIV1_ID_VAL3,
|
||||
CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK, 0x060400);
|
||||
|
||||
if (pcie->ssc) {
|
||||
ret = brcm_pcie_set_ssc(pcie->base);
|
||||
if (!ret)
|
||||
ssc_good = true;
|
||||
else
|
||||
printf("PCIe BRCM: failed attempt to enter SSC mode\n");
|
||||
}
|
||||
|
||||
lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
|
||||
cls = lnksta & PCI_EXP_LNKSTA_CLS;
|
||||
nlw = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
|
||||
|
||||
printf("PCIe BRCM: link up, %s Gbps x%u %s\n", link_speed_to_str(cls),
|
||||
nlw, ssc_good ? "(SSC)" : "(!SSC)");
|
||||
|
||||
/* PCIe->SCB endian mode for BAR */
|
||||
clrsetbits_le32(base + PCIE_RC_CFG_VENDOR_SPECIFIC_REG1,
|
||||
VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK,
|
||||
VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN);
|
||||
/*
|
||||
* Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
|
||||
* is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
|
||||
*/
|
||||
setbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG,
|
||||
PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int brcm_pcie_ofdata_to_platdata(struct udevice *dev)
|
||||
{
|
||||
struct brcm_pcie *pcie = dev_get_priv(dev);
|
||||
ofnode dn = dev_ofnode(dev);
|
||||
u32 max_link_speed;
|
||||
int ret;
|
||||
|
||||
/* Get the controller base address */
|
||||
pcie->base = dev_read_addr_ptr(dev);
|
||||
if (!pcie->base)
|
||||
return -EINVAL;
|
||||
|
||||
pcie->ssc = ofnode_read_bool(dn, "brcm,enable-ssc");
|
||||
|
||||
ret = ofnode_read_u32(dn, "max-link-speed", &max_link_speed);
|
||||
if (ret < 0 || max_link_speed > 4)
|
||||
pcie->gen = 0;
|
||||
else
|
||||
pcie->gen = max_link_speed;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dm_pci_ops brcm_pcie_ops = {
|
||||
.read_config = brcm_pcie_read_config,
|
||||
.write_config = brcm_pcie_write_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id brcm_pcie_ids[] = {
|
||||
{ .compatible = "brcm,bcm2711-pcie" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(pcie_brcm_base) = {
|
||||
.name = "pcie_brcm",
|
||||
.id = UCLASS_PCI,
|
||||
.ops = &brcm_pcie_ops,
|
||||
.of_match = brcm_pcie_ids,
|
||||
.probe = brcm_pcie_probe,
|
||||
.ofdata_to_platdata = brcm_pcie_ofdata_to_platdata,
|
||||
.priv_auto_alloc_size = sizeof(struct brcm_pcie),
|
||||
};
|
||||
|
|
@ -67,9 +67,6 @@
|
|||
#define IS_ROOT_PORT(pcie, bdf) \
|
||||
((PCI_BUS(bdf) == pcie->first_busno) ? true : false)
|
||||
|
||||
#define PCI_EXP_LNKSTA 18 /* Link Status */
|
||||
#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
|
||||
|
||||
/**
|
||||
* struct intel_fpga_pcie - Intel FPGA PCIe controller state
|
||||
* @bus: Pointer to the PCI bus
|
||||
|
|
|
|||
|
|
@ -153,4 +153,15 @@ config RESET_SYSCON
|
|||
depends on DM_RESET
|
||||
help
|
||||
Support generic syscon mapped register reset devices.
|
||||
|
||||
config RESET_RASPBERRYPI
|
||||
bool "Raspberry Pi 4 Firmware Reset Controller Driver"
|
||||
depends on DM_RESET && ARCH_BCM283X
|
||||
default USB_XHCI_PCI
|
||||
help
|
||||
Raspberry Pi 4's co-processor controls some of the board's HW
|
||||
initialization process, but it's up to Linux to trigger it when
|
||||
relevant. This driver provides a reset controller capable of
|
||||
interfacing with RPi4's co-processor and model these firmware
|
||||
initialization routines as reset lines.
|
||||
endmenu
|
||||
|
|
|
|||
|
|
@ -24,3 +24,4 @@ obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
|
|||
obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
|
||||
obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
|
||||
obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o
|
||||
obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
|
||||
|
|
|
|||
60
drivers/reset/reset-raspberrypi.c
Normal file
60
drivers/reset/reset-raspberrypi.c
Normal file
|
|
@ -0,0 +1,60 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Raspberry Pi 4 firmware reset driver
|
||||
*
|
||||
* Copyright (C) 2020 Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <reset-uclass.h>
|
||||
#include <asm/arch/msg.h>
|
||||
#include <dt-bindings/reset/raspberrypi,firmware-reset.h>
|
||||
|
||||
static int raspberrypi_reset_request(struct reset_ctl *reset_ctl)
|
||||
{
|
||||
if (reset_ctl->id >= RASPBERRYPI_FIRMWARE_RESET_NUM_IDS)
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int raspberrypi_reset_free(struct reset_ctl *reset_ctl)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int raspberrypi_reset_assert(struct reset_ctl *reset_ctl)
|
||||
{
|
||||
switch (reset_ctl->id) {
|
||||
case RASPBERRYPI_FIRMWARE_RESET_ID_USB:
|
||||
bcm2711_notify_vl805_reset();
|
||||
return 0;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
static int raspberrypi_reset_deassert(struct reset_ctl *reset_ctl)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct reset_ops raspberrypi_reset_ops = {
|
||||
.request = raspberrypi_reset_request,
|
||||
.rfree = raspberrypi_reset_free,
|
||||
.rst_assert = raspberrypi_reset_assert,
|
||||
.rst_deassert = raspberrypi_reset_deassert,
|
||||
};
|
||||
|
||||
static const struct udevice_id raspberrypi_reset_ids[] = {
|
||||
{ .compatible = "raspberrypi,firmware-reset" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(raspberrypi_reset) = {
|
||||
.name = "raspberrypi-reset",
|
||||
.id = UCLASS_RESET,
|
||||
.of_match = raspberrypi_reset_ids,
|
||||
.ops = &raspberrypi_reset_ops,
|
||||
};
|
||||
|
||||
|
|
@ -180,6 +180,8 @@ void xhci_cleanup(struct xhci_ctrl *ctrl)
|
|||
xhci_free_virt_devices(ctrl);
|
||||
free(ctrl->erst.entries);
|
||||
free(ctrl->dcbaa);
|
||||
if (reset_valid(&ctrl->reset))
|
||||
reset_free(&ctrl->reset);
|
||||
memset(ctrl, '\0', sizeof(struct xhci_ctrl));
|
||||
}
|
||||
|
||||
|
|
@ -395,6 +397,9 @@ static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl)
|
|||
scratchpad->sp_array[i] = cpu_to_le64(ptr);
|
||||
}
|
||||
|
||||
xhci_flush_cache((uintptr_t)scratchpad->sp_array,
|
||||
sizeof(u64) * num_sp);
|
||||
|
||||
return 0;
|
||||
|
||||
fail_sp3:
|
||||
|
|
|
|||
|
|
@ -190,6 +190,37 @@ static int xhci_start(struct xhci_hcor *hcor)
|
|||
return ret;
|
||||
}
|
||||
|
||||
#if CONFIG_IS_ENABLED(DM_USB)
|
||||
/**
|
||||
* Resets XHCI Hardware
|
||||
*
|
||||
* @param ctrl pointer to host controller
|
||||
* @return 0 if OK, or a negative error code.
|
||||
*/
|
||||
static int xhci_reset_hw(struct xhci_ctrl *ctrl)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = reset_get_by_index(ctrl->dev, 0, &ctrl->reset);
|
||||
if (ret && ret != -ENOENT && ret != -ENOTSUPP) {
|
||||
dev_err(ctrl->dev, "failed to get reset\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (reset_valid(&ctrl->reset)) {
|
||||
ret = reset_assert(&ctrl->reset);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = reset_deassert(&ctrl->reset);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Resets the XHCI Controller
|
||||
*
|
||||
|
|
@ -1508,6 +1539,10 @@ int xhci_register(struct udevice *dev, struct xhci_hccr *hccr,
|
|||
|
||||
ctrl->dev = dev;
|
||||
|
||||
ret = xhci_reset_hw(ctrl);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
/*
|
||||
* XHCI needs to issue a Address device command to setup
|
||||
* proper device context structures, before it can interact
|
||||
|
|
|
|||
13
include/dt-bindings/reset/raspberrypi,firmware-reset.h
Normal file
13
include/dt-bindings/reset/raspberrypi,firmware-reset.h
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2020 Nicolas Saenz Julienne
|
||||
* Author: Nicolas Saenz Julienne <nsaenzjulienne@suse.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_RASPBERRYPI_FIRMWARE_RESET_H
|
||||
#define _DT_BINDINGS_RASPBERRYPI_FIRMWARE_RESET_H
|
||||
|
||||
#define RASPBERRYPI_FIRMWARE_RESET_ID_USB 0
|
||||
#define RASPBERRYPI_FIRMWARE_RESET_NUM_IDS 1
|
||||
|
||||
#endif
|
||||
|
|
@ -16,6 +16,7 @@
|
|||
#define _LINUX_BITFIELD_H
|
||||
|
||||
#include <linux/bug.h>
|
||||
#include <asm/byteorder.h>
|
||||
|
||||
/*
|
||||
* Bitfield access macros
|
||||
|
|
@ -103,4 +104,56 @@
|
|||
(typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \
|
||||
})
|
||||
|
||||
extern void __compiletime_error("value doesn't fit into mask")
|
||||
__field_overflow(void);
|
||||
extern void __compiletime_error("bad bitfield mask")
|
||||
__bad_mask(void);
|
||||
|
||||
static __always_inline u64 field_multiplier(u64 field)
|
||||
{
|
||||
if ((field | (field - 1)) & ((field | (field - 1)) + 1))
|
||||
__bad_mask();
|
||||
return field & -field;
|
||||
}
|
||||
|
||||
static __always_inline u64 field_mask(u64 field)
|
||||
{
|
||||
return field / field_multiplier(field);
|
||||
}
|
||||
|
||||
#define ____MAKE_OP(type, base, to, from) \
|
||||
static __always_inline __##type type##_encode_bits(base v, base field) \
|
||||
{ \
|
||||
if (__builtin_constant_p(v) && (v & ~field_mask(field))) \
|
||||
__field_overflow(); \
|
||||
return to((v & field_mask(field)) * field_multiplier(field)); \
|
||||
} \
|
||||
static __always_inline __##type type##_replace_bits(__##type old, \
|
||||
base val, base field) \
|
||||
{ \
|
||||
return (old & ~to(field)) | type##_encode_bits(val, field); \
|
||||
} \
|
||||
static __always_inline void type##p_replace_bits(__##type * p, \
|
||||
base val, base field) \
|
||||
{ \
|
||||
*p = (*p & ~to(field)) | type##_encode_bits(val, field); \
|
||||
} \
|
||||
static __always_inline base type##_get_bits(__##type v, base field) \
|
||||
{ \
|
||||
return (from(v) & field) / field_multiplier(field); \
|
||||
}
|
||||
|
||||
#define __MAKE_OP(size) \
|
||||
____MAKE_OP(le##size, u##size, cpu_to_le##size, le##size##_to_cpu) \
|
||||
____MAKE_OP(be##size, u##size, cpu_to_be##size, be##size##_to_cpu) \
|
||||
____MAKE_OP(u##size, u##size, ,)
|
||||
|
||||
____MAKE_OP(u8, u8, ,)
|
||||
__MAKE_OP(16)
|
||||
__MAKE_OP(32)
|
||||
__MAKE_OP(64)
|
||||
|
||||
#undef __MAKE_OP
|
||||
#undef ____MAKE_OP
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -471,10 +471,28 @@
|
|||
#define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */
|
||||
|
||||
/* PCI Express capabilities */
|
||||
#define PCI_EXP_FLAGS 2 /* Capabilities register */
|
||||
#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
|
||||
#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
|
||||
#define PCI_EXP_DEVCAP 4 /* Device capabilities */
|
||||
#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */
|
||||
#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */
|
||||
#define PCI_EXP_DEVCTL 8 /* Device Control */
|
||||
#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */
|
||||
#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */
|
||||
#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
|
||||
#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */
|
||||
#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
|
||||
#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */
|
||||
#define PCI_EXP_LNKSTA 18 /* Link Status */
|
||||
#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */
|
||||
#define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */
|
||||
#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
|
||||
#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
|
||||
#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */
|
||||
#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */
|
||||
#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
|
||||
#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
|
||||
#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
|
||||
#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
|
||||
|
||||
/* Include the ID list */
|
||||
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@
|
|||
#ifndef HOST_XHCI_H_
|
||||
#define HOST_XHCI_H_
|
||||
|
||||
#include <reset.h>
|
||||
#include <asm/types.h>
|
||||
#include <asm/cache.h>
|
||||
#include <asm/io.h>
|
||||
|
|
@ -1114,28 +1115,20 @@ static inline void xhci_writel(uint32_t volatile *regs, const unsigned int val)
|
|||
*/
|
||||
static inline u64 xhci_readq(__le64 volatile *regs)
|
||||
{
|
||||
#if BITS_PER_LONG == 64
|
||||
return readq(regs);
|
||||
#else
|
||||
__u32 *ptr = (__u32 *)regs;
|
||||
u64 val_lo = readl(ptr);
|
||||
u64 val_hi = readl(ptr + 1);
|
||||
return val_lo + (val_hi << 32);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void xhci_writeq(__le64 volatile *regs, const u64 val)
|
||||
{
|
||||
#if BITS_PER_LONG == 64
|
||||
writeq(val, regs);
|
||||
#else
|
||||
__u32 *ptr = (__u32 *)regs;
|
||||
u32 val_lo = lower_32_bits(val);
|
||||
/* FIXME */
|
||||
u32 val_hi = upper_32_bits(val);
|
||||
writel(val_lo, ptr);
|
||||
writel(val_hi, ptr + 1);
|
||||
#endif
|
||||
}
|
||||
|
||||
int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr,
|
||||
|
|
@ -1217,6 +1210,7 @@ struct xhci_ctrl {
|
|||
#if CONFIG_IS_ENABLED(DM_USB)
|
||||
struct udevice *dev;
|
||||
#endif
|
||||
struct reset_ctl reset;
|
||||
struct xhci_hccr *hccr; /* R/O registers, not need for volatile */
|
||||
struct xhci_hcor *hcor;
|
||||
struct xhci_doorbell_array *dba;
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user