brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-07-05 10:46:15 +09:00
Code Issues Projects Releases Wiki Activity

ram: rk3399: s/ca_tsel_wr_select_p/tsel_wr_select_ca_p

Browse Source 
Rename ca_tsel_wr_select_p to tsel_wr_select_ca_p based
on the bsp code.

No functionality change.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
This commit is contained in:
Jagan Teki 2019-07-15 23:51:03 +05:30 committed by Kever Yang
parent a12a5be7a3
commit 30bd86a399
1 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/ram/rockchip/sdram_rk3399.c
View File

@ -160,14 +160,14 @@ static void set_ds_odt(const struct chan_info *chan,
u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p;
u32 ca_tsel_wr_select_p, tsel_wr_select_ca_n;
u32 tsel_wr_select_ca_p, tsel_wr_select_ca_n;
u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n;
u32 reg_value;
if (params->base.dramtype == LPDDR4) {
tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
tsel_wr_select_dq_p = PHY_DRV_ODT_40;
ca_tsel_wr_select_p = PHY_DRV_ODT_40;
tsel_wr_select_ca_p = PHY_DRV_ODT_40;
tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
tsel_rd_select_n = PHY_DRV_ODT_240;
@ -177,7 +177,7 @@ static void set_ds_odt(const struct chan_info *chan,
} else if (params->base.dramtype == LPDDR3) {
tsel_rd_select_p = PHY_DRV_ODT_240;
tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
ca_tsel_wr_select_p = PHY_DRV_ODT_48;
tsel_wr_select_ca_p = PHY_DRV_ODT_48;
tsel_idle_select_p = PHY_DRV_ODT_240;
tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
@ -187,7 +187,7 @@ static void set_ds_odt(const struct chan_info *chan,
} else {
tsel_rd_select_p = PHY_DRV_ODT_240;
tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
ca_tsel_wr_select_p = PHY_DRV_ODT_34_3;
tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
tsel_idle_select_p = PHY_DRV_ODT_240;
tsel_rd_select_n = PHY_DRV_ODT_240;
@ -228,7 +228,7 @@ static void set_ds_odt(const struct chan_info *chan,
clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value);
/* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */
reg_value = tsel_wr_select_ca_n | (ca_tsel_wr_select_p << 0x4);
reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4);
clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
clrsetbits_le32(&denali_phy[800], 0xff, reg_value);