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https://github.com/brain-hackers/u-boot-brain
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Merge branch 'pci'
This commit is contained in:
commit
304ad60f7d
13
CHANGELOG
13
CHANGELOG
@ -2,6 +2,19 @@
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Changes since U-Boot 1.1.4:
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======================================================================
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* Report back PCI bus when doing table based device config
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Patch by Kumar Gala 11 Jan 2006
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* Added support for PCI prefetchable region and BARs
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If a host controller sets up a region as prefetchable and
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a device's BAR denotes it as prefetchable, allocate the
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BAR into the prefetch region.
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If a BAR is prefetchable and no prefetchable region has
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been setup by the controller we fall back to allocating
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the BAR into the normally memory region.
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Patch by Kumar Gala 11 Jan 2006
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* Only disable the MPC83xx watchdog if its enabled out of reset.
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If its disabled out of reset SW can later enable it if so desired
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Patch by Kumar Gala, 11 Jan 2006
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@ -459,6 +459,7 @@ int pci_hose_scan_bus(struct pci_controller *hose, int bus)
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PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
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if (cfg) {
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cfg->config_device(hose, dev, cfg);
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sub_bus = max(sub_bus, hose->current_busno);
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#ifdef CONFIG_PCI_PNP
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} else {
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int n = pciauto_config_device(hose, dev);
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@ -77,6 +77,7 @@ int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned
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void pciauto_setup_device(struct pci_controller *hose,
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pci_dev_t dev, int bars_num,
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struct pci_region *mem,
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struct pci_region *prefetch,
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struct pci_region *io)
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{
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unsigned int bar_value, bar_response, bar_size;
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@ -111,7 +112,10 @@ void pciauto_setup_device(struct pci_controller *hose,
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found_mem64 = 1;
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bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;
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bar_res = mem;
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if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
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bar_res = prefetch;
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else
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bar_res = mem;
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DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%x, ", bar_nr, bar_size);
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}
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@ -148,6 +152,7 @@ static void pciauto_prescan_setup_bridge(struct pci_controller *hose,
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pci_dev_t dev, int sub_bus)
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{
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struct pci_region *pci_mem = hose->pci_mem;
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struct pci_region *pci_prefetch = hose->pci_prefetch;
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struct pci_region *pci_io = hose->pci_io;
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unsigned int cmdstat;
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@ -169,6 +174,21 @@ static void pciauto_prescan_setup_bridge(struct pci_controller *hose,
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cmdstat |= PCI_COMMAND_MEMORY;
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}
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if (pci_prefetch) {
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/* Round memory allocator to 1MB boundary */
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pciauto_region_align(pci_prefetch, 0x100000);
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/* Set up memory and I/O filter limits, assume 32-bit I/O space */
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pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
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(pci_prefetch->bus_lower & 0xfff00000) >> 16);
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cmdstat |= PCI_COMMAND_MEMORY;
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} else {
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/* We don't support prefetchable memory for now, so disable */
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pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
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pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000);
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}
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if (pci_io) {
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/* Round I/O allocator to 4KB boundary */
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pciauto_region_align(pci_io, 0x1000);
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@ -181,10 +201,6 @@ static void pciauto_prescan_setup_bridge(struct pci_controller *hose,
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cmdstat |= PCI_COMMAND_IO;
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}
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/* We don't support prefetchable memory for now, so disable */
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pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
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pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000);
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/* Enable memory and I/O accesses, enable bus master */
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pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
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}
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@ -193,6 +209,7 @@ static void pciauto_postscan_setup_bridge(struct pci_controller *hose,
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pci_dev_t dev, int sub_bus)
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{
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struct pci_region *pci_mem = hose->pci_mem;
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struct pci_region *pci_prefetch = hose->pci_prefetch;
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struct pci_region *pci_io = hose->pci_io;
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/* Configure bus number registers */
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@ -206,6 +223,14 @@ static void pciauto_postscan_setup_bridge(struct pci_controller *hose,
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(pci_mem->bus_lower-1) >> 16);
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}
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if (pci_prefetch) {
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/* Round memory allocator to 1MB boundary */
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pciauto_region_align(pci_prefetch, 0x100000);
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pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
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(pci_prefetch->bus_lower-1) >> 16);
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}
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if (pci_io) {
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/* Round I/O allocator to 4KB boundary */
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pciauto_region_align(pci_io, 0x1000);
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@ -239,6 +264,11 @@ void pciauto_config_init(struct pci_controller *hose)
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hose->pci_mem->size < hose->regions[i].size)
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hose->pci_mem = hose->regions + i;
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break;
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case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
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if (!hose->pci_prefetch ||
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hose->pci_prefetch->size < hose->regions[i].size)
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hose->pci_prefetch = hose->regions + i;
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break;
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}
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}
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@ -251,6 +281,14 @@ void pciauto_config_init(struct pci_controller *hose)
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hose->pci_mem->bus_start + hose->pci_mem->size - 1);
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}
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if (hose->pci_prefetch) {
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pciauto_region_init(hose->pci_prefetch);
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DEBUGF("PCI Autoconfig: Prefetchable Memory region: [%lx-%lx]\n",
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hose->pci_prefetch->bus_start,
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hose->pci_prefetch->bus_start + hose->pci_prefetch->size - 1);
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}
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if (hose->pci_io) {
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pciauto_region_init(hose->pci_io);
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@ -275,7 +313,7 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
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switch(class) {
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case PCI_CLASS_BRIDGE_PCI:
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hose->current_busno++;
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pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_io);
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pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
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DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));
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@ -301,12 +339,12 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
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return sub_bus;
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}
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pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
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pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
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break;
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case PCI_CLASS_BRIDGE_CARDBUS:
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/* just do a minimal setup of the bridge, let the OS take care of the rest */
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pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_io);
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pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
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DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n", PCI_DEV(dev));
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@ -328,11 +366,11 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
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* the PIMMR window to be allocated (BAR0 - 1MB size)
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*/
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DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n");
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pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_io);
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pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
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break;
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#endif
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default:
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pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
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pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
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break;
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}
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@ -309,6 +309,7 @@ struct pci_region {
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#define PCI_REGION_MEM 0x00000000 /* PCI memory space */
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#define PCI_REGION_IO 0x00000001 /* PCI IO space */
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#define PCI_REGION_TYPE 0x00000001
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#define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */
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#define PCI_REGION_MEMORY 0x00000100 /* System memory */
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#define PCI_REGION_RO 0x00000200 /* Read-only memory */
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@ -386,7 +387,7 @@ struct pci_controller {
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int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);
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/* Used by auto config */
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struct pci_region *pci_mem, *pci_io;
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struct pci_region *pci_mem, *pci_io, *pci_prefetch;
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/* Used by ppc405 autoconfig*/
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struct pci_region *pci_fb;
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@ -472,6 +473,7 @@ extern int pciauto_region_allocate(struct pci_region* res, unsigned int size, un
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extern void pciauto_setup_device(struct pci_controller *hose,
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pci_dev_t dev, int bars_num,
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struct pci_region *mem,
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struct pci_region *prefetch,
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struct pci_region *io);
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int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
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