mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
Fixes for 2020.01
----------------- - imx8qxp_mek: increase buffer sizes and args number - Fixes for imx7ulp - imx8mm: Fix the first root clock in imx8mm_ahb_sels[] - colibri_imx7: reserve DDR memory for Cortex-M4 - vining2000: fixes and convert to ethernet DM - imx8m: fix rom version check to unbreak some B0 chips - tbs2910: Disable VxWorks image booting support -----BEGIN PGP SIGNATURE----- iQHDBAABCgAtFiEEiZClFGvhzbUNsmAvKMTY0yrV63cFAl3uLqsPHHNiYWJpY0Bk ZW54LmRlAAoJECjE2NMq1et3YEEL/jAKMnREGNHCjvwvxkVVZ7sWHeRtqh+OXb8V VnZB0glptth1NDxWyHFZkcsVqjpRlUsm3/lA91xaFXcUB8EWnJMKVReHkB7v0bZW zHziN0rNPoTBVocRlpgPXt3zeSOR3Qg+rFesg4zmlXNIVPyvBanpDCxXDK60gdIi JDrAdIarP0UMK0roIFLIyvnJ+J/ib1ky1aJI8cdktXb+nSyVrMw5VDdmSBtTCp10 6o/fJGtWfzXp59a8y9XnnVxNsU2c0URcsswub4fvWhhwJ86xiWGSEfm5Sybql6kS 6PYjB7jGmdWJjYug7rFthl1Hnn1FULIH9qrxPePtD2ooUUjHPlDmElQqWkHoVlib yUAlWG87ZdjhmEMR1iSFlkcBpOD7SlmcvfYZdeedCdtzTwW0kj6lcX9fUKHE+17e 3SJQtPxpMrVfnUDRn0ciAbwg8+1Tow6sv39j6iYi7jAITny9q16ErdRGup0wB19Y tZkmRdnhtjCalrfDoEaRGXZJDE15XQ== =L2zo -----END PGP SIGNATURE----- Merge tag 'u-boot-imx-20191209' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx Fixes for 2020.01 ----------------- - imx8qxp_mek: increase buffer sizes and args number - Fixes for imx7ulp - imx8mm: Fix the first root clock in imx8mm_ahb_sels[] - colibri_imx7: reserve DDR memory for Cortex-M4 - vining2000: fixes and convert to ethernet DM - imx8m: fix rom version check to unbreak some B0 chips - tbs2910: Disable VxWorks image booting support
This commit is contained in:
Tom Rini
commit
2f02845817
|
|
@ -270,6 +270,17 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
®_pcie {
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regulator-always-on;
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||||
};
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&pcie {
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||||
pinctrl-names = "default";
|
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pinctrl-0 = <&pinctrl_pcie>;
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reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>;
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status = "okay";
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||||
};
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|
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpios>;
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|
|
@ -360,6 +371,12 @@
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>;
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};
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|
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pinctrl_pcie: pciegrp {
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fsl,pins = <
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MX6SX_PAD_NAND_DATA02__GPIO4_IO_6 0x10b0
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||||
>;
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};
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pinctrl_pwm1: pwm1grp-1 {
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fsl,pins = <
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/* blue LED */
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|
|
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|
|
@ -15,7 +15,7 @@
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compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system";
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chosen {
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bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0010,115200";
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bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0000,115200";
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stdout-path = &lpuart4;
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};
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|
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@ -66,7 +66,7 @@
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compatible = "regulator-fixed";
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reg = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb_otg1>;
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pinctrl-0 = <&pinctrl_usbotg1_vbus>;
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regulator-name = "usb_otg1_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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|
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@ -84,22 +84,6 @@
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enable-active-high;
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};
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reg_vsd_3v3b: regulator@2 {
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compatible = "regulator-fixed";
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reg = <2>;
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regulator-name = "VSD_3V3B";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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extcon_usb1: extcon_usb1 {
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compatible = "linux,extcon-usb-gpio";
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id-gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_extcon_usb1>;
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};
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pf1550-rpmsg {
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|
|
@ -166,134 +150,135 @@
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imx7ulp-evk {
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pinctrl_hog_1: hoggrp-1 {
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fsl,pins = <
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ULP1_PAD_PTC10__PTC10 0x30100 /* USDHC0 CD */
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ULP1_PAD_PTC1__PTC1 0x20100
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ULP1_PAD_PTD0__PTD0 0x30100 /* USDHC0 RST */
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ULP1_PAD_PTE13__PTE13 0x30103 /* USDHC1 CD */
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ULP1_PAD_PTE12__PTE12 0x30103 /* USDHC1 WP */
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ULP1_PAD_PTE14__SDHC1_VS 0x843 /* USDHC1 VSEL */
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IMX7ULP_PAD_PTC1__PTC1 0x20000
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>;
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};
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pinctrl_backlight: backlight_grp {
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fsl,pins = <
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ULP1_PAD_PTF2__PTF2 0x20100
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IMX7ULP_PAD_PTF2__PTF2 0x20100
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>;
|
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};
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pinctrl_lpi2c5: lpi2c5grp {
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fsl,pins = <
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ULP1_PAD_PTC4__LPI2C5_SCL 0x527
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ULP1_PAD_PTC5__LPI2C5_SDA 0x527
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IMX7ULP_PAD_PTC4__LPI2C5_SCL 0x27
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IMX7ULP_PAD_PTC5__LPI2C5_SDA 0x27
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>;
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};
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pinctrl_mipi_dsi_reset: mipi_dsi_reset_grp {
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fsl,pins = <
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ULP1_PAD_PTC19__PTC19 0x20103
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IMX7ULP_PAD_PTC19__PTC19 0x20003
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>;
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};
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pinctrl_lpuart4: lpuart4grp {
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fsl,pins = <
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ULP1_PAD_PTC3__LPUART4_RX 0x400
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ULP1_PAD_PTC2__LPUART4_TX 0x400
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IMX7ULP_PAD_PTC3__LPUART4_RX 0x3
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IMX7ULP_PAD_PTC2__LPUART4_TX 0x3
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>;
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};
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pinctrl_lpuart6: lpuart6grp {
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fsl,pins = <
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ULP1_PAD_PTE10__LPUART6_TX 0x400
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ULP1_PAD_PTE11__LPUART6_RX 0x400
|
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ULP1_PAD_PTE9__LPUART6_RTS_B 0x400
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ULP1_PAD_PTE8__LPUART6_CTS_B 0x400
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ULP1_PAD_PTE7__PTE7 0x00 /* BT_REG_ON */
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IMX7ULP_PAD_PTE10__LPUART6_TX 0x3
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IMX7ULP_PAD_PTE11__LPUART6_RX 0x3
|
||||
IMX7ULP_PAD_PTE9__LPUART6_RTS_B 0x3
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IMX7ULP_PAD_PTE8__LPUART6_CTS_B 0x3
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IMX7ULP_PAD_PTE7__PTE7 0x20000 /* BT_REG_ON */
|
||||
>;
|
||||
};
|
||||
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||||
pinctrl_lpuart7: lpuart7grp {
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fsl,pins = <
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ULP1_PAD_PTF14__LPUART7_TX 0x400
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ULP1_PAD_PTF15__LPUART7_RX 0x400
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ULP1_PAD_PTF13__LPUART7_RTS_B 0x400
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ULP1_PAD_PTF12__LPUART7_CTS_B 0x400
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IMX7ULP_PAD_PTF14__LPUART7_TX 0x3
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IMX7ULP_PAD_PTF15__LPUART7_RX 0x3
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IMX7ULP_PAD_PTF13__LPUART7_RTS_B 0x3
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IMX7ULP_PAD_PTF12__LPUART7_CTS_B 0x3
|
||||
>;
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};
|
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|
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pinctrl_usdhc0: usdhc0grp {
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fsl,pins = <
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ULP1_PAD_PTD1__SDHC0_CMD 0x843
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ULP1_PAD_PTD2__SDHC0_CLK 0x10843
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ULP1_PAD_PTD7__SDHC0_D3 0x843
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ULP1_PAD_PTD8__SDHC0_D2 0x843
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ULP1_PAD_PTD9__SDHC0_D1 0x843
|
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ULP1_PAD_PTD10__SDHC0_D0 0x843
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IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
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IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042
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||||
IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
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IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
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IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
|
||||
IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
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||||
IMX7ULP_PAD_PTC10__PTC10 0x10000 /* USDHC0 CD */
|
||||
IMX7ULP_PAD_PTD0__PTD0 0x20000 /* USDHC0 RST */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc0_8bit: usdhc0grp_8bit {
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||||
fsl,pins = <
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ULP1_PAD_PTD1__SDHC0_CMD 0x843
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ULP1_PAD_PTD2__SDHC0_CLK 0x843
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||||
ULP1_PAD_PTD3__SDHC0_D7 0x843
|
||||
ULP1_PAD_PTD4__SDHC0_D6 0x843
|
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ULP1_PAD_PTD5__SDHC0_D5 0x843
|
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ULP1_PAD_PTD6__SDHC0_D4 0x843
|
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ULP1_PAD_PTD7__SDHC0_D3 0x843
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ULP1_PAD_PTD8__SDHC0_D2 0x843
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ULP1_PAD_PTD9__SDHC0_D1 0x843
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ULP1_PAD_PTD10__SDHC0_D0 0x843
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IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
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IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042
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IMX7ULP_PAD_PTD3__SDHC0_D7 0x43
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IMX7ULP_PAD_PTD4__SDHC0_D6 0x43
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IMX7ULP_PAD_PTD5__SDHC0_D5 0x43
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IMX7ULP_PAD_PTD6__SDHC0_D4 0x43
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IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
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IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
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IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
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IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
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IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42
|
||||
>;
|
||||
};
|
||||
|
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pinctrl_lpi2c7: lpi2c7grp {
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fsl,pins = <
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||||
ULP1_PAD_PTF12__LPI2C7_SCL 0x527
|
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ULP1_PAD_PTF13__LPI2C7_SDA 0x527
|
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IMX7ULP_PAD_PTF12__LPI2C7_SCL 0x27
|
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IMX7ULP_PAD_PTF13__LPI2C7_SDA 0x27
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lpspi3: lpspi3grp {
|
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fsl,pins = <
|
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ULP1_PAD_PTF16__LPSPI3_SIN 0x300
|
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ULP1_PAD_PTF17__LPSPI3_SOUT 0x300
|
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ULP1_PAD_PTF18__LPSPI3_SCK 0x300
|
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ULP1_PAD_PTF19__LPSPI3_PCS0 0x300
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IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x0
|
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IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x0
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IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x0
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IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x0
|
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>;
|
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};
|
||||
|
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pinctrl_usb_otg1: usbotg1grp {
|
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pinctrl_usbotg1_vbus: otg1vbusgrp {
|
||||
fsl,pins = <
|
||||
ULP1_PAD_PTC0__PTC0 0x30100
|
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IMX7ULP_PAD_PTC0__PTC0 0x20000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_extcon_usb1: extcon1grp {
|
||||
pinctrl_usbotg1_id: otg1idgrp {
|
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fsl,pins = <
|
||||
ULP1_PAD_PTC8__PTC8 0x30103
|
||||
IMX7ULP_PAD_PTC13__USB0_ID 0x10003
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
ULP1_PAD_PTE3__SDHC1_CMD 0x843
|
||||
ULP1_PAD_PTE2__SDHC1_CLK 0x843
|
||||
ULP1_PAD_PTE1__SDHC1_D0 0x843
|
||||
ULP1_PAD_PTE0__SDHC1_D1 0x843
|
||||
ULP1_PAD_PTE5__SDHC1_D2 0x843
|
||||
ULP1_PAD_PTE4__SDHC1_D3 0x843
|
||||
IMX7ULP_PAD_PTE3__SDHC1_CMD 0x43
|
||||
IMX7ULP_PAD_PTE2__SDHC1_CLK 0x10042
|
||||
IMX7ULP_PAD_PTE1__SDHC1_D0 0x43
|
||||
IMX7ULP_PAD_PTE0__SDHC1_D1 0x43
|
||||
IMX7ULP_PAD_PTE5__SDHC1_D2 0x43
|
||||
IMX7ULP_PAD_PTE4__SDHC1_D3 0x43
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_rst: usdhc1grp_rst {
|
||||
fsl,pins = <
|
||||
ULP1_PAD_PTE11__PTE11 0x30100 /* USDHC1 RST */
|
||||
IMX7ULP_PAD_PTE11__PTE11 0x20000 /* USDHC1 RST */
|
||||
IMX7ULP_PAD_PTE13__PTE13 0x10003 /* USDHC1 CD */
|
||||
IMX7ULP_PAD_PTE12__PTE12 0x10003 /* USDHC1 WP */
|
||||
IMX7ULP_PAD_PTE14__SDHC1_VS 0x43 /* USDHC1 VSEL */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wifi: wifigrp {
|
||||
pinctrl_dsi_hdmi: dsi_hdmi_grp {
|
||||
fsl,pins = <
|
||||
ULP1_PAD_PTE6__PTE6 0x43 /* WL_REG_ON */
|
||||
IMX7ULP_PAD_PTC18__PTC18 0x10003 /* DSI_HDMI_INT */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -304,7 +289,7 @@
|
|||
disp-dev = "mipi_dsi_northwest";
|
||||
display = <&display0>;
|
||||
|
||||
display0: display {
|
||||
display0: display@0 {
|
||||
bits-per-pixel = <16>;
|
||||
bus-width = <24>;
|
||||
|
||||
|
|
@ -343,21 +328,6 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lpi2c5>;
|
||||
status = "okay";
|
||||
|
||||
fxas2100x@20 {
|
||||
compatible = "fsl,fxas2100x";
|
||||
reg = <0x20>;
|
||||
};
|
||||
|
||||
fxos8700@1e {
|
||||
compatible = "fsl,fxos8700";
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
mpl3115@60 {
|
||||
compatible = "fsl,mpl3115";
|
||||
reg = <0x60>;
|
||||
};
|
||||
};
|
||||
|
||||
&lpspi3 {
|
||||
|
|
@ -406,13 +376,18 @@
|
|||
|
||||
&usbotg1 {
|
||||
vbus-supply = <®_usb_otg1_vbus>;
|
||||
extcon = <0>, <&extcon_usb1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg1_id>;
|
||||
srp-disable;
|
||||
hnp-disable;
|
||||
adp-disable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphy1 {
|
||||
fsl,tx-d-cal = <88>;
|
||||
};
|
||||
|
||||
&usdhc0 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
|
||||
pinctrl-0 = <&pinctrl_usdhc0>;
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -16,10 +16,12 @@
|
|||
interrupt-parent = <&intc>;
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpio0;
|
||||
gpio1 = &gpio1;
|
||||
gpio2 = &gpio2;
|
||||
gpio3 = &gpio3;
|
||||
gpio0 = &gpio4;
|
||||
gpio1 = &gpio5;
|
||||
gpio2 = &gpio0;
|
||||
gpio3 = &gpio1;
|
||||
gpio4 = &gpio2;
|
||||
gpio5 = &gpio3;
|
||||
mmc0 = &usdhc0;
|
||||
mmc1 = &usdhc1;
|
||||
serial0 = &lpuart4;
|
||||
|
|
@ -27,10 +29,12 @@
|
|||
serial2 = &lpuart6;
|
||||
serial3 = &lpuart7;
|
||||
usbphy0 = &usbphy1;
|
||||
usb0 = &usbotg1;
|
||||
i2c4 = &lpi2c4;
|
||||
i2c5 = &lpi2c5;
|
||||
i2c6 = &lpi2c6;
|
||||
i2c7 = &lpi2c7;
|
||||
spi0 = &qspi1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
|
|
@ -503,6 +507,22 @@
|
|||
fsl,mux_mask = <0xf00>;
|
||||
};
|
||||
|
||||
gpio4: gpio@4103f000 {
|
||||
compatible = "fsl,imx7ulp-gpio";
|
||||
reg = <0x4103f000 0x1000 0x4100F000 0x40>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 0 32>;
|
||||
};
|
||||
|
||||
gpio5: gpio@41040000 {
|
||||
compatible = "fsl,imx7ulp-gpio";
|
||||
reg = <0x41040000 0x1000 0x4100F040 0x40>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 32 32>;
|
||||
};
|
||||
|
||||
gpio0: gpio@40ae0000 {
|
||||
compatible = "fsl,imx7ulp-gpio";
|
||||
reg = <0x40ae0000 0x1000 0x400F0000 0x40>;
|
||||
|
|
|
|||
|
|
@ -20,6 +20,14 @@
|
|||
int imx6_pcie_toggle_power(void);
|
||||
int imx6_pcie_toggle_reset(void);
|
||||
|
||||
enum ldo_reg {
|
||||
LDO_ARM,
|
||||
LDO_SOC,
|
||||
LDO_PU,
|
||||
};
|
||||
|
||||
int set_ldo_voltage(enum ldo_reg ldo, u32 mv);
|
||||
|
||||
/**
|
||||
* iomuxc_set_rgmii_io_voltage - set voltage level of RGMII/USB pins
|
||||
*
|
||||
|
|
|
|||
|
|
@ -331,7 +331,6 @@ u32 decode_pll(enum pll_clocks pll);
|
|||
void scg_a7_rccr_init(void);
|
||||
void scg_a7_spll_init(void);
|
||||
void scg_a7_ddrclk_init(void);
|
||||
void scg_a7_apll_init(void);
|
||||
void scg_a7_firc_init(void);
|
||||
void scg_a7_nicclk_init(void);
|
||||
void scg_a7_sys_clk_sel(enum scg_sys_src clk);
|
||||
|
|
|
|||
|
|
@ -153,6 +153,8 @@ void init_src(void);
|
|||
void init_snvs(void);
|
||||
void imx_wdog_disable_powerdown(void);
|
||||
|
||||
int arch_auxiliary_core_check_up(u32 core_id);
|
||||
|
||||
int board_mmc_get_env_dev(int devno);
|
||||
|
||||
int nxp_board_rev(void);
|
||||
|
|
|
|||
|
|
@ -217,6 +217,7 @@ u32 get_cpu_rev(void)
|
|||
readl((void __iomem *)ROM_VERSION_A0);
|
||||
if (rom_version != CHIP_REV_1_0) {
|
||||
rom_version = readl((void __iomem *)ROM_VERSION_B0);
|
||||
rom_version &= 0xff;
|
||||
if (rom_version == CHIP_REV_2_0)
|
||||
reg = CHIP_REV_2_0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -558,6 +558,7 @@ config TARGET_SOFTING_VINING_2000
|
|||
select DM
|
||||
select DM_THERMAL
|
||||
select MX6SX
|
||||
select SUPPORT_SPL
|
||||
imply CMD_DM
|
||||
|
||||
config TARGET_WANDBOARD
|
||||
|
|
|
|||
|
|
@ -24,12 +24,6 @@
|
|||
#include <imx_thermal.h>
|
||||
#include <mmc.h>
|
||||
|
||||
enum ldo_reg {
|
||||
LDO_ARM,
|
||||
LDO_SOC,
|
||||
LDO_PU,
|
||||
};
|
||||
|
||||
struct scu_regs {
|
||||
u32 ctrl;
|
||||
u32 config;
|
||||
|
|
@ -255,7 +249,7 @@ static void clear_ldo_ramp(void)
|
|||
* Possible values are from 0.725V to 1.450V in steps of
|
||||
* 0.025V (25mV).
|
||||
*/
|
||||
static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
|
||||
int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
|
||||
{
|
||||
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
|
||||
u32 val, step, old, reg = readl(&anatop->reg_core);
|
||||
|
|
@ -375,6 +369,37 @@ static void init_bandgap(void)
|
|||
}
|
||||
}
|
||||
|
||||
#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL)
|
||||
static void noc_setup(void)
|
||||
{
|
||||
enable_ipu_clock();
|
||||
|
||||
writel(0x80000201, 0xbb0608);
|
||||
/* Bypass IPU1 QoS generator */
|
||||
writel(0x00000002, 0x00bb048c);
|
||||
/* Bypass IPU2 QoS generator */
|
||||
writel(0x00000002, 0x00bb050c);
|
||||
/* Bandwidth THR for of PRE0 */
|
||||
writel(0x00000200, 0x00bb0690);
|
||||
/* Bandwidth THR for of PRE1 */
|
||||
writel(0x00000200, 0x00bb0710);
|
||||
/* Bandwidth THR for of PRE2 */
|
||||
writel(0x00000200, 0x00bb0790);
|
||||
/* Bandwidth THR for of PRE3 */
|
||||
writel(0x00000200, 0x00bb0810);
|
||||
/* Saturation THR for of PRE0 */
|
||||
writel(0x00000010, 0x00bb0694);
|
||||
/* Saturation THR for of PRE1 */
|
||||
writel(0x00000010, 0x00bb0714);
|
||||
/* Saturation THR for of PRE2 */
|
||||
writel(0x00000010, 0x00bb0794);
|
||||
/* Saturation THR for of PRE */
|
||||
writel(0x00000010, 0x00bb0814);
|
||||
|
||||
disable_ipu_clock();
|
||||
}
|
||||
#endif
|
||||
|
||||
int arch_cpu_init(void)
|
||||
{
|
||||
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
|
|
@ -452,6 +477,10 @@ int arch_cpu_init(void)
|
|||
|
||||
init_src();
|
||||
|
||||
#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL)
|
||||
if (is_mx6dqp())
|
||||
noc_setup();
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -3,6 +3,11 @@ if ARCH_MX7ULP
|
|||
config SYS_SOC
|
||||
default "mx7ulp"
|
||||
|
||||
config LDO_ENABLED_MODE
|
||||
bool "i.MX7ULP LDO Enabled Mode"
|
||||
help
|
||||
Select this option to enable the PMC1 LDO.
|
||||
|
||||
config MX7ULP
|
||||
bool
|
||||
|
||||
|
|
|
|||
|
|
@ -949,67 +949,6 @@ void scg_a7_ddrclk_init(void)
|
|||
/* Clock source is System OSC <<0 */
|
||||
#define SCG1_APLL_CFG_CLKSRC_NUM ((0x0) << SCG_PLL_CFG_CLKSRC_SHIFT)
|
||||
|
||||
/*
|
||||
* A7 APLL = 24MHz / 1 * 22 / 1 / 1 = 528MHz,
|
||||
* system PLL is sourced from APLL,
|
||||
* APLL clock source is system OSC (24MHz)
|
||||
*/
|
||||
#define SCG1_APLL_CFG_NUM_24M_OSC (SCG1_APLL_CFG_POSTDIV2_NUM | \
|
||||
SCG1_APLL_CFG_POSTDIV1_NUM | \
|
||||
(22 << SCG_PLL_CFG_MULT_SHIFT) | \
|
||||
SCG1_APLL_CFG_PFDSEL_NUM | \
|
||||
SCG1_APLL_CFG_PREDIV_NUM | \
|
||||
SCG1_APLL_CFG_BYPASS_NUM | \
|
||||
SCG1_APLL_CFG_PLLSEL_NUM | \
|
||||
SCG1_APLL_CFG_CLKSRC_NUM)
|
||||
|
||||
/* PFD0 Freq = A7 APLL(528MHz) * 18 / 27 = 352MHz */
|
||||
#define SCG1_APLL_PFD0_FRAC_NUM (27)
|
||||
|
||||
|
||||
void scg_a7_apll_init(void)
|
||||
{
|
||||
u32 val = 0;
|
||||
|
||||
/* Disable A7 Auxiliary PLL */
|
||||
val = readl(&scg1_regs->apllcsr);
|
||||
val &= ~SCG_APLL_CSR_APLLEN_MASK;
|
||||
writel(val, &scg1_regs->apllcsr);
|
||||
|
||||
/* Gate off A7 APLL PFD0 ~ PDF4 */
|
||||
val = readl(&scg1_regs->apllpfd);
|
||||
val |= 0x80808080;
|
||||
writel(val, &scg1_regs->apllpfd);
|
||||
|
||||
/* ================ A7 APLL Configuration Start ============== */
|
||||
/* Configure A7 Auxiliary PLL */
|
||||
writel(SCG1_APLL_CFG_NUM_24M_OSC, &scg1_regs->apllcfg);
|
||||
|
||||
/* Enable A7 Auxiliary PLL */
|
||||
val = readl(&scg1_regs->apllcsr);
|
||||
val |= SCG_APLL_CSR_APLLEN_MASK;
|
||||
writel(val, &scg1_regs->apllcsr);
|
||||
|
||||
/* Wait for A7 APLL clock ready */
|
||||
while (!(readl(&scg1_regs->apllcsr) & SCG_APLL_CSR_APLLVLD_MASK))
|
||||
;
|
||||
|
||||
/* Configure A7 APLL PFD0 */
|
||||
val = readl(&scg1_regs->apllpfd);
|
||||
val &= ~SCG_PLL_PFD0_FRAC_MASK;
|
||||
val |= SCG1_APLL_PFD0_FRAC_NUM;
|
||||
writel(val, &scg1_regs->apllpfd);
|
||||
|
||||
/* Un-gate A7 APLL PFD0 */
|
||||
val = readl(&scg1_regs->apllpfd);
|
||||
val &= ~SCG_PLL_PFD0_GATE_MASK;
|
||||
writel(val, &scg1_regs->apllpfd);
|
||||
|
||||
/* Wait for A7 APLL PFD0 clock being valid */
|
||||
while (!(readl(&scg1_regs->apllpfd) & SCG_PLL_PFD0_VALID_MASK))
|
||||
;
|
||||
}
|
||||
|
||||
/* SCG1(A7) FIRC DIV configurations */
|
||||
/* Disable FIRC DIV3 */
|
||||
#define SCG1_FIRCDIV_DIV3_NUM ((0x0) << SCG_FIRCDIV_DIV3_SHIFT)
|
||||
|
|
|
|||
|
|
@ -10,6 +10,22 @@
|
|||
#include <asm/mach-imx/boot_mode.h>
|
||||
#include <asm/mach-imx/hab.h>
|
||||
|
||||
#define PMC0_BASE_ADDR 0x410a1000
|
||||
#define PMC0_CTRL 0x28
|
||||
#define PMC0_CTRL_LDOEN BIT(31)
|
||||
#define PMC0_CTRL_LDOOKDIS BIT(30)
|
||||
#define PMC0_CTRL_PMC1ON BIT(24)
|
||||
#define PMC1_BASE_ADDR 0x40400000
|
||||
#define PMC1_RUN 0x8
|
||||
#define PMC1_STOP 0x10
|
||||
#define PMC1_VLPS 0x14
|
||||
#define PMC1_LDOVL_SHIFT 16
|
||||
#define PMC1_LDOVL_MASK (0x3f << PMC1_LDOVL_SHIFT)
|
||||
#define PMC1_LDOVL_900 0x1e
|
||||
#define PMC1_LDOVL_950 0x23
|
||||
#define PMC1_STATUS 0x20
|
||||
#define PMC1_STATUS_LDOVLF BIT(8)
|
||||
|
||||
static char *get_reset_cause(char *);
|
||||
|
||||
#if defined(CONFIG_IMX_HAB)
|
||||
|
|
@ -101,6 +117,44 @@ void init_wdog(void)
|
|||
disable_wdog(WDG2_RBASE);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_LDO_ENABLED_MODE)
|
||||
static void init_ldo_mode(void)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
||||
/* Set LDOOKDIS */
|
||||
setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS);
|
||||
|
||||
/* Set LDOVL to 0.95V in PMC1_RUN */
|
||||
reg = readl(PMC1_BASE_ADDR + PMC1_RUN);
|
||||
reg &= ~PMC1_LDOVL_MASK;
|
||||
reg |= (PMC1_LDOVL_950 << PMC1_LDOVL_SHIFT);
|
||||
writel(PMC1_BASE_ADDR + PMC1_RUN, reg);
|
||||
|
||||
/* Wait for LDOVLF to be cleared */
|
||||
reg = readl(PMC1_BASE_ADDR + PMC1_STATUS);
|
||||
while (reg & PMC1_STATUS_LDOVLF)
|
||||
;
|
||||
|
||||
/* Set LDOVL to 0.95V in PMC1_STOP */
|
||||
reg = readl(PMC1_BASE_ADDR + PMC1_STOP);
|
||||
reg &= ~PMC1_LDOVL_MASK;
|
||||
reg |= (PMC1_LDOVL_950 << PMC1_LDOVL_SHIFT);
|
||||
writel(PMC1_BASE_ADDR + PMC1_STOP, reg);
|
||||
|
||||
/* Set LDOVL to 0.90V in PMC1_VLPS */
|
||||
reg = readl(PMC1_BASE_ADDR + PMC1_VLPS);
|
||||
reg &= ~PMC1_LDOVL_MASK;
|
||||
reg |= (PMC1_LDOVL_900 << PMC1_LDOVL_SHIFT);
|
||||
writel(PMC1_BASE_ADDR + PMC1_VLPS, reg);
|
||||
|
||||
/* Set LDOEN bit */
|
||||
setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN);
|
||||
|
||||
/* Set the PMC1ON bit */
|
||||
setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON);
|
||||
}
|
||||
#endif
|
||||
|
||||
void s_init(void)
|
||||
{
|
||||
|
|
@ -114,6 +168,10 @@ void s_init(void)
|
|||
/* enable dumb pmic */
|
||||
writel((readl(SNVS_LP_LPCR) | SNVS_LPCR_DPEN), SNVS_LP_LPCR);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_LDO_ENABLED_MODE)
|
||||
init_ldo_mode();
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -132,6 +190,21 @@ const char *get_imx_type(u32 imxtype)
|
|||
return "7ULP";
|
||||
}
|
||||
|
||||
#define PMC0_BASE_ADDR 0x410a1000
|
||||
#define PMC0_CTRL 0x28
|
||||
#define PMC0_CTRL_LDOEN BIT(31)
|
||||
|
||||
static bool ldo_mode_is_enabled(void)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
||||
reg = readl(PMC0_BASE_ADDR + PMC0_CTRL);
|
||||
if (reg & PMC0_CTRL_LDOEN)
|
||||
return true;
|
||||
else
|
||||
return false;
|
||||
}
|
||||
|
||||
int print_cpuinfo(void)
|
||||
{
|
||||
u32 cpurev;
|
||||
|
|
@ -160,6 +233,11 @@ int print_cpuinfo(void)
|
|||
break;
|
||||
}
|
||||
|
||||
if (ldo_mode_is_enabled())
|
||||
printf("PMC1: LDO enabled mode\n");
|
||||
else
|
||||
printf("PMC1: LDO bypass mode\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -72,42 +72,23 @@ int dram_init(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static iomux_v3_cfg_t const fec1_pads[] = {
|
||||
MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL) |
|
||||
MUX_MODE_SION,
|
||||
/* LAN8720 PHY Reset */
|
||||
MX6_PAD_RGMII1_TD3__GPIO5_IO_9 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const pwm_led_pads[] = {
|
||||
MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */
|
||||
MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */
|
||||
MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */
|
||||
};
|
||||
|
||||
#define PHY_RESET IMX_GPIO_NR(5, 9)
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
static int board_net_init(void)
|
||||
{
|
||||
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
||||
int ret;
|
||||
unsigned char eth1addr[6];
|
||||
int ret;
|
||||
|
||||
/* just to get secound mac address */
|
||||
/* just to get second mac address */
|
||||
imx_get_mac_from_fuse(1, eth1addr);
|
||||
if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr))
|
||||
eth_env_set_enetaddr("eth1addr", eth1addr);
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
|
||||
|
||||
/*
|
||||
* Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing
|
||||
* ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by
|
||||
|
|
@ -123,15 +104,7 @@ int board_eth_init(bd_t *bis)
|
|||
if (ret)
|
||||
goto eth_fail;
|
||||
|
||||
/* reset phy */
|
||||
gpio_request(PHY_RESET, "PHY-reset");
|
||||
gpio_direction_output(PHY_RESET, 0);
|
||||
mdelay(16);
|
||||
gpio_set_value(PHY_RESET, 1);
|
||||
mdelay(1);
|
||||
|
||||
ret = fecmxc_initialize_multi(bis, 0, CONFIG_FEC_MXC_PHYADDR,
|
||||
IMX_FEC_BASE);
|
||||
ret = enable_fec_anatop_clock(1, ENET_50MHZ);
|
||||
if (ret)
|
||||
goto eth_fail;
|
||||
|
||||
|
|
@ -139,7 +112,6 @@ int board_eth_init(bd_t *bis)
|
|||
|
||||
eth_fail:
|
||||
printf("FEC MXC: %s:failed (%i)\n", __func__, ret);
|
||||
gpio_set_value(PHY_RESET, 0);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -254,6 +226,9 @@ int power_init_board(void)
|
|||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
set_ldo_voltage(LDO_ARM, 1175); /* Set VDDARM to 1.175V */
|
||||
set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -424,7 +399,7 @@ int board_init(void)
|
|||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
return board_net_init();
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
|
|
@ -433,3 +408,218 @@ int checkboard(void)
|
|||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define PCIE_PHY_PUP_REQ BIT(7)
|
||||
|
||||
void board_preboot_os(void)
|
||||
{
|
||||
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
||||
struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
|
||||
|
||||
/* Bring the PCI power domain up, so that old vendorkernel works. */
|
||||
setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
|
||||
setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
|
||||
setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#include <linux/libfdt.h>
|
||||
#include <spl.h>
|
||||
#include <asm/arch/mx6-ddr.h>
|
||||
|
||||
static struct fsl_esdhc_cfg usdhc_cfg = { USDHC4_BASE_ADDR };
|
||||
|
||||
static iomux_v3_cfg_t const pcie_pads[] = {
|
||||
MX6_PAD_NAND_DATA02__GPIO4_IO_6 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const uart_pads[] = {
|
||||
MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const usdhc4_pads[] = {
|
||||
MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void vining2000_spl_setup_iomux_pcie(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
|
||||
}
|
||||
|
||||
static void vining2000_spl_setup_iomux_uart(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
|
||||
}
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
|
||||
u32 val;
|
||||
u32 port;
|
||||
|
||||
val = readl(&src_regs->sbmr1);
|
||||
|
||||
if ((val & 0xc0) != 0x40) {
|
||||
printf("Not boot from USDHC!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
port = (val >> 11) & 0x3;
|
||||
printf("port %d\n", port);
|
||||
switch (port) {
|
||||
case 3:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
|
||||
usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
|
||||
usdhc_cfg.esdhc_base = USDHC4_BASE_ADDR;
|
||||
break;
|
||||
}
|
||||
|
||||
gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
|
||||
return fsl_esdhc_initialize(bis, &usdhc_cfg);
|
||||
}
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
|
||||
.dram_dqm0 = 0x00000028,
|
||||
.dram_dqm1 = 0x00000028,
|
||||
.dram_dqm2 = 0x00000028,
|
||||
.dram_dqm3 = 0x00000028,
|
||||
.dram_ras = 0x00000028,
|
||||
.dram_cas = 0x00000028,
|
||||
.dram_odt0 = 0x00000028,
|
||||
.dram_odt1 = 0x00000028,
|
||||
.dram_sdba2 = 0x00000000,
|
||||
.dram_sdcke0 = 0x00003000,
|
||||
.dram_sdcke1 = 0x00003000,
|
||||
.dram_sdclk_0 = 0x00000030,
|
||||
.dram_sdqs0 = 0x00000028,
|
||||
.dram_sdqs1 = 0x00000028,
|
||||
.dram_sdqs2 = 0x00000028,
|
||||
.dram_sdqs3 = 0x00000028,
|
||||
.dram_reset = 0x00000028,
|
||||
};
|
||||
|
||||
const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
|
||||
.grp_addds = 0x00000028,
|
||||
.grp_b0ds = 0x00000028,
|
||||
.grp_b1ds = 0x00000028,
|
||||
.grp_b2ds = 0x00000028,
|
||||
.grp_b3ds = 0x00000028,
|
||||
.grp_ctlds = 0x00000028,
|
||||
.grp_ddr_type = 0x000c0000,
|
||||
.grp_ddrmode = 0x00020000,
|
||||
.grp_ddrmode_ctl = 0x00020000,
|
||||
.grp_ddrpke = 0x00000000,
|
||||
};
|
||||
|
||||
const struct mx6_mmdc_calibration mx6_mmcd_calib = {
|
||||
.p0_mpwldectrl0 = 0x0022001C,
|
||||
.p0_mpwldectrl1 = 0x001F001A,
|
||||
.p0_mpdgctrl0 = 0x01380134,
|
||||
.p0_mpdgctrl1 = 0x0124011C,
|
||||
.p0_mprddlctl = 0x42404444,
|
||||
.p0_mpwrdlctl = 0x36383C38,
|
||||
};
|
||||
|
||||
static struct mx6_ddr3_cfg mem_ddr = {
|
||||
.mem_speed = 1600,
|
||||
.density = 4,
|
||||
.width = 32,
|
||||
.banks = 8,
|
||||
.rowaddr = 15,
|
||||
.coladdr = 10,
|
||||
.pagesz = 2,
|
||||
.trcd = 1391,
|
||||
.trcmin = 4875,
|
||||
.trasmin = 3500,
|
||||
};
|
||||
|
||||
static void ccgr_init(void)
|
||||
{
|
||||
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
|
||||
writel(0xF000000F, &ccm->CCGR0); /* AIPS_TZ{1,2,3} */
|
||||
writel(0x303C0000, &ccm->CCGR1); /* GPT, OCRAM */
|
||||
writel(0x00FFFCC0, &ccm->CCGR2); /* IPMUX, I2C1, I2C3 */
|
||||
writel(0x3F300030, &ccm->CCGR3); /* OCRAM, MMDC, ENET */
|
||||
writel(0x0000C003, &ccm->CCGR4); /* PCI, PL301 */
|
||||
writel(0x0F0330C3, &ccm->CCGR5); /* UART, ROM */
|
||||
writel(0x00000F00, &ccm->CCGR6); /* SDHI4, EIM */
|
||||
}
|
||||
|
||||
static void vining2000_spl_dram_init(void)
|
||||
{
|
||||
struct mx6_ddr_sysinfo sysinfo = {
|
||||
.dsize = mem_ddr.width / 32,
|
||||
.cs_density = 24,
|
||||
.ncs = 1,
|
||||
.cs1_mirror = 0,
|
||||
.rtt_wr = 1, /* RTT_wr = RZQ/4 */
|
||||
.rtt_nom = 1, /* RTT_Nom = RZQ/4 */
|
||||
.walat = 1, /* Write additional latency */
|
||||
.ralat = 5, /* Read additional latency */
|
||||
.mif3_mode = 3, /* Command prediction working mode */
|
||||
.bi_on = 1, /* Bank interleaving enabled */
|
||||
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
|
||||
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
|
||||
.ddr_type = DDR_TYPE_DDR3,
|
||||
.refsel = 1, /* Refresh cycles at 32KHz */
|
||||
.refr = 7, /* 8 refresh commands per refresh cycle */
|
||||
};
|
||||
|
||||
mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
|
||||
mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
|
||||
|
||||
/* Perform DDR DRAM calibration */
|
||||
udelay(100);
|
||||
mmdc_do_write_level_calibration(&sysinfo);
|
||||
mmdc_do_dqs_calibration(&sysinfo);
|
||||
}
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
/* setup AIPS and disable watchdog */
|
||||
arch_cpu_init();
|
||||
|
||||
ccgr_init();
|
||||
|
||||
/* iomux setup */
|
||||
vining2000_spl_setup_iomux_pcie();
|
||||
vining2000_spl_setup_iomux_uart();
|
||||
|
||||
/* setup GP timer */
|
||||
timer_init();
|
||||
|
||||
/* reset the PCIe device */
|
||||
gpio_set_value(IMX_GPIO_NR(4, 6), 1);
|
||||
udelay(50);
|
||||
gpio_set_value(IMX_GPIO_NR(4, 6), 0);
|
||||
|
||||
/* UART clocks enabled and gd valid - init serial console */
|
||||
preloader_console_init();
|
||||
|
||||
/* DDR initialization */
|
||||
vining2000_spl_dram_init();
|
||||
|
||||
/* Clear the BSS. */
|
||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||
|
||||
/* load/boot image from boot device */
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
MX6CUBOXI BOARD
|
||||
M: Baruch Siach <baruch@tkos.co.il>
|
||||
M: Fabio Estevam <fabio.estevam@nxp.com>
|
||||
S: Maintained
|
||||
F: board/solidrun/mx6cuboxi/
|
||||
|
|
|
|||
|
|
@ -333,6 +333,43 @@ int checkboard(void)
|
|||
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
#if defined(CONFIG_IMX_BOOTAUX) && defined(CONFIG_ARCH_FIXUP_FDT_MEMORY)
|
||||
int up;
|
||||
|
||||
up = arch_auxiliary_core_check_up(0);
|
||||
if (up) {
|
||||
int ret;
|
||||
int areas = 1;
|
||||
u64 start[2], size[2];
|
||||
|
||||
/*
|
||||
* Reserve 1MB of memory for M4 (1MiB is also the minimum
|
||||
* alignment for Linux due to MMU section size restrictions).
|
||||
*/
|
||||
start[0] = gd->bd->bi_dram[0].start;
|
||||
size[0] = SZ_256M - SZ_1M;
|
||||
|
||||
/* If needed, create a second entry for memory beyond 256M */
|
||||
if (gd->bd->bi_dram[0].size > SZ_256M) {
|
||||
start[1] = gd->bd->bi_dram[0].start + SZ_256M;
|
||||
size[1] = gd->bd->bi_dram[0].size - SZ_256M;
|
||||
areas = 2;
|
||||
}
|
||||
|
||||
ret = fdt_set_usable_memory(blob, start, size, areas);
|
||||
if (ret) {
|
||||
eprintf("Cannot set usable memory\n");
|
||||
return ret;
|
||||
}
|
||||
} else {
|
||||
int off;
|
||||
|
||||
off = fdt_node_offset_by_compatible(blob, -1,
|
||||
"fsl,imx7d-rpmsg");
|
||||
if (off > 0)
|
||||
fdt_status_disabled(blob, off);
|
||||
}
|
||||
#endif
|
||||
#if defined(CONFIG_FDT_FIXUP_PARTITIONS)
|
||||
static const struct node_info nodes[] = {
|
||||
{ "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
|
||||
|
|
|
|||
|
|
@ -467,6 +467,41 @@ int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks)
|
|||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int fdt_set_usable_memory(void *blob, u64 start[], u64 size[], int areas)
|
||||
{
|
||||
int err, nodeoffset;
|
||||
int len;
|
||||
u8 tmp[8 * 16]; /* Up to 64-bit address + 64-bit size */
|
||||
|
||||
if (areas > 8) {
|
||||
printf("%s: num areas %d exceeds hardcoded limit %d\n",
|
||||
__func__, areas, 8);
|
||||
return -1;
|
||||
}
|
||||
|
||||
err = fdt_check_header(blob);
|
||||
if (err < 0) {
|
||||
printf("%s: %s\n", __func__, fdt_strerror(err));
|
||||
return err;
|
||||
}
|
||||
|
||||
/* find or create "/memory" node. */
|
||||
nodeoffset = fdt_find_or_add_subnode(blob, 0, "memory");
|
||||
if (nodeoffset < 0)
|
||||
return nodeoffset;
|
||||
|
||||
len = fdt_pack_reg(blob, tmp, start, size, areas);
|
||||
|
||||
err = fdt_setprop(blob, nodeoffset, "linux,usable-memory", tmp, len);
|
||||
if (err < 0) {
|
||||
printf("WARNING: could not set %s %s.\n",
|
||||
"reg", fdt_strerror(err));
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int fdt_fixup_memory(void *blob, u64 start, u64 size)
|
||||
|
|
|
|||
|
|
@ -1,18 +1,32 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_SYS_TEXT_BASE=0x87800000
|
||||
CONFIG_SPL_GPIO_SUPPORT=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x4000
|
||||
CONFIG_MX6_DDRCAL=y
|
||||
CONFIG_TARGET_SOFTING_VINING_2000=y
|
||||
CONFIG_SPL_MMC_SUPPORT=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_OFFSET=0x80000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SPL_LIBDISK_SUPPORT=y
|
||||
# CONFIG_CMD_BMODE is not set
|
||||
CONFIG_SPL_TEXT_BASE=0x00908000
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/softing/vining_2000/imximage.cfg"
|
||||
CONFIG_BOOTDELAY=0
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_SUPPORT_RAW_INITRD=y
|
||||
CONFIG_BOUNCE_BUFFER=y
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_SPL_FS_EXT4=y
|
||||
CONFIG_SPL_I2C_SUPPORT=y
|
||||
CONFIG_SPL_WATCHDOG_SUPPORT=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
|
|
@ -46,13 +60,15 @@ CONFIG_SUPPORT_EMMC_RPMB=y
|
|||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_FSL_USDHC=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_FEC_MXC=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX6=y
|
||||
CONFIG_PWM_IMX=y
|
||||
CONFIG_SPECIFY_CONSOLE_INDEX=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_USB=y
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ CONFIG_ARCH_MX7=y
|
|||
CONFIG_SYS_TEXT_BASE=0x87800000
|
||||
CONFIG_TARGET_WARP7=y
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_OFFSET=0x80000
|
||||
CONFIG_ENV_OFFSET=0xC0000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
|
||||
# CONFIG_ARMV7_VIRT is not set
|
||||
|
|
|
|||
|
|
@ -74,7 +74,7 @@ static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
|
|||
static const char *imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m",
|
||||
"sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", };
|
||||
|
||||
static const char *imx8mm_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m",
|
||||
static const char *imx8mm_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m",
|
||||
"sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", };
|
||||
|
||||
static const char *imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
|
||||
|
|
|
|||
|
|
@ -196,4 +196,9 @@
|
|||
#define CONFIG_FEC_XCV_TYPE RGMII
|
||||
#define FEC_QUIRK_ENET_MAC
|
||||
|
||||
/* Misc configuration */
|
||||
#define CONFIG_SYS_CBSIZE 2048
|
||||
#define CONFIG_SYS_MAXARGS 64
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
|
||||
#endif /* __IMX8QXP_MEK_H */
|
||||
|
|
|
|||
|
|
@ -58,8 +58,6 @@
|
|||
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
|
||||
|
||||
/* Network */
|
||||
#define CONFIG_FEC_MXC
|
||||
|
||||
#define IMX_FEC_BASE ENET_BASE_ADDR
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0x0
|
||||
|
||||
|
|
@ -91,4 +89,8 @@
|
|||
#define CONFIG_SYS_MMC_ENV_PART 1 /* boot0 */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_MXC_UART_BASE UART1_BASE
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
|
|||
|
|
@ -125,6 +125,19 @@
|
|||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
/*
|
||||
* Environment starts at CONFIG_ENV_OFFSET= 0xC0000 = 768k = 768*1024 = 786432
|
||||
*
|
||||
* Detect overlap between U-Boot image and environment area in build-time
|
||||
*
|
||||
* CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.imx offset
|
||||
* CONFIG_BOARD_SIZE_LIMIT = 768k - 1k = 767k = 785408
|
||||
*
|
||||
* Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so
|
||||
* write the direct value here
|
||||
*/
|
||||
#define CONFIG_BOARD_SIZE_LIMIT 785408
|
||||
|
||||
/* I2C configs */
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
|
|
|
|||
|
|
@ -94,6 +94,7 @@ int fdt_fixup_memory(void *blob, u64 start, u64 size);
|
|||
*/
|
||||
#ifdef CONFIG_ARCH_FIXUP_FDT_MEMORY
|
||||
int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks);
|
||||
int fdt_set_usable_memory(void *blob, u64 start[], u64 size[], int banks);
|
||||
#else
|
||||
static inline int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[],
|
||||
int banks)
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user