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mips: cache: Allow using CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CM

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This patch enables the usage of CONFIG_MIPS_L2_CACHE without
CONFIG_MIPS_CM, which is what is needed for the newly added Octeon
platform.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2020-05-14 11:59:03 +02:00 committed by Daniel Schwierzeck
parent c372813105
commit 2eed3dca22
2 changed files with 12 additions and 2 deletions
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12
arch/mips/include/asm/cm.h
View File

@ -41,6 +41,7 @@
#include <asm/io.h>
#include <linux/bitops.h>
#if CONFIG_IS_ENABLED(MIPS_CM)
static inline void *mips_cm_base(void)
{
return (void *)CKSEG1ADDR(CONFIG_MIPS_CM_BASE);
@ -56,6 +57,17 @@ static inline unsigned long mips_cm_l2_line_size(void)
line_sz &= GENMASK(GCR_L2_CONFIG_LINESZ_BITS - 1, 0);
return line_sz ? (2 << line_sz) : 0;
}
#else
static inline void *mips_cm_base(void)
{
return NULL;
}
static inline unsigned long mips_cm_l2_line_size(void)
{
return 0;
}
#endif
#endif /* !__ASSEMBLY__ */

2
arch/mips/lib/cache.c
View File

@ -8,9 +8,7 @@
#include <cpu_func.h>
#include <asm/cache.h>
#include <asm/cacheops.h>
#ifdef CONFIG_MIPS_L2_CACHE
#include <asm/cm.h>
#endif
#include <asm/io.h>
#include <asm/mipsregs.h>
#include <asm/system.h>