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Merge branch 'rmobile' of git://git.denx.de/u-boot-sh

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This commit is contained in:
Tom Rini 2017-10-10 20:14:38 -04:00
commit 2ee87b0c1a
35 changed files with 14028 additions and 1712 deletions
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342
arch/arm/dts/r8a7795-h3ulcb.dts
View File

@ -9,24 +9,16 @@
* kind, whether express or implied.
*/
#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
/dts-v1/;
#include "r8a7795.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "ulcb.dtsi"
/ {
model = "Renesas H3ULCB board based on r8a7795";
model = "Renesas H3ULCB board based on r8a7795 ES2.0+";
compatible = "renesas,h3ulcb", "renesas,r8a7795";
aliases {
serial0 = &scif2;
ethernet0 = &avb;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
@ -47,330 +39,4 @@
device_type = "memory";
reg = <0x7 0x00000000 0x0 0x40000000>;
};
leds {
compatible = "gpio-leds";
led5 {
gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
};
led6 {
gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
};
};
keyboard {
compatible = "gpio-keys";
key-1 {
linux,code = <KEY_1>;
label = "SW3";
wakeup-source;
debounce-interval = <20>;
gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
};
};
x12_clk: x12 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
};
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator1 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vcc_sdhi0: regulator-vcc-sdhi0 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
audio_clkout: audio-clkout {
/*
* This is same as <&rcar_sound 0>
* but needed to avoid cs2000/rcar_sound probe dead-lock
*/
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <11289600>;
};
rsnd_ak4613: sound {
compatible = "simple-audio-card";
simple-audio-card,format = "left_j";
simple-audio-card,bitclock-master = <&sndcpu>;
simple-audio-card,frame-master = <&sndcpu>;
sndcpu: simple-audio-card,cpu {
sound-dai = <&rcar_sound>;
};
sndcodec: simple-audio-card,codec {
sound-dai = <&ak4613>;
};
};
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
scif2_pins: scif2 {
groups = "scif2_data_a";
function = "scif2";
};
scif_clk_pins: scif_clk {
groups = "scif_clk_a";
function = "scif_clk";
};
i2c2_pins: i2c2 {
groups = "i2c2_a";
function = "i2c2";
};
avb_pins: avb {
groups = "avb_mdc";
function = "avb";
};
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
sdhi0_pins_uhs: sd0_uhs {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <1800>;
};
sdhi2_pins: sd2 {
groups = "sdhi2_data8", "sdhi2_ctrl";
function = "sdhi2";
power-source = <3300>;
};
sdhi2_pins_uhs: sd2_uhs {
groups = "sdhi2_data8", "sdhi2_ctrl";
function = "sdhi2";
power-source = <1800>;
};
sound_pins: sound {
groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
function = "ssi";
};
sound_clk_pins: sound-clk {
groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
"audio_clkout_a", "audio_clkout3_a";
function = "audio_clk";
};
usb1_pins: usb1 {
groups = "usb1";
function = "usb1";
};
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif_clk {
clock-frequency = <14745600>;
};
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <100000>;
ak4613: codec@10 {
compatible = "asahi-kasei,ak4613";
#sound-dai-cells = <0>;
reg = <0x10>;
clocks = <&rcar_sound 3>;
asahi-kasei,in1-single-end;
asahi-kasei,in2-single-end;
asahi-kasei,out1-single-end;
asahi-kasei,out2-single-end;
asahi-kasei,out3-single-end;
asahi-kasei,out4-single-end;
asahi-kasei,out5-single-end;
asahi-kasei,out6-single-end;
};
cs2000: clk-multiplier@4f {
#clock-cells = <0>;
compatible = "cirrus,cs2000-cp";
reg = <0x4f>;
clocks = <&audio_clkout>, <&x12_clk>;
clock-names = "clk_in", "ref_clk";
assigned-clocks = <&cs2000>;
assigned-clock-rates = <24576000>; /* 1/1 divide */
};
};
&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
#sound-dai-cells = <0>;
/* audio_clkout0/1/2/3 */
#clock-cells = <1>;
clock-frequency = <11289600>;
status = "okay";
/* update <audio_clk_b> to <cs2000> */
clocks = <&cpg CPG_MOD 1005>,
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&cs2000>,
<&audio_clk_c>,
<&cpg CPG_CORE R8A7795_CLK_S0D4>;
rcar_sound,dai {
dai0 {
playback = <&ssi0 &src0 &dvc0>;
capture = <&ssi1 &src1 &dvc1>;
};
};
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
sd-uhs-sdr50;
status = "okay";
};
&sdhi2 {
/* used for on-board 8bit eMMC */
pinctrl-0 = <&sdhi2_pins>;
pinctrl-1 = <&sdhi2_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
bus-width = <8>;
non-removable;
status = "okay";
};
&ssi1 {
shared-pin;
};
&wdt0 {
timeout-sec = <60>;
status = "okay";
};
&audio_clk_a {
clock-frequency = <22579200>;
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
status = "okay";
phy0: ethernet-phy@0 {
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
};
};
&usb2_phy1 {
pinctrl-0 = <&usb1_pins>;
pinctrl-names = "default";
status = "okay";
};
&ehci1 {
status = "okay";
};
&ohci1 {
status = "okay";
};

579
arch/arm/dts/r8a7795-salvator-x.dts
View File

@ -8,577 +8,108 @@
* kind, whether express or implied.
*/
/*
* SSI-AK4613
*
* This command is required when Playback/Capture
*
* amixer set "DVC Out" 100%
* amixer set "DVC In" 100%
*
* You can use Mute
*
* amixer set "DVC Out Mute" on
* amixer set "DVC In Mute" on
*
* You can use Volume Ramp
*
* amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
* amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
* amixer set "DVC Out Ramp" on
* aplay xxx.wav &
* amixer set "DVC Out" 80% // Volume Down
* amixer set "DVC Out" 100% // Volume Up
*/
#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
/dts-v1/;
#include "r8a7795.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include "salvator-x.dtsi"
/ {
model = "Renesas Salvator-X board based on r8a7795";
model = "Renesas Salvator-X board based on r8a7795 ES2.0+";
compatible = "renesas,salvator-x", "renesas,r8a7795";
aliases {
serial0 = &scif2;
serial1 = &scif1;
ethernet0 = &avb;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8";
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
x12_clk: x12 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
memory@500000000 {
device_type = "memory";
reg = <0x5 0x00000000 0x0 0x40000000>;
};
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
memory@600000000 {
device_type = "memory";
reg = <0x6 0x00000000 0x0 0x40000000>;
};
reg_3p3v: regulator1 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vcc_sdhi0: regulator-vcc-sdhi0 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
vcc_sdhi3: regulator-vcc-sdhi3 {
compatible = "regulator-fixed";
regulator-name = "SDHI3 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi3: regulator-vccq-sdhi3 {
compatible = "regulator-gpio";
regulator-name = "SDHI3 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
vbus0_usb2: regulator-vbus0-usb2 {
compatible = "regulator-fixed";
regulator-name = "USB20_VBUS0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
audio_clkout: audio_clkout {
/*
* This is same as <&rcar_sound 0>
* but needed to avoid cs2000/rcar_sound probe dead-lock
*/
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <11289600>;
};
rsnd_ak4613: sound {
compatible = "simple-audio-card";
simple-audio-card,format = "left_j";
simple-audio-card,bitclock-master = <&sndcpu>;
simple-audio-card,frame-master = <&sndcpu>;
sndcpu: simple-audio-card,cpu {
sound-dai = <&rcar_sound>;
};
sndcodec: simple-audio-card,codec {
sound-dai = <&ak4613>;
};
};
vga-encoder {
compatible = "adi,adv7123";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7123_in: endpoint {
remote-endpoint = <&du_out_rgb>;
};
};
port@1 {
reg = <1>;
adv7123_out: endpoint {
remote-endpoint = <&vga_in>;
};
};
};
};
vga {
compatible = "vga-connector";
port {
vga_in: endpoint {
remote-endpoint = <&adv7123_out>;
};
};
memory@700000000 {
device_type = "memory";
reg = <0x7 0x00000000 0x0 0x40000000>;
};
};
&du {
pinctrl-0 = <&du_pins>;
pinctrl-names = "default";
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 721>,
<&cpg CPG_MOD 727>,
<&versaclock5 1>,
<&x21_clk>,
<&x22_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
"dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
};
&ehci2 {
status = "okay";
};
&hdmi0 {
status = "okay";
ports {
port@0 {
endpoint {
remote-endpoint = <&adv7123_in>;
};
};
port@3 {
lvds_connector: endpoint {
port@1 {
reg = <1>;
rcar_dw_hdmi0_out: endpoint {
remote-endpoint = <&hdmi0_con>;
};
};
};
};
&extal_clk {
clock-frequency = <16666666>;
&hdmi0_con {
remote-endpoint = <&rcar_dw_hdmi0_out>;
};
&extalr_clk {
clock-frequency = <32768>;
&hdmi1 {
status = "okay";
ports {
port@1 {
reg = <1>;
rcar_dw_hdmi1_out: endpoint {
remote-endpoint = <&hdmi1_con>;
};
};
};
};
&hdmi1_con {
remote-endpoint = <&rcar_dw_hdmi1_out>;
};
&ohci2 {
status = "okay";
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
scif1_pins: scif1 {
groups = "scif1_data_a", "scif1_ctrl";
function = "scif1";
};
scif2_pins: scif2 {
groups = "scif2_data_a";
function = "scif2";
};
scif_clk_pins: scif_clk {
groups = "scif_clk_a";
function = "scif_clk";
};
i2c2_pins: i2c2 {
groups = "i2c2_a";
function = "i2c2";
};
avb_pins: avb {
mux {
groups = "avb_link", "avb_phy_int", "avb_mdc",
"avb_mii";
function = "avb";
};
pins_mdc {
groups = "avb_mdc";
drive-strength = <24>;
};
pins_mii_tx {
pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
"PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
drive-strength = <12>;
};
};
du_pins: du {
groups = "du_rgb888", "du_sync", "du_oddf", "du_clk_out_0";
function = "du";
};
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
sdhi0_pins_uhs: sd0_uhs {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <1800>;
};
sdhi2_pins: sd2 {
groups = "sdhi2_data8", "sdhi2_ctrl";
function = "sdhi2";
power-source = <3300>;
};
sdhi2_pins_uhs: sd2_uhs {
groups = "sdhi2_data8", "sdhi2_ctrl";
function = "sdhi2";
power-source = <1800>;
};
sdhi3_pins: sd3 {
groups = "sdhi3_data4", "sdhi3_ctrl";
function = "sdhi3";
power-source = <3300>;
};
sdhi3_pins_uhs: sd3_uhs {
groups = "sdhi3_data4", "sdhi3_ctrl";
function = "sdhi3";
power-source = <1800>;
};
sound_pins: sound {
groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
function = "ssi";
};
sound_clk_pins: sound_clk {
groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
"audio_clkout_a", "audio_clkout3_a";
function = "audio_clk";
};
usb0_pins: usb0 {
groups = "usb0";
function = "usb0";
};
usb1_pins: usb1 {
mux {
groups = "usb1";
function = "usb1";
};
ovc {
pins = "GP_6_27";
bias-pull-up;
};
pwen {
pins = "GP_6_26";
bias-pull-down;
};
};
usb2_pins: usb2 {
groups = "usb2";
function = "usb2";
};
};
&scif1 {
pinctrl-0 = <&scif1_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif_clk {
clock-frequency = <14745600>;
};
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <100000>;
ak4613: codec@10 {
compatible = "asahi-kasei,ak4613";
#sound-dai-cells = <0>;
reg = <0x10>;
clocks = <&rcar_sound 3>;
asahi-kasei,in1-single-end;
asahi-kasei,in2-single-end;
asahi-kasei,out1-single-end;
asahi-kasei,out2-single-end;
asahi-kasei,out3-single-end;
asahi-kasei,out4-single-end;
asahi-kasei,out5-single-end;
asahi-kasei,out6-single-end;
};
cs2000: clk_multiplier@4f {
#clock-cells = <0>;
compatible = "cirrus,cs2000-cp";
reg = <0x4f>;
clocks = <&audio_clkout>, <&x12_clk>;
clock-names = "clk_in", "ref_clk";
assigned-clocks = <&cs2000>;
assigned-clock-rates = <24576000>; /* 1/1 divide */
};
};
&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
#sound-dai-cells = <0>;
/* audio_clkout0/1/2/3 */
#clock-cells = <1>;
clock-frequency = <11289600>;
status = "okay";
/* update <audio_clk_b> to <cs2000> */
clocks = <&cpg CPG_MOD 1005>,
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&cs2000>,
<&audio_clk_c>,
<&cpg CPG_CORE R8A7795_CLK_S0D4>;
rcar_sound,dai {
dai0 {
playback = <&ssi0 &src0 &dvc0>;
capture = <&ssi1 &src1 &dvc1>;
};
};
};
&sata {
status = "okay";
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
sd-uhs-sdr50;
status = "okay";
};
&sdhi2 {
/* used for on-board 8bit eMMC */
pinctrl-0 = <&sdhi2_pins>;
pinctrl-1 = <&sdhi2_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
bus-width = <8>;
non-removable;
status = "okay";
};
&sdhi3 {
pinctrl-0 = <&sdhi3_pins>;
pinctrl-1 = <&sdhi3_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi3>;
vqmmc-supply = <&vccq_sdhi3>;
cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
sd-uhs-sdr50;
status = "okay";
};
&ssi1 {
shared-pin;
};
&wdt0 {
timeout-sec = <60>;
status = "okay";
};
&audio_clk_a {
clock-frequency = <22579200>;
};
&i2c_dvfs {
status = "okay";
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
status = "okay";
phy0: ethernet-phy@0 {
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
};
};
&xhci0 {
status = "okay";
};
&usb2_phy0 {
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";
vbus-supply = <&vbus0_usb2>;
status = "okay";
};
&usb2_phy1 {
pinctrl-0 = <&usb1_pins>;
pinctrl-names = "default";
status = "okay";
};
&usb2_phy2 {
pinctrl-0 = <&usb2_pins>;
pinctrl-names = "default";
status = "okay";
};
&ehci0 {
status = "okay";
};
&ehci1 {
status = "okay";
};
&ehci2 {
status = "okay";
};
&ohci0 {
status = "okay";
};
&ohci1 {
status = "okay";
};
&ohci2 {
status = "okay";
};
&hsusb {
status = "okay";
};
&pcie_bus_clk {
clock-frequency = <100000000>;
};
&pciec0 {
status = "okay";
};
&pciec1 {
status = "okay";
};

133
arch/arm/dts/r8a7795.dtsi
View File

@ -184,7 +184,7 @@
clock-frequency = <0>;
};
soc {
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
@ -402,7 +402,7 @@
#power-domain-cells = <1>;
};
pfc: pfc@e6060000 {
pfc: pin-controller@e6060000 {
compatible = "renesas,pfc-r8a7795";
reg = <0 0xe6060000 0 0x50c>;
};
@ -887,6 +887,8 @@
clocks = <&cpg CPG_MOD 926>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 926>;
dmas = <&dmac0 0x11>, <&dmac0 0x10>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1122,6 +1124,16 @@
"dvc.0", "dvc.1",
"clk_a", "clk_b", "clk_c", "clk_i";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 1005>,
<&cpg 1006>, <&cpg 1007>,
<&cpg 1008>, <&cpg 1009>,
<&cpg 1010>, <&cpg 1011>,
<&cpg 1012>, <&cpg 1013>,
<&cpg 1014>, <&cpg 1015>;
reset-names = "ssi-all",
"ssi.9", "ssi.8", "ssi.7", "ssi.6",
"ssi.5", "ssi.4", "ssi.3", "ssi.2",
"ssi.1", "ssi.0";
status = "disabled";
rcar_sound,dvc {
@ -1278,16 +1290,6 @@
status = "disabled";
};
xhci1: usb@ee0400000 {
compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci";
reg = <0 0xee040000 0 0xc00>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 327>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 327>;
status = "disabled";
};
usb_dmac0: dma-controller@e65a0000 {
compatible = "renesas,r8a7795-usb-dmac",
"renesas,usb-dmac";
@ -1572,14 +1574,6 @@
resets = <&cpg 614>;
};
fcpf2: fcp@fe952000 {
compatible = "renesas,fcpf";
reg = <0 0xfe952000 0 0x200>;
clocks = <&cpg CPG_MOD 613>;
power-domains = <&sysc R8A7795_PD_A3VP>;
resets = <&cpg 613>;
};
vspbd: vsp@fe960000 {
compatible = "renesas,vsp2";
reg = <0 0xfe960000 0 0x8000>;
@ -1637,25 +1631,6 @@
resets = <&cpg 610>;
};
vspi2: vsp@fe9c0000 {
compatible = "renesas,vsp2";
reg = <0 0xfe9c0000 0 0x8000>;
interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 629>;
power-domains = <&sysc R8A7795_PD_A3VP>;
resets = <&cpg 629>;
renesas,fcp = <&fcpvi2>;
};
fcpvi2: fcp@fe9cf000 {
compatible = "renesas,fcpv";
reg = <0 0xfe9cf000 0 0x200>;
clocks = <&cpg CPG_MOD 609>;
power-domains = <&sysc R8A7795_PD_A3VP>;
resets = <&cpg 609>;
};
vspd0: vsp@fea20000 {
compatible = "renesas,vsp2";
reg = <0 0xfea20000 0 0x4000>;
@ -1713,25 +1688,6 @@
resets = <&cpg 601>;
};
vspd3: vsp@fea38000 {
compatible = "renesas,vsp2";
reg = <0 0xfea38000 0 0x4000>;
interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 620>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 620>;
renesas,fcp = <&fcpvd3>;
};
fcpvd3: fcp@fea3f000 {
compatible = "renesas,fcpv";
reg = <0 0xfea3f000 0 0x200>;
clocks = <&cpg CPG_MOD 600>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 600>;
};
fdp1@fe940000 {
compatible = "renesas,fdp1";
reg = <0 0xfe940000 0 0x2400>;
@ -1752,18 +1708,57 @@
renesas,fcp = <&fcpf1>;
};
fdp1@fe948000 {
compatible = "renesas,fdp1";
reg = <0 0xfe948000 0 0x2400>;
interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 117>;
power-domains = <&sysc R8A7795_PD_A3VP>;
resets = <&cpg 117>;
renesas,fcp = <&fcpf2>;
hdmi0: hdmi0@fead0000 {
compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
reg = <0 0xfead0000 0 0x10000>;
interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7795_CLK_HDMI>;
clock-names = "iahb", "isfr";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 729>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dw_hdmi0_in: endpoint {
remote-endpoint = <&du_out_hdmi0>;
};
};
port@1 {
reg = <1>;
};
};
};
hdmi1: hdmi1@feae0000 {
compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
reg = <0 0xfeae0000 0 0x10000>;
interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 728>, <&cpg CPG_CORE R8A7795_CLK_HDMI>;
clock-names = "iahb", "isfr";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 728>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dw_hdmi1_in: endpoint {
remote-endpoint = <&du_out_hdmi1>;
};
};
port@1 {
reg = <1>;
};
};
};
du: display@feb00000 {
compatible = "renesas,du-r8a7795";
reg = <0 0xfeb00000 0 0x80000>,
<0 0xfeb90000 0 0x14>;
reg-names = "du", "lvds.0";
@ -1779,8 +1774,6 @@
clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";
status = "disabled";
vsps = <&vspd0 &vspd1 &vspd2 &vspd3>;
ports {
#address-cells = <1>;
#size-cells = <0>;
@ -1793,11 +1786,13 @@
port@1 {
reg = <1>;
du_out_hdmi0: endpoint {
remote-endpoint = <&dw_hdmi0_in>;
};
};
port@2 {
reg = <2>;
du_out_hdmi1: endpoint {
remote-endpoint = <&dw_hdmi1_in>;
};
};
port@3 {

168
arch/arm/dts/r8a7796-m3ulcb.dts
View File

@ -9,180 +9,24 @@
* kind, whether express or implied.
*/
#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4
/dts-v1/;
#include "r8a7796.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "ulcb.dtsi"
/ {
model = "Renesas M3ULCB board based on r8a7796";
compatible = "renesas,m3ulcb", "renesas,r8a7796";
aliases {
serial0 = &scif2;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
leds {
compatible = "gpio-leds";
led5 {
gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
};
led6 {
gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
};
};
keyboard {
compatible = "gpio-keys";
key-1 {
linux,code = <KEY_1>;
label = "SW3";
wakeup-source;
debounce-interval = <20>;
gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
};
};
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator1 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vcc_sdhi0: regulator-vcc-sdhi0 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
memory@600000000 {
device_type = "memory";
reg = <0x6 0x00000000 0x0 0x40000000>;
};
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
scif2_pins: scif2 {
groups = "scif2_data_a";
function = "scif2";
};
scif_clk_pins: scif_clk {
groups = "scif_clk_a";
function = "scif_clk";
};
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
sdhi0_pins_uhs: sd0_uhs {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <1800>;
};
sdhi2_pins: sd2 {
groups = "sdhi2_data8", "sdhi2_ctrl";
function = "sdhi2";
power-source = <3300>;
};
sdhi2_pins_uhs: sd2_uhs {
groups = "sdhi2_data8", "sdhi2_ctrl";
function = "sdhi2";
power-source = <1800>;
};
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
sd-uhs-sdr50;
status = "okay";
};
&sdhi2 {
/* used for on-board 8bit eMMC */
pinctrl-0 = <&sdhi2_pins>;
pinctrl-1 = <&sdhi2_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
bus-width = <8>;
non-removable;
status = "okay";
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif_clk {
clock-frequency = <14745600>;
};
&wdt0 {
timeout-sec = <60>;
status = "okay";
};

244
arch/arm/dts/r8a7796-salvator-x.dts
View File

@ -8,25 +8,16 @@
* kind, whether express or implied.
*/
#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4
/dts-v1/;
#include "r8a7796.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include "salvator-x.dtsi"
/ {
model = "Renesas Salvator-X board based on r8a7796";
compatible = "renesas,salvator-x", "renesas,r8a7796";
aliases {
serial0 = &scif2;
serial1 = &scif1;
ethernet0 = &avb;
};
chosen {
bootargs = "ignore_loglevel";
stdout-path = "serial0:115200n8";
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
@ -37,233 +28,4 @@
device_type = "memory";
reg = <0x6 0x00000000 0x0 0x80000000>;
};
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator1 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vcc_sdhi0: regulator-vcc-sdhi0 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
vcc_sdhi3: regulator-vcc-sdhi3 {
compatible = "regulator-fixed";
regulator-name = "SDHI3 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi3: regulator-vccq-sdhi3 {
compatible = "regulator-gpio";
regulator-name = "SDHI3 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
avb_pins: avb {
groups = "avb_mdc";
function = "avb";
};
scif1_pins: scif1 {
groups = "scif1_data_a", "scif1_ctrl";
function = "scif1";
};
scif2_pins: scif2 {
groups = "scif2_data_a";
function = "scif2";
};
scif_clk_pins: scif_clk {
groups = "scif_clk_a";
function = "scif_clk";
};
i2c2_pins: i2c2 {
groups = "i2c2_a";
function = "i2c2";
};
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
sdhi0_pins_uhs: sd0_uhs {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <1800>;
};
sdhi2_pins: sd2 {
groups = "sdhi2_data8", "sdhi2_ctrl";
function = "sdhi2";
power-source = <3300>;
};
sdhi2_pins_uhs: sd2_uhs {
groups = "sdhi2_data8", "sdhi2_ctrl";
function = "sdhi2";
power-source = <1800>;
};
sdhi3_pins: sd3 {
groups = "sdhi3_data4", "sdhi3_ctrl";
function = "sdhi3";
power-source = <3300>;
};
sdhi3_pins_uhs: sd3_uhs {
groups = "sdhi3_data4", "sdhi3_ctrl";
function = "sdhi3";
power-source = <1800>;
};
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
status = "okay";
phy0: ethernet-phy@0 {
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
};
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
sd-uhs-sdr50;
status = "okay";
};
&sdhi2 {
/* used for on-board 8bit eMMC */
pinctrl-0 = <&sdhi2_pins>;
pinctrl-1 = <&sdhi2_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
bus-width = <8>;
non-removable;
status = "okay";
};
&sdhi3 {
pinctrl-0 = <&sdhi3_pins>;
pinctrl-1 = <&sdhi3_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi3>;
vqmmc-supply = <&vccq_sdhi3>;
cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
sd-uhs-sdr50;
status = "okay";
};
&scif1 {
pinctrl-0 = <&scif1_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif_clk {
clock-frequency = <14745600>;
};
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
status = "okay";
};
&wdt0 {
timeout-sec = <60>;
status = "okay";
};
&i2c_dvfs {
status = "okay";
};

468
arch/arm/dts/r8a7796.dtsi
View File

@ -122,6 +122,29 @@
u-boot,dm-pre-reloc;
};
/*
* The external audio clocks are configured as 0 Hz fixed frequency
* clocks by default.
* Boards that provide audio clocks should override them.
*/
audio_clk_a: audio_clk_a {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
audio_clk_b: audio_clk_b {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
audio_clk_c: audio_clk_c {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
compatible = "fixed-clock";
@ -136,6 +159,13 @@
clock-frequency = <0>;
};
/* External PCIe clock - can be overridden by the board */
pcie_bus_clk: pcie_bus {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
@ -366,6 +396,78 @@
clocks = <&cpg CPG_MOD 926>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 926>;
dmas = <&dmac0 0x11>, <&dmac0 0x10>;
dma-names = "tx", "rx";
status = "disabled";
};
pwm0: pwm@e6e30000 {
compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
reg = <0 0xe6e30000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
pwm1: pwm@e6e31000 {
compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
reg = <0 0xe6e31000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
pwm2: pwm@e6e32000 {
compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
reg = <0 0xe6e32000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
pwm3: pwm@e6e33000 {
compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
reg = <0 0xe6e33000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
pwm4: pwm@e6e34000 {
compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
reg = <0 0xe6e34000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
pwm5: pwm@e6e35000 {
compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
reg = <0 0xe6e35000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
pwm6: pwm@e6e36000 {
compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
reg = <0 0xe6e36000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
@ -935,6 +1037,153 @@
dma-channels = <16>;
};
audma0: dma-controller@ec700000 {
compatible = "renesas,dmac-r8a7796",
"renesas,rcar-dmac";
reg = <0 0xec700000 0 0x10000>;
interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 502>;
clock-names = "fck";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 502>;
#dma-cells = <1>;
dma-channels = <16>;
};
audma1: dma-controller@ec720000 {
compatible = "renesas,dmac-r8a7796",
"renesas,rcar-dmac";
reg = <0 0xec720000 0 0x10000>;
interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 501>;
clock-names = "fck";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 501>;
#dma-cells = <1>;
dma-channels = <16>;
};
hsusb: usb@e6590000 {
compatible = "renesas,usbhs-r8a7796",
"renesas,rcar-gen3-usbhs";
reg = <0 0xe6590000 0 0x100>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 704>;
renesas,buswait = <11>;
phys = <&usb2_phy0>;
phy-names = "usb";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 704>;
status = "disabled";
};
xhci0: usb@ee000000 {
compatible = "renesas,xhci-r8a7796", "renesas,rcar-gen3-xhci";
reg = <0 0xee000000 0 0xc00>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 328>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 328>;
status = "disabled";
};
ohci0: usb@ee080000 {
/* placeholder */
};
ehci0: usb@ee080100 {
compatible = "generic-ehci";
reg = <0 0xee080100 0 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>;
phys = <&usb2_phy0>;
phy-names = "usb";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 703>;
status = "disabled";
};
usb2_phy0: usb-phy@ee080200 {
compatible = "renesas,usb2-phy-r8a7796",
"renesas,rcar-gen3-usb2-phy";
reg = <0 0xee080200 0 0x700>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 703>;
#phy-cells = <0>;
status = "disabled";
};
ohci1: usb@ee0a0000 {
/* placeholder */
};
ehci1: usb@ee0a0100 {
compatible = "generic-ehci";
reg = <0 0xee0a0100 0 0x100>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 702>;
phys = <&usb2_phy1>;
phy-names = "usb";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 702>;
status = "disabled";
};
usb2_phy1: usb-phy@ee0a0200 {
compatible = "renesas,usb2-phy-r8a7796",
"renesas,rcar-gen3-usb2-phy";
reg = <0 0xee0a0200 0 0x700>;
clocks = <&cpg CPG_MOD 702>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 702>;
#phy-cells = <0>;
status = "disabled";
};
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a7796";
reg = <0 0xee100000 0 0x2000>;
@ -1037,5 +1286,224 @@
};
};
};
rcar_sound: sound@ec500000 {
/*
* #sound-dai-cells is required
*
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
*/
/*
* #clock-cells is required for audio_clkout0/1/2/3
*
* clkout : #clock-cells = <0>; <&rcar_sound>;
* clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
*/
compatible = "renesas,rcar_sound-r8a7796", "renesas,rcar_sound-gen3";
reg = <0 0xec500000 0 0x1000>, /* SCU */
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>, /* SSI */
<0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
clocks = <&cpg CPG_MOD 1005>,
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&audio_clk_b>,
<&audio_clk_c>,
<&cpg CPG_CORE R8A7796_CLK_S0D4>;
clock-names = "ssi-all",
"ssi.9", "ssi.8", "ssi.7", "ssi.6",
"ssi.5", "ssi.4", "ssi.3", "ssi.2",
"ssi.1", "ssi.0",
"src.9", "src.8", "src.7", "src.6",
"src.5", "src.4", "src.3", "src.2",
"src.1", "src.0",
"mix.1", "mix.0",
"ctu.1", "ctu.0",
"dvc.0", "dvc.1",
"clk_a", "clk_b", "clk_c", "clk_i";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 1005>,
<&cpg 1006>, <&cpg 1007>,
<&cpg 1008>, <&cpg 1009>,
<&cpg 1010>, <&cpg 1011>,
<&cpg 1012>, <&cpg 1013>,
<&cpg 1014>, <&cpg 1015>;
reset-names = "ssi-all",
"ssi.9", "ssi.8", "ssi.7", "ssi.6",
"ssi.5", "ssi.4", "ssi.3", "ssi.2",
"ssi.1", "ssi.0";
status = "disabled";
rcar_sound,dvc {
dvc0: dvc-0 {
dmas = <&audma1 0xbc>;
dma-names = "tx";
};
dvc1: dvc-1 {
dmas = <&audma1 0xbe>;
dma-names = "tx";
};
};
rcar_sound,mix {
mix0: mix-0 { };
mix1: mix-1 { };
};
rcar_sound,ctu {
ctu00: ctu-0 { };
ctu01: ctu-1 { };
ctu02: ctu-2 { };
ctu03: ctu-3 { };
ctu10: ctu-4 { };
ctu11: ctu-5 { };
ctu12: ctu-6 { };
ctu13: ctu-7 { };
};
rcar_sound,src {
src0: src-0 {
interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x85>, <&audma1 0x9a>;
dma-names = "rx", "tx";
};
src1: src-1 {
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x87>, <&audma1 0x9c>;
dma-names = "rx", "tx";
};
src2: src-2 {
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x89>, <&audma1 0x9e>;
dma-names = "rx", "tx";
};
src3: src-3 {
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x8b>, <&audma1 0xa0>;
dma-names = "rx", "tx";
};
src4: src-4 {
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x8d>, <&audma1 0xb0>;
dma-names = "rx", "tx";
};
src5: src-5 {
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x8f>, <&audma1 0xb2>;
dma-names = "rx", "tx";
};
src6: src-6 {
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x91>, <&audma1 0xb4>;
dma-names = "rx", "tx";
};
src7: src-7 {
interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x93>, <&audma1 0xb6>;
dma-names = "rx", "tx";
};
src8: src-8 {
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x95>, <&audma1 0xb8>;
dma-names = "rx", "tx";
};
src9: src-9 {
interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x97>, <&audma1 0xba>;
dma-names = "rx", "tx";
};
};
rcar_sound,ssi {
ssi0: ssi-0 {
interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi1: ssi-1 {
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi2: ssi-2 {
interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi3: ssi-3 {
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi4: ssi-4 {
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi5: ssi-5 {
interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi6: ssi-6 {
interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi7: ssi-7 {
interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi8: ssi-8 {
interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi9: ssi-9 {
interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
dma-names = "rx", "tx", "rxu", "txu";
};
};
};
pciec0: pcie@fe000000 {
/* placeholder */
};
pciec1: pcie@ee800000 {
/* placeholder */
};
du: display@feb00000 {
/* placeholder */
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
du_out_rgb: endpoint {
};
};
};
};
};
};

639
arch/arm/dts/salvator-common.dtsi Normal file
View File

@ -0,0 +1,639 @@
/*
* Device Tree Source for common parts of Salvator-X board variants
*
* Copyright (C) 2015-2016 Renesas Electronics Corp.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/*
* SSI-AK4613
*
* This command is required when Playback/Capture
*
* amixer set "DVC Out" 100%
* amixer set "DVC In" 100%
*
* You can use Mute
*
* amixer set "DVC Out Mute" on
* amixer set "DVC In Mute" on
*
* You can use Volume Ramp
*
* amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
* amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
* amixer set "DVC Out Ramp" on
* aplay xxx.wav &
* amixer set "DVC Out" 80% // Volume Down
* amixer set "DVC Out" 100% // Volume Up
*/
#include <dt-bindings/gpio/gpio.h>
/ {
aliases {
serial0 = &scif2;
serial1 = &scif1;
ethernet0 = &avb;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8";
};
audio_clkout: audio-clkout {
/*
* This is same as <&rcar_sound 0>
* but needed to avoid cs2000/rcar_sound probe dead-lock
*/
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <11289600>;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 50000>;
brightness-levels = <256 128 64 16 8 4 0>;
default-brightness-level = <6>;
enable-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
};
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator1 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
rsnd_ak4613: sound {
compatible = "simple-audio-card";
simple-audio-card,format = "left_j";
simple-audio-card,bitclock-master = <&sndcpu>;
simple-audio-card,frame-master = <&sndcpu>;
sndcpu: simple-audio-card,cpu {
sound-dai = <&rcar_sound>;
};
sndcodec: simple-audio-card,codec {
sound-dai = <&ak4613>;
};
};
vbus0_usb2: regulator-vbus0-usb2 {
compatible = "regulator-fixed";
regulator-name = "USB20_VBUS0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vcc_sdhi0: regulator-vcc-sdhi0 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
vcc_sdhi3: regulator-vcc-sdhi3 {
compatible = "regulator-fixed";
regulator-name = "SDHI3 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi3: regulator-vccq-sdhi3 {
compatible = "regulator-gpio";
regulator-name = "SDHI3 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
hdmi0-out {
compatible = "hdmi-connector";
label = "HDMI0 OUT";
type = "a";
port {
hdmi0_con: endpoint {
};
};
};
hdmi1-out {
compatible = "hdmi-connector";
label = "HDMI1 OUT";
type = "a";
port {
hdmi1_con: endpoint {
};
};
};
vga {
compatible = "vga-connector";
port {
vga_in: endpoint {
remote-endpoint = <&adv7123_out>;
};
};
};
vga-encoder {
compatible = "adi,adv7123";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7123_in: endpoint {
remote-endpoint = <&du_out_rgb>;
};
};
port@1 {
reg = <1>;
adv7123_out: endpoint {
remote-endpoint = <&vga_in>;
};
};
};
};
x12_clk: x12 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
};
/* External DU dot clocks */
x21_clk: x21-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <33000000>;
};
x22_clk: x22-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <33000000>;
};
x23_clk: x23-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
};
&audio_clk_a {
clock-frequency = <22579200>;
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
status = "okay";
phy0: ethernet-phy@0 {
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
};
};
&du {
pinctrl-0 = <&du_pins>;
pinctrl-names = "default";
status = "okay";
ports {
port@0 {
endpoint {
remote-endpoint = <&adv7123_in>;
};
};
port@3 {
lvds_connector: endpoint {
};
};
};
};
&ehci0 {
status = "okay";
};
&ehci1 {
status = "okay";
};
&extalr_clk {
clock-frequency = <32768>;
};
&hsusb {
status = "okay";
};
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <100000>;
ak4613: codec@10 {
compatible = "asahi-kasei,ak4613";
#sound-dai-cells = <0>;
reg = <0x10>;
clocks = <&rcar_sound 3>;
asahi-kasei,in1-single-end;
asahi-kasei,in2-single-end;
asahi-kasei,out1-single-end;
asahi-kasei,out2-single-end;
asahi-kasei,out3-single-end;
asahi-kasei,out4-single-end;
asahi-kasei,out5-single-end;
asahi-kasei,out6-single-end;
};
cs2000: clk_multiplier@4f {
#clock-cells = <0>;
compatible = "cirrus,cs2000-cp";
reg = <0x4f>;
clocks = <&audio_clkout>, <&x12_clk>;
clock-names = "clk_in", "ref_clk";
assigned-clocks = <&cs2000>;
assigned-clock-rates = <24576000>; /* 1/1 divide */
};
};
&i2c4 {
status = "okay";
csa_vdd: adc@7c {
compatible = "maxim,max9611";
reg = <0x7c>;
shunt-resistor-micro-ohms = <5000>;
};
csa_dvfs: adc@7f {
compatible = "maxim,max9611";
reg = <0x7f>;
shunt-resistor-micro-ohms = <5000>;
};
};
&i2c_dvfs {
status = "okay";
};
&ohci0 {
status = "okay";
};
&ohci1 {
status = "okay";
};
&pcie_bus_clk {
clock-frequency = <100000000>;
};
&pciec0 {
status = "okay";
};
&pciec1 {
status = "okay";
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
avb_pins: avb {
mux {
groups = "avb_link", "avb_phy_int", "avb_mdc",
"avb_mii";
function = "avb";
};
pins_mdc {
groups = "avb_mdc";
drive-strength = <24>;
};
pins_mii_tx {
pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
"PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
drive-strength = <12>;
};
};
du_pins: du {
groups = "du_rgb888", "du_sync", "du_oddf", "du_clk_out_0";
function = "du";
};
i2c2_pins: i2c2 {
groups = "i2c2_a";
function = "i2c2";
};
pwm1_pins: pwm1 {
groups = "pwm1_a";
function = "pwm1";
};
scif1_pins: scif1 {
groups = "scif1_data_a", "scif1_ctrl";
function = "scif1";
};
scif2_pins: scif2 {
groups = "scif2_data_a";
function = "scif2";
};
scif_clk_pins: scif_clk {
groups = "scif_clk_a";
function = "scif_clk";
};
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
sdhi0_pins_uhs: sd0_uhs {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <1800>;
};
sdhi2_pins: sd2 {
groups = "sdhi2_data8", "sdhi2_ctrl";
function = "sdhi2";
power-source = <3300>;
};
sdhi2_pins_uhs: sd2_uhs {
groups = "sdhi2_data8", "sdhi2_ctrl";
function = "sdhi2";
power-source = <1800>;
};
sdhi3_pins: sd3 {
groups = "sdhi3_data4", "sdhi3_ctrl";
function = "sdhi3";
power-source = <3300>;
};
sdhi3_pins_uhs: sd3_uhs {
groups = "sdhi3_data4", "sdhi3_ctrl";
function = "sdhi3";
power-source = <1800>;
};
sound_pins: sound {
groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
function = "ssi";
};
sound_clk_pins: sound_clk {
groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
"audio_clkout_a", "audio_clkout3_a";
function = "audio_clk";
};
usb0_pins: usb0 {
groups = "usb0";
function = "usb0";
};
usb1_pins: usb1 {
mux {
groups = "usb1";
function = "usb1";
};
ovc {
pins = "GP_6_27";
bias-pull-up;
};
pwen {
pins = "GP_6_26";
bias-pull-down;
};
};
};
&pwm1 {
pinctrl-0 = <&pwm1_pins>;
pinctrl-names = "default";
status = "okay";
};
&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
#sound-dai-cells = <0>;
/* audio_clkout0/1/2/3 */
#clock-cells = <1>;
clock-frequency = <12288000 11289600>;
status = "okay";
/* update <audio_clk_b> to <cs2000> */
clocks = <&cpg CPG_MOD 1005>,
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&cs2000>,
<&audio_clk_c>,
<&cpg CPG_CORE CPG_AUDIO_CLK_I>;
rcar_sound,dai {
dai0 {
playback = <&ssi0 &src0 &dvc0>;
capture = <&ssi1 &src1 &dvc1>;
};
};
};
&scif1 {
pinctrl-0 = <&scif1_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif_clk {
clock-frequency = <14745600>;
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
max-frequency = <208000000>;
};
&sdhi2 {
/* used for on-board 8bit eMMC */
pinctrl-0 = <&sdhi2_pins>;
pinctrl-1 = <&sdhi2_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
non-removable;
status = "okay";
max-frequency = <200000000>;
};
&sdhi3 {
pinctrl-0 = <&sdhi3_pins>;
pinctrl-1 = <&sdhi3_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi3>;
vqmmc-supply = <&vccq_sdhi3>;
cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
max-frequency = <208000000>;
};
&ssi1 {
shared-pin;
};
&usb2_phy0 {
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";
vbus-supply = <&vbus0_usb2>;
status = "okay";
};
&usb2_phy1 {
pinctrl-0 = <&usb1_pins>;
pinctrl-names = "default";
status = "okay";
};
&wdt0 {
timeout-sec = <60>;
status = "okay";
};
&xhci0 {
status = "okay";
};

30
arch/arm/dts/salvator-x.dtsi Normal file
View File

@ -0,0 +1,30 @@
/*
* Device Tree Source for the Salvator-X board
*
* Copyright (C) 2015-2016 Renesas Electronics Corp.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include "salvator-common.dtsi"
/ {
model = "Renesas Salvator-X board";
compatible = "renesas,salvator-x";
};
&extal_clk {
clock-frequency = <16666666>;
};
&i2c4 {
versaclock5: clock-generator@6a {
compatible = "idt,5p49v5923";
reg = <0x6a>;
#clock-cells = <1>;
clocks = <&x23_clk>;
clock-names = "xin";
};
};

368
arch/arm/dts/ulcb.dtsi Normal file
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@ -0,0 +1,368 @@
/*
* Device Tree Source for the R-Car Gen3 ULCB board
*
* Copyright (C) 2016 Renesas Electronics Corp.
* Copyright (C) 2016 Cogent Embedded, Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Renesas R-Car Gen3 ULCB board";
aliases {
serial0 = &scif2;
ethernet0 = &avb;
};
chosen {
stdout-path = "serial0:115200n8";
};
audio_clkout: audio-clkout {
/*
* This is same as <&rcar_sound 0>
* but needed to avoid cs2000/rcar_sound probe dead-lock
*/
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <11289600>;
};
keyboard {
compatible = "gpio-keys";
key-1 {
linux,code = <KEY_1>;
label = "SW3";
wakeup-source;
debounce-interval = <20>;
gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
};
};
leds {
compatible = "gpio-leds";
led5 {
gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
};
led6 {
gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
};
};
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator1 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
rsnd_ak4613: sound {
compatible = "simple-audio-card";
simple-audio-card,format = "left_j";
simple-audio-card,bitclock-master = <&sndcpu>;
simple-audio-card,frame-master = <&sndcpu>;
sndcpu: simple-audio-card,cpu {
sound-dai = <&rcar_sound>;
};
sndcodec: simple-audio-card,codec {
sound-dai = <&ak4613>;
};
};
vcc_sdhi0: regulator-vcc-sdhi0 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
x12_clk: x12 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
};
};
&audio_clk_a {
clock-frequency = <22579200>;
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
status = "okay";
phy0: ethernet-phy@0 {
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
};
};
&ehci1 {
status = "okay";
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <100000>;
ak4613: codec@10 {
compatible = "asahi-kasei,ak4613";
#sound-dai-cells = <0>;
reg = <0x10>;
clocks = <&rcar_sound 3>;
asahi-kasei,in1-single-end;
asahi-kasei,in2-single-end;
asahi-kasei,out1-single-end;
asahi-kasei,out2-single-end;
asahi-kasei,out3-single-end;
asahi-kasei,out4-single-end;
asahi-kasei,out5-single-end;
asahi-kasei,out6-single-end;
};
cs2000: clk-multiplier@4f {
#clock-cells = <0>;
compatible = "cirrus,cs2000-cp";
reg = <0x4f>;
clocks = <&audio_clkout>, <&x12_clk>;
clock-names = "clk_in", "ref_clk";
assigned-clocks = <&cs2000>;
assigned-clock-rates = <24576000>; /* 1/1 divide */
};
};
&ohci1 {
status = "okay";
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
avb_pins: avb {
mux {
groups = "avb_link", "avb_phy_int", "avb_mdc",
"avb_mii";
function = "avb";
};
pins_mdc {
groups = "avb_mdc";
drive-strength = <24>;
};
pins_mii_tx {
pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
"PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
drive-strength = <12>;
};
};
i2c2_pins: i2c2 {
groups = "i2c2_a";
function = "i2c2";
};
scif2_pins: scif2 {
groups = "scif2_data_a";
function = "scif2";
};
scif_clk_pins: scif_clk {
groups = "scif_clk_a";
function = "scif_clk";
};
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
sdhi0_pins_uhs: sd0_uhs {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <1800>;
};
sdhi2_pins: sd2 {
groups = "sdhi2_data8", "sdhi2_ctrl";
function = "sdhi2";
power-source = <3300>;
};
sdhi2_pins_uhs: sd2_uhs {
groups = "sdhi2_data8", "sdhi2_ctrl";
function = "sdhi2";
power-source = <1800>;
};
sound_pins: sound {
groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
function = "ssi";
};
sound_clk_pins: sound-clk {
groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
"audio_clkout_a", "audio_clkout3_a";
function = "audio_clk";
};
usb1_pins: usb1 {
groups = "usb1";
function = "usb1";
};
};
&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
#sound-dai-cells = <0>;
/* audio_clkout0/1/2/3 */
#clock-cells = <1>;
clock-frequency = <12288000 11289600>;
status = "okay";
/* update <audio_clk_b> to <cs2000> */
clocks = <&cpg CPG_MOD 1005>,
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&cs2000>,
<&audio_clk_c>,
<&cpg CPG_CORE CPG_AUDIO_CLK_I>;
rcar_sound,dai {
dai0 {
playback = <&ssi0 &src0 &dvc0>;
capture = <&ssi1 &src1 &dvc1>;
};
};
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif_clk {
clock-frequency = <14745600>;
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
sd-uhs-sdr50;
status = "okay";
};
&sdhi2 {
/* used for on-board 8bit eMMC */
pinctrl-0 = <&sdhi2_pins>;
pinctrl-1 = <&sdhi2_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
bus-width = <8>;
mmc-hs200-1_8v;
non-removable;
status = "okay";
};
&ssi1 {
shared-pin;
};
&usb2_phy1 {
pinctrl-0 = <&usb1_pins>;
pinctrl-names = "default";
status = "okay";
};
&wdt0 {
timeout-sec = <60>;
status = "okay";
};

152
board/renesas/salvator-x/salvator-x.c
View File

@ -49,35 +49,13 @@ void s_init(void)
#define TMU0_MSTP125 BIT(25) /* secure */
#define TMU1_MSTP124 BIT(24) /* non-secure */
#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
#define ETHERAVB_MSTP812 BIT(12)
#define DVFS_MSTP926 BIT(26)
#define SD0_MSTP314 BIT(14)
#define SD1_MSTP313 BIT(13)
#define SD2_MSTP312 BIT(12) /* either MMC0 */
#define SD3_MSTP311 BIT(11) /* either MMC1 */
#define SD0CKCR 0xE6150074
#define SD1CKCR 0xE6150078
#define SD2CKCR 0xE6150268
#define SD3CKCR 0xE615026C
#define HSUSB_MSTP704 BIT(4) /* HSUSB */
int board_early_init_f(void)
{
/* TMU0,1 */ /* which use ? */
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
/* SCIF2 */
mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310);
/* EHTERAVB */
mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHERAVB_MSTP812);
/* eMMC */
mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD1_MSTP313 | SD2_MSTP312);
/* SDHI0, 3 */
mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314 | SD3_MSTP311);
writel(1, SD0CKCR);
writel(1, SD1CKCR);
writel(1, SD2CKCR);
writel(1, SD3CKCR);
#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
/* DVFS for reset */
@ -92,18 +70,18 @@ int board_early_init_f(void)
/* -/W 32 Power resume control register 2 (3DG) */
#define SYSC_PWRONCR2 0xE618010C
/* HSUSB block registers */
#define HSUSB_REG_LPSTS 0xE6590102
#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
#define HSUSB_REG_UGCTRL2 0xE6590184
#define HSUSB_REG_UGCTRL2_USB0SEL 0x30
#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
/* Init PFC controller */
#if defined(CONFIG_R8A7795)
r8a7795_pinmux_init();
#elif defined(CONFIG_R8A7796)
r8a7796_pinmux_init();
#endif
#if defined(CONFIG_R8A7795)
/* GSX: force power and clock supply */
writel(0x0000001F, SYSC_PWRONCR2);
@ -116,113 +94,13 @@ int board_init(void)
/* USB1 pull-up */
setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
#ifdef CONFIG_RENESAS_RAVB
/* EtherAVB Enable */
/* GPSR2 */
gpio_request(GPIO_GFN_AVB_AVTP_CAPTURE_A, NULL);
gpio_request(GPIO_GFN_AVB_AVTP_MATCH_A, NULL);
gpio_request(GPIO_GFN_AVB_LINK, NULL);
gpio_request(GPIO_GFN_AVB_PHY_INT, NULL);
gpio_request(GPIO_GFN_AVB_MAGIC, NULL);
gpio_request(GPIO_GFN_AVB_MDC, NULL);
/* IPSR0 */
gpio_request(GPIO_IFN_AVB_MDC, NULL);
gpio_request(GPIO_IFN_AVB_MAGIC, NULL);
gpio_request(GPIO_IFN_AVB_PHY_INT, NULL);
gpio_request(GPIO_IFN_AVB_LINK, NULL);
gpio_request(GPIO_IFN_AVB_AVTP_MATCH_A, NULL);
gpio_request(GPIO_IFN_AVB_AVTP_CAPTURE_A, NULL);
/* IPSR1 */
gpio_request(GPIO_FN_AVB_AVTP_PPS, NULL);
/* IPSR2 */
gpio_request(GPIO_FN_AVB_AVTP_MATCH_B, NULL);
/* IPSR3 */
gpio_request(GPIO_FN_AVB_AVTP_CAPTURE_B, NULL);
#if defined(CONFIG_R8A7795)
/* USB2_OVC */
gpio_request(GPIO_GP_6_15, NULL);
gpio_direction_input(GPIO_GP_6_15);
/* USB2_PWEN */
gpio_request(GPIO_GP_6_14, NULL);
gpio_direction_output(GPIO_GP_6_14, 1);
gpio_set_value(GPIO_GP_6_14, 1);
#endif
/* AVB_PHY_RST */
gpio_request(GPIO_GP_2_10, NULL);
gpio_direction_output(GPIO_GP_2_10, 0);
mdelay(20);
gpio_set_value(GPIO_GP_2_10, 1);
udelay(1);
#endif
#ifdef CONFIG_MMC
/* SDHI0 */
gpio_request(GPIO_GFN_SD0_DAT0, NULL);
gpio_request(GPIO_GFN_SD0_DAT1, NULL);
gpio_request(GPIO_GFN_SD0_DAT2, NULL);
gpio_request(GPIO_GFN_SD0_DAT3, NULL);
gpio_request(GPIO_GFN_SD0_CLK, NULL);
gpio_request(GPIO_GFN_SD0_CMD, NULL);
gpio_request(GPIO_GFN_SD0_CD, NULL);
gpio_request(GPIO_GFN_SD0_WP, NULL);
gpio_request(GPIO_GP_5_2, NULL);
gpio_request(GPIO_GP_5_1, NULL);
gpio_direction_output(GPIO_GP_5_2, 1); /* power on */
gpio_direction_output(GPIO_GP_5_1, 1); /* 1: 3.3V, 0: 1.8V */
/* SDHI1/SDHI2 eMMC */
gpio_request(GPIO_GFN_SD1_DAT0, NULL);
gpio_request(GPIO_GFN_SD1_DAT1, NULL);
gpio_request(GPIO_GFN_SD1_DAT2, NULL);
gpio_request(GPIO_GFN_SD1_DAT3, NULL);
gpio_request(GPIO_GFN_SD2_DAT0, NULL);
gpio_request(GPIO_GFN_SD2_DAT1, NULL);
gpio_request(GPIO_GFN_SD2_DAT2, NULL);
gpio_request(GPIO_GFN_SD2_DAT3, NULL);
gpio_request(GPIO_GFN_SD2_CLK, NULL);
#if defined(CONFIG_R8A7795)
gpio_request(GPIO_GFN_SD2_CMD, NULL);
#elif defined(CONFIG_R8A7796)
gpio_request(GPIO_FN_SD2_CMD, NULL);
#else
#error Only R8A7795 and R87796 is supported
#endif
gpio_request(GPIO_GP_5_3, NULL);
gpio_request(GPIO_GP_5_9, NULL);
gpio_direction_output(GPIO_GP_5_3, 0); /* 1: 3.3V, 0: 1.8V */
gpio_direction_output(GPIO_GP_5_9, 0); /* 1: 3.3V, 0: 1.8V */
#if defined(CONFIG_R8A7795)
/* SDHI3 */
gpio_request(GPIO_GFN_SD3_DAT0, NULL); /* GP_4_9 */
gpio_request(GPIO_GFN_SD3_DAT1, NULL); /* GP_4_10 */
gpio_request(GPIO_GFN_SD3_DAT2, NULL); /* GP_4_11 */
gpio_request(GPIO_GFN_SD3_DAT3, NULL); /* GP_4_12 */
gpio_request(GPIO_GFN_SD3_CLK, NULL); /* GP_4_7 */
gpio_request(GPIO_GFN_SD3_CMD, NULL); /* GP_4_8 */
#elif defined(CONFIG_R8A7796)
gpio_request(GPIO_FN_SD3_DAT0, NULL); /* GP_4_9 */
gpio_request(GPIO_FN_SD3_DAT1, NULL); /* GP_4_10 */
gpio_request(GPIO_FN_SD3_DAT2, NULL); /* GP_4_11 */
gpio_request(GPIO_FN_SD3_DAT3, NULL); /* GP_4_12 */
gpio_request(GPIO_FN_SD3_CLK, NULL); /* GP_4_7 */
gpio_request(GPIO_FN_SD3_CMD, NULL); /* GP_4_8 */
#else
#error Only R8A7795 and R87796 is supported
#endif
/* IPSR10 */
gpio_request(GPIO_FN_SD3_CD, NULL);
gpio_request(GPIO_FN_SD3_WP, NULL);
gpio_request(GPIO_GP_3_15, NULL);
gpio_request(GPIO_GP_3_14, NULL);
gpio_direction_output(GPIO_GP_3_15, 1); /* power on */
gpio_direction_output(GPIO_GP_3_14, 1); /* 1: 3.3V, 0: 1.8V */
#endif
/* Configure the HSUSB block */
mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
/* Choice USB0SEL */
clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
/* low power status */
setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
return 0;
}

8
board/renesas/ulcb/cpld.c
View File

@ -12,10 +12,10 @@
#include <asm/io.h>
#include <asm/gpio.h>
#define SCLK GPIO_GP_6_8
#define SSTBZ GPIO_GP_2_3
#define MOSI GPIO_GP_6_7
#define MISO GPIO_GP_6_10
#define SCLK (192 + 8) /* GPIO6 8 */
#define SSTBZ (64 + 3) /* GPIO2 3 */
#define MOSI (192 + 7) /* GPIO6 8 */
#define MISO (192 + 10) /* GPIO6 10 */
#define CPLD_ADDR_MODE 0x00 /* RW */
#define CPLD_ADDR_MUX 0x02 /* RW */

114
board/renesas/ulcb/ulcb.c
View File

@ -48,34 +48,13 @@ void s_init(void)
#define TMU0_MSTP125 BIT(25) /* secure */
#define TMU1_MSTP124 BIT(24) /* non-secure */
#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
#define ETHERAVB_MSTP812 BIT(12)
#define DVFS_MSTP926 BIT(26)
#define SD0_MSTP314 BIT(14)
#define SD1_MSTP313 BIT(13)
#define SD2_MSTP312 BIT(12) /* either MMC0 */
#define SD0CKCR 0xE6150074
#define SD1CKCR 0xE6150078
#define SD2CKCR 0xE6150268
#define SD3CKCR 0xE615026C
#define HSUSB_MSTP704 BIT(4) /* HSUSB */
int board_early_init_f(void)
{
/* TMU0,1 */ /* which use ? */
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
/* SCIF2 */
mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310);
/* EHTERAVB */
mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHERAVB_MSTP812);
/* eMMC */
mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD1_MSTP313 | SD2_MSTP312);
/* SDHI0 */
mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314);
writel(1, SD0CKCR);
writel(1, SD1CKCR);
writel(1, SD2CKCR);
writel(1, SD3CKCR);
#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
/* DVFS for reset */
@ -90,91 +69,28 @@ int board_early_init_f(void)
/* -/W 32 Power resume control register 2 (3DG) */
#define SYSC_PWRONCR2 0xE618010C
/* HSUSB block registers */
#define HSUSB_REG_LPSTS 0xE6590102
#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
#define HSUSB_REG_UGCTRL2 0xE6590184
#define HSUSB_REG_UGCTRL2_USB0SEL 0x30
#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
/* Init PFC controller */
#if defined(CONFIG_R8A7795)
r8a7795_pinmux_init();
#elif defined(CONFIG_R8A7796)
r8a7796_pinmux_init();
#endif
/* USB1 pull-up */
setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
#ifdef CONFIG_RENESAS_RAVB
/* EtherAVB Enable */
/* GPSR2 */
gpio_request(GPIO_GFN_AVB_AVTP_CAPTURE_A, NULL);
gpio_request(GPIO_GFN_AVB_AVTP_MATCH_A, NULL);
gpio_request(GPIO_GFN_AVB_LINK, NULL);
gpio_request(GPIO_GFN_AVB_PHY_INT, NULL);
gpio_request(GPIO_GFN_AVB_MAGIC, NULL);
gpio_request(GPIO_GFN_AVB_MDC, NULL);
/* IPSR0 */
gpio_request(GPIO_IFN_AVB_MDC, NULL);
gpio_request(GPIO_IFN_AVB_MAGIC, NULL);
gpio_request(GPIO_IFN_AVB_PHY_INT, NULL);
gpio_request(GPIO_IFN_AVB_LINK, NULL);
gpio_request(GPIO_IFN_AVB_AVTP_MATCH_A, NULL);
gpio_request(GPIO_IFN_AVB_AVTP_CAPTURE_A, NULL);
/* IPSR1 */
gpio_request(GPIO_FN_AVB_AVTP_PPS, NULL);
/* IPSR2 */
gpio_request(GPIO_FN_AVB_AVTP_MATCH_B, NULL);
/* IPSR3 */
gpio_request(GPIO_FN_AVB_AVTP_CAPTURE_B, NULL);
/* AVB_PHY_RST */
gpio_request(GPIO_GP_2_10, NULL);
gpio_direction_output(GPIO_GP_2_10, 0);
mdelay(20);
gpio_set_value(GPIO_GP_2_10, 1);
udelay(1);
#endif
#ifdef CONFIG_MMC
/* SDHI0 */
gpio_request(GPIO_GFN_SD0_DAT0, NULL);
gpio_request(GPIO_GFN_SD0_DAT1, NULL);
gpio_request(GPIO_GFN_SD0_DAT2, NULL);
gpio_request(GPIO_GFN_SD0_DAT3, NULL);
gpio_request(GPIO_GFN_SD0_CLK, NULL);
gpio_request(GPIO_GFN_SD0_CMD, NULL);
gpio_request(GPIO_GFN_SD0_CD, NULL);
gpio_request(GPIO_GFN_SD0_WP, NULL);
gpio_request(GPIO_GP_5_2, NULL);
gpio_request(GPIO_GP_5_1, NULL);
gpio_direction_output(GPIO_GP_5_2, 1); /* power on */
gpio_direction_output(GPIO_GP_5_1, 1); /* 1: 3.3V, 0: 1.8V */
/* SDHI1/SDHI2 eMMC */
gpio_request(GPIO_GFN_SD1_DAT0, NULL);
gpio_request(GPIO_GFN_SD1_DAT1, NULL);
gpio_request(GPIO_GFN_SD1_DAT2, NULL);
gpio_request(GPIO_GFN_SD1_DAT3, NULL);
gpio_request(GPIO_GFN_SD2_DAT0, NULL);
gpio_request(GPIO_GFN_SD2_DAT1, NULL);
gpio_request(GPIO_GFN_SD2_DAT2, NULL);
gpio_request(GPIO_GFN_SD2_DAT3, NULL);
gpio_request(GPIO_GFN_SD2_CLK, NULL);
#if defined(CONFIG_R8A7795)
gpio_request(GPIO_GFN_SD2_CMD, NULL);
#elif defined(CONFIG_R8A7796)
gpio_request(GPIO_FN_SD2_CMD, NULL);
#else
#error Only R8A7795 and R87796 is supported
#endif
gpio_request(GPIO_GP_5_3, NULL);
gpio_request(GPIO_GP_5_9, NULL);
gpio_direction_output(GPIO_GP_5_3, 0); /* 1: 3.3V, 0: 1.8V */
gpio_direction_output(GPIO_GP_5_9, 0); /* 1: 3.3V, 0: 1.8V */
#endif
/* Configure the HSUSB block */
mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
/* Choice USB0SEL */
clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
/* low power status */
setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
return 0;
}

16
configs/r8a7795_salvator-x_defconfig
View File

@ -12,26 +12,40 @@ CONFIG_DEFAULT_FDT_FILE="r8a7795-salvator-x.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SDRAM=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DM_GPIO=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_MMC=y
CONFIG_SH_SDHI=y
CONFIG_MMC_UNIPHIER=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_RENESAS_RAVB=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_PINCTRL_PFC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_SMBIOS_MANUFACTURER=""

17
configs/r8a7795_ulcb_defconfig
View File

@ -12,22 +12,37 @@ CONFIG_DEFAULT_FDT_FILE="r8a7795-h3ulcb.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DM_GPIO=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_MMC=y
CONFIG_SH_SDHI=y
CONFIG_MMC_UNIPHIER=y
CONFIG_DM_ETH=y
CONFIG_RENESAS_RAVB=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_PINCTRL_PFC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_SMBIOS_MANUFACTURER=""

16
configs/r8a7796_salvator-x_defconfig
View File

@ -13,26 +13,40 @@ CONFIG_DEFAULT_FDT_FILE="r8a7796-salvator-x.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SDRAM=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DM_GPIO=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_MMC=y
CONFIG_SH_SDHI=y
CONFIG_MMC_UNIPHIER=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_RENESAS_RAVB=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_PINCTRL_PFC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_SMBIOS_MANUFACTURER=""

17
configs/r8a7796_ulcb_defconfig
View File

@ -13,22 +13,37 @@ CONFIG_DEFAULT_FDT_FILE="r8a7796-m3ulcb.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DM_GPIO=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_MMC=y
CONFIG_SH_SDHI=y
CONFIG_MMC_UNIPHIER=y
CONFIG_DM_ETH=y
CONFIG_RENESAS_RAVB=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_PINCTRL_PFC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_SMBIOS_MANUFACTURER=""

41
doc/README.rmobile
View File

@ -2,8 +2,8 @@ Summary
=======
This README is about U-Boot support for Renesas's ARM Cortex-A9 based RMOBILE[1]
and R-Car[2]family of SoCs. Renesas's RMOBILE/R-Car SoC family contains an ARM
Cortex-A9.
and Cortex-A9/A53/A57 based R-Car[2] family of SoCs. Renesas's RMOBILE/R-Car SoC
family contains an ARM Cortex-A9/A53/A57.
Currently the following boards are supported:
@ -11,16 +11,21 @@ Currently the following boards are supported:
* Atmark-Techno Armadillo-800-EVA [4]
* Renesas Electronics Lager
* Renesas Electronics Koelsch
* Renesas Electronics Salvator-X M3
* Renesas Electronics Salvator-XS H3 ES2.0+
* Renesas Electronics ULCB M3 / H3 ES2.0+
Toolchain
=========
ARM Cortex-A9 support ARM v7 instruction set (-march=armv7a).
But currently we compile with -march=armv5 to allow more compilers to work.
(For U-Boot code this has no performance impact.)
Because there was no compiler which is supporting armv7a not much before.
Currently, ELDK[5], Linaro[6], CodeSourcey[7] and Emdebian[8] supports -march=armv7a
and you can get.
Either ARMv7 toolchain for 32bit Cortex-A9 systems or ARMv8 (aarch64)
toolchain for 64bit Cortex-A53/A57 systems. Currently we compile the
32bit systems with -march=armv5 to allow more compilers to work. (For
U-Boot code this has no performance impact.)
Currently, ELDK[5], Linaro[6], CodeSourcery[7] and Emdebian[8] supports
ARMv7. Modern distributions also contain ARMv7 and ARMv8 crosstoolchains
in their package feeds.
Build
=====
@ -48,6 +53,26 @@ Build
make koelsch_config
make
* Salvator-X M3
make r8a7796_salvator-x_defconfig
make
* Salvator-XS H3 ES2.0
make r8a7795_salvator-x_defconfig
make
* ULCB M3
make r8a7796_ulcb_defconfig
make
* ULCB H3 ES2.0
make r8a7795_ulcb_defconfig
make
Links
=====

78
drivers/clk/renesas/clk-rcar-gen3.c
View File

@ -27,6 +27,11 @@
#define CPG_PLL2CR 0x002c
#define CPG_PLL4CR 0x01f4
#define CPG_RPC_PREDIV_MASK 0x3
#define CPG_RPC_PREDIV_OFFSET 3
#define CPG_RPC_POSTDIV_MASK 0x7
#define CPG_RPC_POSTDIV_OFFSET 0
/*
* Module Standby and Software Reset register offets.
*
@ -119,6 +124,8 @@ enum clk_types {
DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
#define DEF_GEN3_RPC(_name, _id, _parent, _offset) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset)
/*
* Definitions of Module Clocks
@ -145,6 +152,7 @@ enum rcar_gen3_clk_types {
CLK_TYPE_GEN3_PLL3,
CLK_TYPE_GEN3_PLL4,
CLK_TYPE_GEN3_SD,
CLK_TYPE_GEN3_RPC,
CLK_TYPE_GEN3_R,
};
@ -176,6 +184,7 @@ enum clk_ids {
CLK_S2,
CLK_S3,
CLK_SDSRC,
CLK_RPCSRC,
CLK_SSPSRC,
CLK_RINT,
@ -203,6 +212,7 @@ static const struct cpg_core_clk r8a7795_core_clks[] = {
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
/* Core Clock Outputs */
DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
@ -231,6 +241,8 @@ static const struct cpg_core_clk r8a7795_core_clks[] = {
DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268),
DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c),
DEF_GEN3_RPC("rpc", R8A7795_CLK_RPC, CLK_RPCSRC, 0x238),
DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
@ -358,6 +370,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4),
DEF_MOD("rpc", 917, R8A7795_CLK_RPC),
DEF_MOD("i2c6", 918, R8A7795_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A7795_CLK_S0D6),
DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP),
@ -414,6 +427,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] = {
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
/* Core Clock Outputs */
DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
@ -442,6 +456,8 @@ static const struct cpg_core_clk r8a7796_core_clks[] = {
DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268),
DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c),
DEF_GEN3_RPC("rpc", R8A7796_CLK_RPC, CLK_RPCSRC, 0x238),
DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1),
@ -541,6 +557,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = {
DEF_MOD("can-fd", 914, R8A7796_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A7796_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A7796_CLK_S3D4),
DEF_MOD("rpc", 917, R8A7795_CLK_RPC),
DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A7796_CLK_S0D6),
DEF_MOD("i2c-dvfs", 926, R8A7796_CLK_CP),
@ -752,6 +769,36 @@ static int gen3_clk_get_parent(struct clk *clk, struct clk *parent)
return 0;
}
static int gen3_clk_setup_sdif_div(struct clk *clk)
{
struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
const struct cpg_core_clk *core;
struct clk parent;
int ret;
ret = gen3_clk_get_parent(clk, &parent);
if (ret) {
printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
return ret;
}
if (gen3_clk_is_mod(&parent))
return 0;
ret = gen3_clk_get_core(&parent, &core);
if (ret)
return ret;
if (core->type != CLK_TYPE_GEN3_SD)
return 0;
debug("%s[%i] SDIF offset=%x\n", __func__, __LINE__, core->offset);
writel(1, priv->base + core->offset);
return 0;
}
static int gen3_clk_endisable(struct clk *clk, bool enable)
{
struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
@ -759,6 +806,7 @@ static int gen3_clk_endisable(struct clk *clk, bool enable)
const unsigned int reg = clkid / 100;
const unsigned int bit = clkid % 100;
const u32 bitmask = BIT(bit);
int ret;
if (!gen3_clk_is_mod(clk))
return -EINVAL;
@ -767,6 +815,9 @@ static int gen3_clk_endisable(struct clk *clk, bool enable)
clkid, reg, bit, enable ? "ON" : "OFF");
if (enable) {
ret = gen3_clk_setup_sdif_div(clk);
if (ret)
return ret;
clrbits_le32(priv->base + SMSTPCR(reg), bitmask);
return wait_for_bit("MSTP", priv->base + MSTPSR(reg),
bitmask, 0, 100, 0);
@ -793,7 +844,7 @@ static ulong gen3_clk_get_rate(struct clk *clk)
const struct cpg_core_clk *core;
const struct rcar_gen3_cpg_pll_config *pll_config =
priv->cpg_pll_config;
u32 value, mult, rate = 0;
u32 value, mult, prediv, postdiv, rate = 0;
int i, ret;
debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
@ -903,6 +954,31 @@ static ulong gen3_clk_get_rate(struct clk *clk)
}
return -EINVAL;
case CLK_TYPE_GEN3_RPC:
rate = gen3_clk_get_rate(&parent);
value = readl(priv->base + core->offset);
prediv = (value >> CPG_RPC_PREDIV_OFFSET) &
CPG_RPC_PREDIV_MASK;
if (prediv == 2)
rate /= 5;
else if (prediv == 3)
rate /= 6;
else
return -EINVAL;
postdiv = (value >> CPG_RPC_POSTDIV_OFFSET) &
CPG_RPC_POSTDIV_MASK;
rate /= postdiv + 1;
debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%u\n",
__func__, __LINE__,
core->parent, prediv, postdiv, rate);
return -EINVAL;
}
printf("%s[%i] unknown fail\n", __func__, __LINE__);

6
drivers/gpio/Kconfig
View File

@ -135,6 +135,12 @@ config PCF8575_GPIO
Support for PCF8575 I2C 16-bit GPIO expander. Most of these
chips are from NXP and TI.
config RCAR_GPIO
bool "Renesas RCar GPIO driver"
depends on DM_GPIO && ARCH_RMOBILE
help
This driver supports the GPIO banks on Renesas RCar SoCs.
config ROCKCHIP_GPIO
bool "Rockchip GPIO driver"
depends on DM_GPIO

1
drivers/gpio/Makefile
View File

@ -28,6 +28,7 @@ obj-$(CONFIG_MXS_GPIO) += mxs_gpio.o
obj-$(CONFIG_PCA953X) += pca953x.o
obj-$(CONFIG_PCA9698) += pca9698.o
obj-$(CONFIG_ROCKCHIP_GPIO) += rk_gpio.o
obj-$(CONFIG_RCAR_GPIO) += gpio-rcar.o
obj-$(CONFIG_S5P) += s5p_gpio.o
obj-$(CONFIG_SANDBOX_GPIO) += sandbox.o
obj-$(CONFIG_SPEAR_GPIO) += spear_gpio.o

169
drivers/gpio/gpio-rcar.c Normal file
View File

@ -0,0 +1,169 @@
/*
* Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
#define GPIO_IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
#define GPIO_INOUTSEL 0x04 /* General Input/Output Switching Register */
#define GPIO_OUTDT 0x08 /* General Output Register */
#define GPIO_INDT 0x0c /* General Input Register */
#define GPIO_INTDT 0x10 /* Interrupt Display Register */
#define GPIO_INTCLR 0x14 /* Interrupt Clear Register */
#define GPIO_INTMSK 0x18 /* Interrupt Mask Register */
#define GPIO_MSKCLR 0x1c /* Interrupt Mask Clear Register */
#define GPIO_POSNEG 0x20 /* Positive/Negative Logic Select Register */
#define GPIO_EDGLEVEL 0x24 /* Edge/level Select Register */
#define GPIO_FILONOFF 0x28 /* Chattering Prevention On/Off Register */
#define GPIO_BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
#define RCAR_MAX_GPIO_PER_BANK 32
DECLARE_GLOBAL_DATA_PTR;
struct rcar_gpio_priv {
void __iomem *regs;
};
static int rcar_gpio_get_value(struct udevice *dev, unsigned offset)
{
struct rcar_gpio_priv *priv = dev_get_priv(dev);
const u32 bit = BIT(offset);
/*
* Testing on r8a7790 shows that INDT does not show correct pin state
* when configured as output, so use OUTDT in case of output pins.
*/
if (readl(priv->regs + GPIO_INOUTSEL) & bit)
return !!(readl(priv->regs + GPIO_OUTDT) & bit);
else
return !!(readl(priv->regs + GPIO_INDT) & bit);
}
static int rcar_gpio_set_value(struct udevice *dev, unsigned offset,
int value)
{
struct rcar_gpio_priv *priv = dev_get_priv(dev);
if (value)
setbits_le32(priv->regs + GPIO_OUTDT, BIT(offset));
else
clrbits_le32(priv->regs + GPIO_OUTDT, BIT(offset));
return 0;
}
static void rcar_gpio_set_direction(void __iomem *regs, unsigned offset,
bool output)
{
/*
* follow steps in the GPIO documentation for
* "Setting General Output Mode" and
* "Setting General Input Mode"
*/
/* Configure postive logic in POSNEG */
clrbits_le32(regs + GPIO_POSNEG, BIT(offset));
/* Select "General Input/Output Mode" in IOINTSEL */
clrbits_le32(regs + GPIO_IOINTSEL, BIT(offset));
/* Select Input Mode or Output Mode in INOUTSEL */
if (output)
setbits_le32(regs + GPIO_INOUTSEL, BIT(offset));
else
clrbits_le32(regs + GPIO_INOUTSEL, BIT(offset));
}
static int rcar_gpio_direction_input(struct udevice *dev, unsigned offset)
{
struct rcar_gpio_priv *priv = dev_get_priv(dev);
rcar_gpio_set_direction(priv->regs, offset, false);
return 0;
}
static int rcar_gpio_direction_output(struct udevice *dev, unsigned offset,
int value)
{
struct rcar_gpio_priv *priv = dev_get_priv(dev);
/* write GPIO value to output before selecting output mode of pin */
rcar_gpio_set_value(dev, offset, value);
rcar_gpio_set_direction(priv->regs, offset, true);
return 0;
}
static int rcar_gpio_get_function(struct udevice *dev, unsigned offset)
{
struct rcar_gpio_priv *priv = dev_get_priv(dev);
if (readl(priv->regs + GPIO_INOUTSEL) & BIT(offset))
return GPIOF_OUTPUT;
else
return GPIOF_INPUT;
}
static const struct dm_gpio_ops rcar_gpio_ops = {
.direction_input = rcar_gpio_direction_input,
.direction_output = rcar_gpio_direction_output,
.get_value = rcar_gpio_get_value,
.set_value = rcar_gpio_set_value,
.get_function = rcar_gpio_get_function,
};
static int rcar_gpio_probe(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct rcar_gpio_priv *priv = dev_get_priv(dev);
struct fdtdec_phandle_args args;
struct clk clk;
int node = dev_of_offset(dev);
int ret;
priv->regs = (void __iomem *)devfdt_get_addr(dev);
uc_priv->bank_name = dev->name;
ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges",
NULL, 3, 0, &args);
uc_priv->gpio_count = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
ret = clk_get_by_index(dev, 0, &clk);
if (ret < 0) {
dev_err(dev, "Failed to get GPIO bank clock\n");
return ret;
}
ret = clk_enable(&clk);
clk_free(&clk);
if (ret) {
dev_err(dev, "Failed to enable GPIO bank clock\n");
return ret;
}
return 0;
}
static const struct udevice_id rcar_gpio_ids[] = {
{ .compatible = "renesas,gpio-r8a7795" },
{ .compatible = "renesas,gpio-r8a7796" },
{ /* sentinel */ }
};
U_BOOT_DRIVER(rcar_gpio) = {
.name = "rcar-gpio",
.id = UCLASS_GPIO,
.of_match = rcar_gpio_ids,
.ops = &rcar_gpio_ops,
.priv_auto_alloc_size = sizeof(struct rcar_gpio_priv),
.probe = rcar_gpio_probe,
};

13
drivers/net/ravb.c
View File

@ -18,6 +18,7 @@
#include <linux/mii.h>
#include <wait_bit.h>
#include <asm/io.h>
#include <asm/gpio.h>
/* Registers */
#define RAVB_REG_CCC 0x000
@ -122,6 +123,7 @@ struct ravb_priv {
struct mii_dev *bus;
void __iomem *iobase;
struct clk clk;
struct gpio_desc reset_gpio;
};
static inline void ravb_flush_dcache(u32 addr, u32 len)
@ -302,6 +304,13 @@ static int ravb_phy_config(struct udevice *dev)
struct phy_device *phydev;
int mask = 0xffffffff, reg;
if (dm_gpio_is_valid(&eth->reset_gpio)) {
dm_gpio_set_value(&eth->reset_gpio, 1);
mdelay(20);
dm_gpio_set_value(&eth->reset_gpio, 0);
mdelay(1);
}
phydev = phy_find_by_mask(eth->bus, mask, pdata->phy_interface);
if (!phydev)
return -ENODEV;
@ -483,6 +492,9 @@ static int ravb_probe(struct udevice *dev)
if (ret < 0)
goto err_mdio_alloc;
gpio_request_by_name_nodev(dev_ofnode(dev), "reset-gpios", 0,
&eth->reset_gpio, GPIOD_IS_OUT);
mdiodev = mdio_alloc();
if (!mdiodev) {
ret = -ENOMEM;
@ -516,6 +528,7 @@ static int ravb_remove(struct udevice *dev)
free(eth->phydev);
mdio_unregister(eth->bus);
mdio_free(eth->bus);
dm_gpio_free(dev, &eth->reset_gpio);
unmap_physmem(eth->iobase, MAP_NOCACHE);
return 0;

1
drivers/pinctrl/Kconfig
View File

@ -292,6 +292,7 @@ endif
source "drivers/pinctrl/meson/Kconfig"
source "drivers/pinctrl/nxp/Kconfig"
source "drivers/pinctrl/renesas/Kconfig"
source "drivers/pinctrl/uniphier/Kconfig"
source "drivers/pinctrl/exynos/Kconfig"
source "drivers/pinctrl/mvebu/Kconfig"

1
drivers/pinctrl/Makefile
View File

@ -10,6 +10,7 @@ obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o
obj-y += nxp/
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_ARCH_ATH79) += ath79/
obj-$(CONFIG_ARCH_RMOBILE) += renesas/
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o

31
drivers/pinctrl/renesas/Kconfig Normal file
View File

@ -0,0 +1,31 @@
if ARCH_RMOBILE
config PINCTRL_PFC
bool "Renesas pin control drivers"
depends on DM && ARCH_RMOBILE
help
Enable support for clock present on Renesas RCar SoCs.
config PINCTRL_PFC_R8A7795
bool "Renesas RCar Gen3 R8A7795 pin control driver"
def_bool y if R8A7795
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RCar Gen3 R8A7795 SoCs.
The driver is controlled by a device tree node which contains both
the GPIO definitions and pin control functions for each available
multiplex function.
config PINCTRL_PFC_R8A7796
bool "Renesas RCar Gen3 R8A7796 pin control driver"
def_bool y if R8A7796
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RCar Gen3 R8A7796 SoCs.
The driver is controlled by a device tree node which contains both
the GPIO definitions and pin control functions for each available
multiplex function.
endif

3
drivers/pinctrl/renesas/Makefile Normal file
View File

@ -0,0 +1,3 @@
obj-$(CONFIG_PINCTRL_PFC) += pfc.o
obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o

4898
drivers/pinctrl/renesas/pfc-r8a7795.c Normal file
View File

File diff suppressed because it is too large Load Diff

5728
drivers/pinctrl/renesas/pfc-r8a7796.c Normal file
View File

File diff suppressed because it is too large Load Diff

752
drivers/pinctrl/renesas/pfc.c Normal file
View File

@ -0,0 +1,752 @@
/*
* Pin Control driver for SuperH Pin Function Controller.
*
* Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
*
* Copyright (C) 2008 Magnus Damm
* Copyright (C) 2009 - 2012 Paul Mundt
* Copyright (C) 2017 Marek Vasut
*
* SPDX-License-Identifier: GPL-2.0
*/
#define DRV_NAME "sh-pfc"
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <dm/pinctrl.h>
#include <linux/io.h>
#include <linux/sizes.h>
#include "sh_pfc.h"
DECLARE_GLOBAL_DATA_PTR;
enum sh_pfc_model {
SH_PFC_R8A7795 = 0,
SH_PFC_R8A7796,
};
struct sh_pfc_pin_config {
u32 type;
};
struct sh_pfc_pinctrl {
struct sh_pfc *pfc;
struct sh_pfc_pin_config *configs;
const char *func_prop_name;
const char *groups_prop_name;
const char *pins_prop_name;
};
struct sh_pfc_pin_range {
u16 start;
u16 end;
};
struct sh_pfc_pinctrl_priv {
struct sh_pfc pfc;
struct sh_pfc_pinctrl pmx;
};
int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
{
unsigned int offset;
unsigned int i;
for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
const struct sh_pfc_pin_range *range = &pfc->ranges[i];
if (pin <= range->end)
return pin >= range->start
? offset + pin - range->start : -1;
offset += range->end - range->start + 1;
}
return -EINVAL;
}
static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
{
if (enum_id < r->begin)
return 0;
if (enum_id > r->end)
return 0;
return 1;
}
u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
{
switch (reg_width) {
case 8:
return readb(mapped_reg);
case 16:
return readw(mapped_reg);
case 32:
return readl(mapped_reg);
}
BUG();
return 0;
}
void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
u32 data)
{
switch (reg_width) {
case 8:
writeb(data, mapped_reg);
return;
case 16:
writew(data, mapped_reg);
return;
case 32:
writel(data, mapped_reg);
return;
}
BUG();
}
u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width)
{
return sh_pfc_read_raw_reg(pfc->regs + reg, width);
}
void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data)
{
void __iomem *unlock_reg =
(void __iomem *)(uintptr_t)pfc->info->unlock_reg;
if (pfc->info->unlock_reg)
sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
sh_pfc_write_raw_reg(pfc->regs + reg, width, data);
}
static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
const struct pinmux_cfg_reg *crp,
unsigned int in_pos,
void __iomem **mapped_regp, u32 *maskp,
unsigned int *posp)
{
unsigned int k;
*mapped_regp = (void __iomem *)(uintptr_t)crp->reg;
if (crp->field_width) {
*maskp = (1 << crp->field_width) - 1;
*posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
} else {
*maskp = (1 << crp->var_field_width[in_pos]) - 1;
*posp = crp->reg_width;
for (k = 0; k <= in_pos; k++)
*posp -= crp->var_field_width[k];
}
}
static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
const struct pinmux_cfg_reg *crp,
unsigned int field, u32 value)
{
void __iomem *mapped_reg;
void __iomem *unlock_reg =
(void __iomem *)(uintptr_t)pfc->info->unlock_reg;
unsigned int pos;
u32 mask, data;
sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
"r_width = %u, f_width = %u\n",
crp->reg, value, field, crp->reg_width, crp->field_width);
mask = ~(mask << pos);
value = value << pos;
data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
data &= mask;
data |= value;
if (pfc->info->unlock_reg)
sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
}
static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
const struct pinmux_cfg_reg **crp,
unsigned int *fieldp, u32 *valuep)
{
unsigned int k = 0;
while (1) {
const struct pinmux_cfg_reg *config_reg =
pfc->info->cfg_regs + k;
unsigned int r_width = config_reg->reg_width;
unsigned int f_width = config_reg->field_width;
unsigned int curr_width;
unsigned int bit_pos;
unsigned int pos = 0;
unsigned int m = 0;
if (!r_width)
break;
for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
u32 ncomb;
u32 n;
if (f_width)
curr_width = f_width;
else
curr_width = config_reg->var_field_width[m];
ncomb = 1 << curr_width;
for (n = 0; n < ncomb; n++) {
if (config_reg->enum_ids[pos + n] == enum_id) {
*crp = config_reg;
*fieldp = m;
*valuep = n;
return 0;
}
}
pos += ncomb;
m++;
}
k++;
}
return -EINVAL;
}
static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
u16 *enum_idp)
{
const u16 *data = pfc->info->pinmux_data;
unsigned int k;
if (pos) {
*enum_idp = data[pos + 1];
return pos + 1;
}
for (k = 0; k < pfc->info->pinmux_data_size; k++) {
if (data[k] == mark) {
*enum_idp = data[k + 1];
return k + 1;
}
}
dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
mark);
return -EINVAL;
}
int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
{
const struct pinmux_range *range;
int pos = 0;
switch (pinmux_type) {
case PINMUX_TYPE_GPIO:
case PINMUX_TYPE_FUNCTION:
range = NULL;
break;
case PINMUX_TYPE_OUTPUT:
range = &pfc->info->output;
break;
case PINMUX_TYPE_INPUT:
range = &pfc->info->input;
break;
default:
return -EINVAL;
}
/* Iterate over all the configuration fields we need to update. */
while (1) {
const struct pinmux_cfg_reg *cr;
unsigned int field;
u16 enum_id;
u32 value;
int in_range;
int ret;
pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
if (pos < 0)
return pos;
if (!enum_id)
break;
/* Check if the configuration field selects a function. If it
* doesn't, skip the field if it's not applicable to the
* requested pinmux type.
*/
in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
if (!in_range) {
if (pinmux_type == PINMUX_TYPE_FUNCTION) {
/* Functions are allowed to modify all
* fields.
*/
in_range = 1;
} else if (pinmux_type != PINMUX_TYPE_GPIO) {
/* Input/output types can only modify fields
* that correspond to their respective ranges.
*/
in_range = sh_pfc_enum_in_range(enum_id, range);
/*
* special case pass through for fixed
* input-only or output-only pins without
* function enum register association.
*/
if (in_range && enum_id == range->force)
continue;
}
/* GPIOs are only allowed to modify function fields. */
}
if (!in_range)
continue;
ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
if (ret < 0)
return ret;
sh_pfc_write_config_reg(pfc, cr, field, value);
}
return 0;
}
const struct sh_pfc_bias_info *
sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
unsigned int num, unsigned int pin)
{
unsigned int i;
for (i = 0; i < num; i++)
if (info[i].pin == pin)
return &info[i];
printf("Pin %u is not in bias info list\n", pin);
return NULL;
}
static int sh_pfc_init_ranges(struct sh_pfc *pfc)
{
struct sh_pfc_pin_range *range;
unsigned int nr_ranges;
unsigned int i;
if (pfc->info->pins[0].pin == (u16)-1) {
/* Pin number -1 denotes that the SoC doesn't report pin numbers
* in its pin arrays yet. Consider the pin numbers range as
* continuous and allocate a single range.
*/
pfc->nr_ranges = 1;
pfc->ranges = kzalloc(sizeof(*pfc->ranges), GFP_KERNEL);
if (pfc->ranges == NULL)
return -ENOMEM;
pfc->ranges->start = 0;
pfc->ranges->end = pfc->info->nr_pins - 1;
pfc->nr_gpio_pins = pfc->info->nr_pins;
return 0;
}
/* Count, allocate and fill the ranges. The PFC SoC data pins array must
* be sorted by pin numbers, and pins without a GPIO port must come
* last.
*/
for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
nr_ranges++;
}
pfc->nr_ranges = nr_ranges;
pfc->ranges = kzalloc(sizeof(*pfc->ranges) * nr_ranges, GFP_KERNEL);
if (pfc->ranges == NULL)
return -ENOMEM;
range = pfc->ranges;
range->start = pfc->info->pins[0].pin;
for (i = 1; i < pfc->info->nr_pins; ++i) {
if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
continue;
range->end = pfc->info->pins[i-1].pin;
if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
pfc->nr_gpio_pins = range->end + 1;
range++;
range->start = pfc->info->pins[i].pin;
}
range->end = pfc->info->pins[i-1].pin;
if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
pfc->nr_gpio_pins = range->end + 1;
return 0;
}
static int sh_pfc_pinctrl_get_pins_count(struct udevice *dev)
{
struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
return priv->pfc.info->nr_pins;
}
static const char *sh_pfc_pinctrl_get_pin_name(struct udevice *dev,
unsigned selector)
{
struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
return priv->pfc.info->pins[selector].name;
}
static int sh_pfc_pinctrl_get_groups_count(struct udevice *dev)
{
struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
return priv->pfc.info->nr_groups;
}
static const char *sh_pfc_pinctrl_get_group_name(struct udevice *dev,
unsigned selector)
{
struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
return priv->pfc.info->groups[selector].name;
}
static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev)
{
struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
return priv->pfc.info->nr_functions;
}
static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev,
unsigned selector)
{
struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
return priv->pfc.info->functions[selector].name;
}
static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector,
unsigned func_selector)
{
struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
struct sh_pfc_pinctrl *pmx = &priv->pmx;
struct sh_pfc *pfc = &priv->pfc;
const struct sh_pfc_pin_group *grp = &priv->pfc.info->groups[group_selector];
unsigned int i;
int ret = 0;
for (i = 0; i < grp->nr_pins; ++i) {
int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
if (cfg->type != PINMUX_TYPE_NONE) {
ret = -EBUSY;
goto done;
}
}
for (i = 0; i < grp->nr_pins; ++i) {
ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
if (ret < 0)
break;
}
done:
return ret;
}
#if CONFIG_IS_ENABLED(PINCONF)
static const struct pinconf_param sh_pfc_pinconf_params[] = {
{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
{ "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
{ "power-source", PIN_CONFIG_POWER_SOURCE, 3300 },
};
static void __iomem *
sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, unsigned int pin,
unsigned int *offset, unsigned int *size)
{
const struct pinmux_drive_reg_field *field;
const struct pinmux_drive_reg *reg;
unsigned int i;
for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
field = &reg->fields[i];
if (field->size && field->pin == pin) {
*offset = field->offset;
*size = field->size;
return (void __iomem *)(uintptr_t)reg->reg;
}
}
}
return NULL;
}
static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
unsigned int pin, u16 strength)
{
unsigned int offset;
unsigned int size;
unsigned int step;
void __iomem *reg;
void __iomem *unlock_reg =
(void __iomem *)(uintptr_t)pfc->info->unlock_reg;
u32 val;
reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
if (!reg)
return -EINVAL;
step = size == 2 ? 6 : 3;
if (strength < step || strength > 24)
return -EINVAL;
/* Convert the value from mA based on a full drive strength value of
* 24mA. We can make the full value configurable later if needed.
*/
strength = strength / step - 1;
val = sh_pfc_read_raw_reg(reg, 32);
val &= ~GENMASK(offset + size - 1, offset);
val |= strength << offset;
if (unlock_reg)
sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
sh_pfc_write_raw_reg(reg, 32, val);
return 0;
}
/* Check whether the requested parameter is supported for a pin. */
static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
unsigned int param)
{
int idx = sh_pfc_get_pin_index(pfc, _pin);
const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
return pin->configs &
(SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
case PIN_CONFIG_BIAS_PULL_UP:
return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
case PIN_CONFIG_BIAS_PULL_DOWN:
return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
case PIN_CONFIG_DRIVE_STRENGTH:
return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
case PIN_CONFIG_POWER_SOURCE:
return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
default:
return false;
}
}
static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
unsigned int param, unsigned int arg)
{
struct sh_pfc *pfc = pmx->pfc;
void __iomem *pocctrl;
void __iomem *unlock_reg =
(void __iomem *)(uintptr_t)pfc->info->unlock_reg;
u32 addr, val;
int bit, ret;
if (!sh_pfc_pinconf_validate(pfc, _pin, param))
return -ENOTSUPP;
switch (param) {
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
case PIN_CONFIG_BIAS_DISABLE:
if (!pfc->info->ops || !pfc->info->ops->set_bias)
return -ENOTSUPP;
pfc->info->ops->set_bias(pfc, _pin, param);
break;
case PIN_CONFIG_DRIVE_STRENGTH:
ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
if (ret < 0)
return ret;
break;
case PIN_CONFIG_POWER_SOURCE:
if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
return -ENOTSUPP;
bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &addr);
if (bit < 0) {
printf("invalid pin %#x", _pin);
return bit;
}
if (arg != 1800 && arg != 3300)
return -EINVAL;
pocctrl = (void __iomem *)(uintptr_t)addr;
val = sh_pfc_read_raw_reg(pocctrl, 32);
if (arg == 3300)
val |= BIT(bit);
else
val &= ~BIT(bit);
if (unlock_reg)
sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
sh_pfc_write_raw_reg(pocctrl, 32, val);
break;
default:
return -ENOTSUPP;
}
return 0;
}
static int sh_pfc_pinconf_group_set(struct udevice *dev,
unsigned int group_selector,
unsigned int param, unsigned int arg)
{
struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
struct sh_pfc_pinctrl *pmx = &priv->pmx;
struct sh_pfc *pfc = &priv->pfc;
const struct sh_pfc_pin_group *grp = &pfc->info->groups[group_selector];
unsigned int i;
for (i = 0; i < grp->nr_pins; i++)
sh_pfc_pinconf_set(pmx, grp->pins[i], param, arg);
return 0;
}
#endif
static struct pinctrl_ops sh_pfc_pinctrl_ops = {
.get_pins_count = sh_pfc_pinctrl_get_pins_count,
.get_pin_name = sh_pfc_pinctrl_get_pin_name,
.get_groups_count = sh_pfc_pinctrl_get_groups_count,
.get_group_name = sh_pfc_pinctrl_get_group_name,
.get_functions_count = sh_pfc_pinctrl_get_functions_count,
.get_function_name = sh_pfc_pinctrl_get_function_name,
#if CONFIG_IS_ENABLED(PINCONF)
.pinconf_num_params = ARRAY_SIZE(sh_pfc_pinconf_params),
.pinconf_params = sh_pfc_pinconf_params,
.pinconf_group_set = sh_pfc_pinconf_group_set,
#endif
.pinmux_group_set = sh_pfc_pinctrl_group_set,
.set_state = pinctrl_generic_set_state,
};
static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
{
unsigned int i;
/* Allocate and initialize the pins and configs arrays. */
pmx->configs = kzalloc(sizeof(*pmx->configs) * pfc->info->nr_pins,
GFP_KERNEL);
if (unlikely(!pmx->configs))
return -ENOMEM;
for (i = 0; i < pfc->info->nr_pins; ++i) {
struct sh_pfc_pin_config *cfg = &pmx->configs[i];
cfg->type = PINMUX_TYPE_NONE;
}
return 0;
}
static int sh_pfc_pinctrl_probe(struct udevice *dev)
{
struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
enum sh_pfc_model model = dev_get_driver_data(dev);
fdt_addr_t base;
base = devfdt_get_addr(dev);
if (base == FDT_ADDR_T_NONE)
return -EINVAL;
priv->pfc.regs = devm_ioremap(dev, base, SZ_2K);
if (!priv->pfc.regs)
return -ENOMEM;
#ifdef CONFIG_PINCTRL_PFC_R8A7795
if (model == SH_PFC_R8A7795)
priv->pfc.info = &r8a7795_pinmux_info;
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7796
if (model == SH_PFC_R8A7796)
priv->pfc.info = &r8a7796_pinmux_info;
#endif
priv->pmx.pfc = &priv->pfc;
sh_pfc_init_ranges(&priv->pfc);
sh_pfc_map_pins(&priv->pfc, &priv->pmx);
return 0;
}
static const struct udevice_id sh_pfc_pinctrl_ids[] = {
#ifdef CONFIG_PINCTRL_PFC_R8A7795
{
.compatible = "renesas,pfc-r8a7795",
.data = SH_PFC_R8A7795,
},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7796
{
.compatible = "renesas,pfc-r8a7796",
.data = SH_PFC_R8A7796,
},
#endif
{ },
};
U_BOOT_DRIVER(pinctrl_sh_pfc) = {
.name = "sh_pfc_pinctrl",
.id = UCLASS_PINCTRL,
.of_match = sh_pfc_pinctrl_ids,
.priv_auto_alloc_size = sizeof(struct sh_pfc_pinctrl_priv),
.ops = &sh_pfc_pinctrl_ops,
.probe = sh_pfc_pinctrl_probe,
};

575
drivers/pinctrl/renesas/sh_pfc.h Normal file
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@ -0,0 +1,575 @@
/*
* SuperH Pin Function Controller Support
*
* Copyright (c) 2008 Magnus Damm
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __SH_PFC_H
#define __SH_PFC_H
#include <linux/stringify.h>
enum {
PINMUX_TYPE_NONE,
PINMUX_TYPE_FUNCTION,
PINMUX_TYPE_GPIO,
PINMUX_TYPE_OUTPUT,
PINMUX_TYPE_INPUT,
};
#define SH_PFC_PIN_CFG_INPUT (1 << 0)
#define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
#define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
#define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
#define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
#define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5)
#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
struct sh_pfc_pin {
u16 pin;
u16 enum_id;
const char *name;
unsigned int configs;
};
#define SH_PFC_PIN_GROUP(n) \
{ \
.name = #n, \
.pins = n##_pins, \
.mux = n##_mux, \
.nr_pins = ARRAY_SIZE(n##_pins), \
}
struct sh_pfc_pin_group {
const char *name;
const unsigned int *pins;
const unsigned int *mux;
unsigned int nr_pins;
};
/*
* Using union vin_data saves memory occupied by the VIN data pins.
* VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups
* in this case.
*/
#define VIN_DATA_PIN_GROUP(n, s) \
{ \
.name = #n#s, \
.pins = n##_pins.data##s, \
.mux = n##_mux.data##s, \
.nr_pins = ARRAY_SIZE(n##_pins.data##s), \
}
union vin_data {
unsigned int data24[24];
unsigned int data20[20];
unsigned int data16[16];
unsigned int data12[12];
unsigned int data10[10];
unsigned int data8[8];
unsigned int data4[4];
};
#define SH_PFC_FUNCTION(n) \
{ \
.name = #n, \
.groups = n##_groups, \
.nr_groups = ARRAY_SIZE(n##_groups), \
}
struct sh_pfc_function {
const char *name;
const char * const *groups;
unsigned int nr_groups;
};
struct pinmux_func {
u16 enum_id;
const char *name;
};
struct pinmux_cfg_reg {
u32 reg;
u8 reg_width, field_width;
const u16 *enum_ids;
const u8 *var_field_width;
};
/*
* Describe a config register consisting of several fields of the same width
* - name: Register name (unused, for documentation purposes only)
* - r: Physical register address
* - r_width: Width of the register (in bits)
* - f_width: Width of the fixed-width register fields (in bits)
* This macro must be followed by initialization data: For each register field
* (from left to right, i.e. MSB to LSB), 2^f_width enum IDs must be specified,
* one for each possible combination of the register field bit values.
*/
#define PINMUX_CFG_REG(name, r, r_width, f_width) \
.reg = r, .reg_width = r_width, .field_width = f_width, \
.enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])
/*
* Describe a config register consisting of several fields of different widths
* - name: Register name (unused, for documentation purposes only)
* - r: Physical register address
* - r_width: Width of the register (in bits)
* - var_fw0, var_fwn...: List of widths of the register fields (in bits),
* From left to right (i.e. MSB to LSB)
* This macro must be followed by initialization data: For each register field
* (from left to right, i.e. MSB to LSB), 2^var_fwi enum IDs must be specified,
* one for each possible combination of the register field bit values.
*/
#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
.reg = r, .reg_width = r_width, \
.var_field_width = (const u8 [r_width]) \
{ var_fw0, var_fwn, 0 }, \
.enum_ids = (const u16 [])
struct pinmux_drive_reg_field {
u16 pin;
u8 offset;
u8 size;
};
struct pinmux_drive_reg {
u32 reg;
const struct pinmux_drive_reg_field fields[8];
};
#define PINMUX_DRIVE_REG(name, r) \
.reg = r, \
.fields =
struct pinmux_data_reg {
u32 reg;
u8 reg_width;
const u16 *enum_ids;
};
/*
* Describe a data register
* - name: Register name (unused, for documentation purposes only)
* - r: Physical register address
* - r_width: Width of the register (in bits)
* This macro must be followed by initialization data: For each register bit
* (from left to right, i.e. MSB to LSB), one enum ID must be specified.
*/
#define PINMUX_DATA_REG(name, r, r_width) \
.reg = r, .reg_width = r_width, \
.enum_ids = (const u16 [r_width]) \
struct pinmux_irq {
const short *gpios;
};
/*
* Describe the mapping from GPIOs to a single IRQ
* - ids...: List of GPIOs that are mapped to the same IRQ
*/
#define PINMUX_IRQ(ids...) \
{ .gpios = (const short []) { ids, -1 } }
struct pinmux_range {
u16 begin;
u16 end;
u16 force;
};
struct sh_pfc_bias_info {
u16 pin;
u16 reg : 11;
u16 bit : 5;
};
struct sh_pfc_pin_range;
struct sh_pfc {
struct device *dev;
const struct sh_pfc_soc_info *info;
void *regs;
struct sh_pfc_pin_range *ranges;
unsigned int nr_ranges;
unsigned int nr_gpio_pins;
struct sh_pfc_chip *gpio;
};
struct sh_pfc_soc_operations {
int (*init)(struct sh_pfc *pfc);
unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
unsigned int bias);
int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl);
};
struct sh_pfc_soc_info {
const char *name;
const struct sh_pfc_soc_operations *ops;
struct pinmux_range input;
struct pinmux_range output;
struct pinmux_range function;
const struct sh_pfc_pin *pins;
unsigned int nr_pins;
const struct sh_pfc_pin_group *groups;
unsigned int nr_groups;
const struct sh_pfc_function *functions;
unsigned int nr_functions;
const struct pinmux_cfg_reg *cfg_regs;
const struct pinmux_drive_reg *drive_regs;
const struct pinmux_data_reg *data_regs;
const u16 *pinmux_data;
unsigned int pinmux_data_size;
const struct pinmux_irq *gpio_irq;
unsigned int gpio_irq_size;
u32 unlock_reg;
};
u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width);
void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data);
const struct sh_pfc_bias_info *
sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
unsigned int num, unsigned int pin);
extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
/* -----------------------------------------------------------------------------
* Helper macros to create pin and port lists
*/
/*
* sh_pfc_soc_info pinmux_data array macros
*/
/*
* Describe generic pinmux data
* - data_or_mark: *_DATA or *_MARK enum ID
* - ids...: List of enum IDs to associate with data_or_mark
*/
#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
/*
* Describe a pinmux configuration without GPIO function that needs
* configuration in a Peripheral Function Select Register (IPSR)
* - ipsr: IPSR field (unused, for documentation purposes only)
* - fn: Function name, referring to a field in the IPSR
*/
#define PINMUX_IPSR_NOGP(ipsr, fn) \
PINMUX_DATA(fn##_MARK, FN_##fn)
/*
* Describe a pinmux configuration with GPIO function that needs configuration
* in both a Peripheral Function Select Register (IPSR) and in a
* GPIO/Peripheral Function Select Register (GPSR)
* - ipsr: IPSR field
* - fn: Function name, also referring to the IPSR field
*/
#define PINMUX_IPSR_GPSR(ipsr, fn) \
PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
/*
* Describe a pinmux configuration without GPIO function that needs
* configuration in a Peripheral Function Select Register (IPSR), and where the
* pinmux function has a representation in a Module Select Register (MOD_SEL).
* - ipsr: IPSR field (unused, for documentation purposes only)
* - fn: Function name, also referring to the IPSR field
* - msel: Module selector
*/
#define PINMUX_IPSR_NOGM(ipsr, fn, msel) \
PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel)
/*
* Describe a pinmux configuration with GPIO function where the pinmux function
* has no representation in a Peripheral Function Select Register (IPSR), but
* instead solely depends on a group selection.
* - gpsr: GPSR field
* - fn: Function name, also referring to the GPSR field
* - gsel: Group selector
*/
#define PINMUX_IPSR_NOFN(gpsr, fn, gsel) \
PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel)
/*
* Describe a pinmux configuration with GPIO function that needs configuration
* in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral
* Function Select Register (GPSR), and where the pinmux function has a
* representation in a Module Select Register (MOD_SEL).
* - ipsr: IPSR field
* - fn: Function name, also referring to the IPSR field
* - msel: Module selector
*/
#define PINMUX_IPSR_MSEL(ipsr, fn, msel) \
PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)
/*
* Describe a pinmux configuration for a single-function pin with GPIO
* capability.
* - fn: Function name
*/
#define PINMUX_SINGLE(fn) \
PINMUX_DATA(fn##_MARK, FN_##fn)
/*
* GP port style (32 ports banks)
*/
#define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \
fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
#define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
#define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
PORT_GP_CFG_4(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 5, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 7, fn, sfx, cfg)
#define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0)
#define PORT_GP_CFG_9(bank, fn, sfx, cfg) \
PORT_GP_CFG_8(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 8, fn, sfx, cfg)
#define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0)
#define PORT_GP_CFG_10(bank, fn, sfx, cfg) \
PORT_GP_CFG_9(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 9, fn, sfx, cfg)
#define PORT_GP_10(bank, fn, sfx) PORT_GP_CFG_10(bank, fn, sfx, 0)
#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
PORT_GP_CFG_10(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
#define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)
#define PORT_GP_CFG_14(bank, fn, sfx, cfg) \
PORT_GP_CFG_12(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
#define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0)
#define PORT_GP_CFG_15(bank, fn, sfx, cfg) \
PORT_GP_CFG_14(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
#define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0)
#define PORT_GP_CFG_16(bank, fn, sfx, cfg) \
PORT_GP_CFG_15(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
#define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0)
#define PORT_GP_CFG_17(bank, fn, sfx, cfg) \
PORT_GP_CFG_16(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 16, fn, sfx, cfg)
#define PORT_GP_17(bank, fn, sfx) PORT_GP_CFG_17(bank, fn, sfx, 0)
#define PORT_GP_CFG_18(bank, fn, sfx, cfg) \
PORT_GP_CFG_17(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
#define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0)
#define PORT_GP_CFG_20(bank, fn, sfx, cfg) \
PORT_GP_CFG_18(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 19, fn, sfx, cfg)
#define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0)
#define PORT_GP_CFG_21(bank, fn, sfx, cfg) \
PORT_GP_CFG_20(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
#define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0)
#define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
PORT_GP_CFG_21(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
#define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0)
#define PORT_GP_CFG_24(bank, fn, sfx, cfg) \
PORT_GP_CFG_23(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 23, fn, sfx, cfg)
#define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0)
#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
PORT_GP_CFG_24(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
#define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)
#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
PORT_GP_CFG_26(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
#define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0)
#define PORT_GP_CFG_29(bank, fn, sfx, cfg) \
PORT_GP_CFG_28(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 28, fn, sfx, cfg)
#define PORT_GP_29(bank, fn, sfx) PORT_GP_CFG_29(bank, fn, sfx, 0)
#define PORT_GP_CFG_30(bank, fn, sfx, cfg) \
PORT_GP_CFG_29(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
#define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0)
#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
PORT_GP_CFG_30(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
#define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0)
#define PORT_GP_32_REV(bank, fn, sfx) \
PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
/* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
#define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx
#define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str)
/* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
#define _GP_GPIO(bank, _pin, _name, sfx, cfg) \
{ \
.pin = (bank * 32) + _pin, \
.name = __stringify(_name), \
.enum_id = _name##_DATA, \
.configs = cfg, \
}
#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
/* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */
#define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN)
#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
/*
* PORT style (linear pin space)
*/
#define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)
#define PORT_10(pn, fn, pfx, sfx) \
PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \
PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \
PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \
PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \
PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)
#define PORT_90(pn, fn, pfx, sfx) \
PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
PORT_10(pn+90, fn, pfx##9, sfx)
/* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */
#define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx
#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
/* PINMUX_GPIO - Expand to a sh_pfc_pin entry */
#define PINMUX_GPIO(_pin) \
[GPIO_##_pin] = { \
.pin = (u16)-1, \
.name = __stringify(GPIO_##_pin), \
.enum_id = _pin##_DATA, \
}
/* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
#define SH_PFC_PIN_CFG(_pin, cfgs) \
{ \
.pin = _pin, \
.name = __stringify(PORT##_pin), \
.enum_id = PORT##_pin##_DATA, \
.configs = cfgs, \
}
/* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */
#define SH_PFC_PIN_NAMED(row, col, _name) \
{ \
.pin = PIN_NUMBER(row, col), \
.name = __stringify(PIN_##_name), \
.configs = SH_PFC_PIN_CFG_NO_GPIO, \
}
/* SH_PFC_PIN_NAMED_CFG - Expand to a sh_pfc_pin entry with the given name */
#define SH_PFC_PIN_NAMED_CFG(row, col, _name, cfgs) \
{ \
.pin = PIN_NUMBER(row, col), \
.name = __stringify(PIN_##_name), \
.configs = SH_PFC_PIN_CFG_NO_GPIO | cfgs, \
}
/* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
* PORT_name_OUT, PORT_name_IN marks
*/
#define _PORT_DATA(pn, pfx, sfx) \
PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \
PORT##pfx##_OUT, PORT##pfx##_IN)
#define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
/* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
#define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
[gpio - (base)] = { \
.name = __stringify(gpio), \
.enum_id = data_or_mark, \
}
#define GPIO_FN(str) \
PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
/*
* PORTnCR helper macro for SH-Mobile/R-Mobile
*/
#define PORTCR(nr, reg) \
{ \
PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\
/* PULMD[1:0], handled by .set_bias() */ \
0, 0, 0, 0, \
/* IE and OE */ \
0, PORT##nr##_OUT, PORT##nr##_IN, 0, \
/* SEC, not supported */ \
0, 0, \
/* PTMD[2:0] */ \
PORT##nr##_FN0, PORT##nr##_FN1, \
PORT##nr##_FN2, PORT##nr##_FN3, \
PORT##nr##_FN4, PORT##nr##_FN5, \
PORT##nr##_FN6, PORT##nr##_FN7 \
} \
}
/*
* GPIO number helper macro for R-Car
*/
#define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin))
#endif /* __SH_PFC_H */

9
drivers/serial/serial_sh.c
View File

@ -226,11 +226,14 @@ static int sh_serial_ofdata_to_platdata(struct udevice *dev)
plat->base = addr;
ret = clk_get_by_name(dev, "fck", &sh_serial_clk);
if (!ret)
plat->clk = clk_get_rate(&sh_serial_clk);
else
if (!ret) {
ret = clk_enable(&sh_serial_clk);
if (!ret)
plat->clk = clk_get_rate(&sh_serial_clk);
} else {
plat->clk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"clock", 1);
}
plat->type = dev_get_driver_data(dev);
return 0;

8
drivers/usb/host/Kconfig
View File

@ -157,14 +157,6 @@ config USB_EHCI_PCI
help
Enables support for the PCI-based EHCI controller.
config USB_EHCI_RCAR_GEN3
bool "Support for Renesas RCar M3/H3 EHCI USB controller"
depends on RCAR_GEN3
default y
---help---
Enables support for the on-chip EHCI controller on Renesas
R8A7795 and R8A7796 SoCs.
config USB_EHCI_ZYNQ
bool "Support for Xilinx Zynq on-chip EHCI USB controller"
depends on ARCH_ZYNQ

1
drivers/usb/host/Makefile
View File

@ -46,7 +46,6 @@ obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o
obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
obj-$(CONFIG_USB_EHCI_RCAR_GEN3) += ehci-rcar_gen3.o
obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
# xhci

106
drivers/usb/host/ehci-rcar_gen3.c
View File

@ -1,106 +0,0 @@
/*
* drivers/usb/host/ehci-rcar_gen3.
* This file is EHCI HCD (Host Controller Driver) for USB.
*
* Copyright (C) 2015-2017 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <errno.h>
#include <wait_bit.h>
#include <asm/io.h>
#include <usb/ehci-ci.h>
#include "ehci.h"
#define RCAR_GEN3_USB_BASE(n) (0xEE080000 + ((n) * 0x20000))
#define EHCI_USBCMD 0x120
#define CORE_SPD_RSM_TIMSET 0x30c
#define CORE_OC_TIMSET 0x310
/* Register offset */
#define AHB_OFFSET 0x200
#define BASE_HSUSB 0xE6590000
#define REG_LPSTS (BASE_HSUSB + 0x0102) /* 16bit */
#define SUSPM 0x4000
#define SUSPM_NORMAL BIT(14)
#define REG_UGCTRL2 (BASE_HSUSB + 0x0184) /* 32bit */
#define USB0SEL 0x00000030
#define USB0SEL_EHCI 0x00000010
#define SMSTPCR7 0xE615014C
#define SMSTPCR700 BIT(0) /* EHCI3 */
#define SMSTPCR701 BIT(1) /* EHCI2 */
#define SMSTPCR702 BIT(2) /* EHCI1 */
#define SMSTPCR703 BIT(3) /* EHCI0 */
#define SMSTPCR704 BIT(4) /* HSUSB */
#define AHB_PLL_RST BIT(1)
#define USBH_INTBEN BIT(2)
#define USBH_INTAEN BIT(1)
#define AHB_INT_ENABLE 0x200
#define AHB_USBCTR 0x20c
int ehci_hcd_stop(int index)
{
#if defined(CONFIG_R8A7795)
const u32 mask = SMSTPCR703 | SMSTPCR702 | SMSTPCR701 | SMSTPCR700;
#else
const u32 mask = SMSTPCR703 | SMSTPCR702;
#endif
const u32 base = RCAR_GEN3_USB_BASE(index);
int ret;
/* Reset EHCI */
setbits_le32((uintptr_t)(base + EHCI_USBCMD), CMD_RESET);
ret = wait_for_bit("ehci-rcar", (void *)(uintptr_t)base + EHCI_USBCMD,
CMD_RESET, false, 10, true);
if (ret) {
printf("ehci-rcar: reset failed (index=%i, ret=%i).\n",
index, ret);
}
setbits_le32(SMSTPCR7, BIT(3 - index));
if ((readl(SMSTPCR7) & mask) == mask)
setbits_le32(SMSTPCR7, SMSTPCR704);
return 0;
}
int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
const void __iomem *base =
(void __iomem *)(uintptr_t)RCAR_GEN3_USB_BASE(index);
struct usb_ehci *ehci = (struct usb_ehci *)(uintptr_t)base;
clrbits_le32(SMSTPCR7, BIT(3 - index));
clrbits_le32(SMSTPCR7, SMSTPCR704);
*hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength);
*hcor = (struct ehci_hcor *)((uintptr_t)*hccr +
HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
/* Enable interrupt */
setbits_le32(base + AHB_INT_ENABLE, USBH_INTBEN | USBH_INTAEN);
writel(0x014e029b, base + CORE_SPD_RSM_TIMSET);
writel(0x000209ab, base + CORE_OC_TIMSET);
/* Choice USB0SEL */
clrsetbits_le32(REG_UGCTRL2, USB0SEL, USB0SEL_EHCI);
/* Clock & Reset */
clrbits_le32(base + AHB_USBCTR, AHB_PLL_RST);
/* low power status */
clrsetbits_le16(REG_LPSTS, SUSPM, SUSPM_NORMAL);
return 0;
}

8
include/configs/rcar-gen3-common.h
View File

@ -12,10 +12,6 @@
#include <asm/arch/rmobile.h>
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_REMAKE_ELF
/* boot option */
@ -35,8 +31,6 @@
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SH_GPIO_PFC
/* console */
#define CONFIG_SYS_CBSIZE 2048
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
@ -46,7 +40,7 @@
/* MEMORY */
#define CONFIG_SYS_TEXT_BASE 0x50000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x7fff0)
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
#define DRAM_RSV_SIZE 0x08000000
#if defined(CONFIG_R8A7795)