mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-10-01 09:00:45 +09:00
Merge branch 'next' of /home/wd/git/u-boot/next
Conflicts: include/ppc4xx.h Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
commit
2e6e1772c0
@ -486,6 +486,7 @@ Stephen Williams <steve@icarus.com>
|
|||||||
|
|
||||||
Ilya Yanok <yanok@emcraft.com>
|
Ilya Yanok <yanok@emcraft.com>
|
||||||
|
|
||||||
|
mpc8308_p1m MPC8308
|
||||||
MPC8308RDB MPC8308
|
MPC8308RDB MPC8308
|
||||||
|
|
||||||
Roy Zang <tie-fei.zang@freescale.com>
|
Roy Zang <tie-fei.zang@freescale.com>
|
||||||
|
359
MAKEALL
359
MAKEALL
@ -41,39 +41,39 @@ ERR_LIST=""
|
|||||||
TOTAL_CNT=0
|
TOTAL_CNT=0
|
||||||
RC=0
|
RC=0
|
||||||
|
|
||||||
|
# Helper funcs for parsing boards.cfg
|
||||||
|
boards_by_field()
|
||||||
|
{
|
||||||
|
awk \
|
||||||
|
-v field="$1" \
|
||||||
|
-v select="$2" \
|
||||||
|
'($1 !~ /^#/ && $field == select) { print $1 }' \
|
||||||
|
boards.cfg
|
||||||
|
}
|
||||||
|
boards_by_arch() { boards_by_field 2 "$@" ; }
|
||||||
|
boards_by_cpu() { boards_by_field 3 "$@" ; }
|
||||||
|
|
||||||
#########################################################################
|
#########################################################################
|
||||||
## MPC5xx Systems
|
## MPC5xx Systems
|
||||||
#########################################################################
|
#########################################################################
|
||||||
|
|
||||||
LIST_5xx=" \
|
LIST_5xx="$(boards_by_cpu mpc5xx)"
|
||||||
cmi_mpc5xx \
|
|
||||||
"
|
|
||||||
|
|
||||||
#########################################################################
|
#########################################################################
|
||||||
## MPC5xxx Systems
|
## MPC5xxx Systems
|
||||||
#########################################################################
|
#########################################################################
|
||||||
|
|
||||||
LIST_5xxx=" \
|
LIST_5xxx="$(boards_by_cpu mpc5xxx)
|
||||||
BC3450 \
|
|
||||||
cm5200 \
|
|
||||||
cpci5200 \
|
|
||||||
digsy_mtc \
|
digsy_mtc \
|
||||||
EVAL5200 \
|
EVAL5200 \
|
||||||
fo300 \
|
fo300 \
|
||||||
galaxy5200 \
|
galaxy5200 \
|
||||||
icecube_5200 \
|
icecube_5200 \
|
||||||
inka4x0 \
|
|
||||||
ipek01 \
|
|
||||||
lite5200b \
|
lite5200b \
|
||||||
mcc200 \
|
mcc200 \
|
||||||
mecp5200 \
|
|
||||||
motionpro \
|
|
||||||
munices \
|
|
||||||
MVBC_P \
|
MVBC_P \
|
||||||
MVSMR \
|
MVSMR \
|
||||||
o2dnt \
|
|
||||||
pcm030 \
|
pcm030 \
|
||||||
pf5200 \
|
|
||||||
PM520 \
|
PM520 \
|
||||||
TB5200 \
|
TB5200 \
|
||||||
Total5200 \
|
Total5200 \
|
||||||
@ -81,62 +81,39 @@ LIST_5xxx=" \
|
|||||||
TQM5200 \
|
TQM5200 \
|
||||||
TQM5200_B \
|
TQM5200_B \
|
||||||
TQM5200S \
|
TQM5200S \
|
||||||
v38b \
|
|
||||||
"
|
"
|
||||||
|
|
||||||
#########################################################################
|
#########################################################################
|
||||||
## MPC512x Systems
|
## MPC512x Systems
|
||||||
#########################################################################
|
#########################################################################
|
||||||
|
|
||||||
LIST_512x=" \
|
LIST_512x="$(boards_by_cpu mpc512x)
|
||||||
aria \
|
|
||||||
mecp5123 \
|
|
||||||
mpc5121ads \
|
mpc5121ads \
|
||||||
pdm360ng \
|
|
||||||
"
|
"
|
||||||
|
|
||||||
#########################################################################
|
#########################################################################
|
||||||
## MPC8xx Systems
|
## MPC8xx Systems
|
||||||
#########################################################################
|
#########################################################################
|
||||||
LIST_8xx=" \
|
|
||||||
|
LIST_8xx="$(boards_by_cpu mpc8xx)
|
||||||
Adder87x \
|
Adder87x \
|
||||||
AdderII \
|
AdderII \
|
||||||
ADS860 \
|
ADS860 \
|
||||||
AMX860 \
|
|
||||||
c2mon \
|
|
||||||
CCM \
|
|
||||||
cogent_mpc8xx \
|
|
||||||
ELPT860 \
|
|
||||||
EP88x \
|
|
||||||
ESTEEM192E \
|
|
||||||
ETX094 \
|
|
||||||
FADS823 \
|
FADS823 \
|
||||||
FADS850SAR \
|
FADS850SAR \
|
||||||
FADS860T \
|
FADS860T \
|
||||||
FLAGADM \
|
|
||||||
FPS850L \
|
FPS850L \
|
||||||
GEN860T \
|
GEN860T \
|
||||||
GEN860T_SC \
|
GEN860T_SC \
|
||||||
GENIETV \
|
|
||||||
hermes \
|
|
||||||
IAD210 \
|
|
||||||
ICU862_100MHz \
|
ICU862_100MHz \
|
||||||
IP860 \
|
|
||||||
IVML24 \
|
IVML24 \
|
||||||
IVML24_128 \
|
IVML24_128 \
|
||||||
IVML24_256 \
|
IVML24_256 \
|
||||||
IVMS8 \
|
IVMS8 \
|
||||||
IVMS8_128 \
|
IVMS8_128 \
|
||||||
IVMS8_256 \
|
IVMS8_256 \
|
||||||
KUP4K \
|
|
||||||
KUP4X \
|
|
||||||
LANTEC \
|
|
||||||
lwmon \
|
|
||||||
kmsupx4 \
|
|
||||||
MBX \
|
MBX \
|
||||||
MBX860T \
|
MBX860T \
|
||||||
mgsuvd \
|
|
||||||
MHPC \
|
|
||||||
MPC86xADS \
|
MPC86xADS \
|
||||||
MPC885ADS \
|
MPC885ADS \
|
||||||
NETPHONE \
|
NETPHONE \
|
||||||
@ -145,33 +122,16 @@ LIST_8xx=" \
|
|||||||
NETTA_ISDN \
|
NETTA_ISDN \
|
||||||
NETVIA \
|
NETVIA \
|
||||||
NETVIA_V2 \
|
NETVIA_V2 \
|
||||||
NX823 \
|
|
||||||
pcu_e \
|
|
||||||
QS823 \
|
|
||||||
QS850 \
|
|
||||||
QS860T \
|
|
||||||
quantum \
|
|
||||||
R360MPI \
|
|
||||||
RBC823 \
|
|
||||||
rmu \
|
|
||||||
RPXClassic \
|
|
||||||
RPXlite \
|
|
||||||
RPXlite_DW \
|
RPXlite_DW \
|
||||||
RRvision \
|
|
||||||
SM850 \
|
|
||||||
spc1920 \
|
|
||||||
SPD823TS \
|
SPD823TS \
|
||||||
svm_sc8xx \
|
|
||||||
SXNI855T \
|
SXNI855T \
|
||||||
TK885D \
|
TK885D \
|
||||||
TOP860 \
|
|
||||||
TQM823L \
|
TQM823L \
|
||||||
TQM823L_LCD \
|
TQM823L_LCD \
|
||||||
TQM850L \
|
TQM850L \
|
||||||
TQM855L \
|
TQM855L \
|
||||||
TQM860L \
|
TQM860L \
|
||||||
TQM885D \
|
TQM885D \
|
||||||
uc100 \
|
|
||||||
v37 \
|
v37 \
|
||||||
"
|
"
|
||||||
|
|
||||||
@ -179,195 +139,98 @@ LIST_8xx=" \
|
|||||||
## PPC4xx Systems
|
## PPC4xx Systems
|
||||||
#########################################################################
|
#########################################################################
|
||||||
|
|
||||||
LIST_4xx=" \
|
LIST_4xx="$(boards_by_cpu ppc4xx)
|
||||||
acadia \
|
|
||||||
acadia_nand \
|
acadia_nand \
|
||||||
ADCIOP \
|
|
||||||
alpr \
|
|
||||||
AP1000 \
|
|
||||||
APC405 \
|
|
||||||
AR405 \
|
|
||||||
arches \
|
arches \
|
||||||
ASH405 \
|
|
||||||
bamboo \
|
|
||||||
bamboo_nand \
|
bamboo_nand \
|
||||||
bubinga \
|
|
||||||
CANBT \
|
|
||||||
canyonlands \
|
canyonlands \
|
||||||
canyonlands_nand \
|
canyonlands_nand \
|
||||||
CMS700 \
|
|
||||||
CPCI2DP \
|
|
||||||
CPCI405 \
|
CPCI405 \
|
||||||
CPCI4052 \
|
CPCI4052 \
|
||||||
CPCI405AB \
|
CPCI405AB \
|
||||||
CPCI405DT \
|
CPCI405DT \
|
||||||
CPCIISER4 \
|
|
||||||
CRAYL1 \
|
|
||||||
csb272 \
|
|
||||||
csb472 \
|
|
||||||
DASA_SIM \
|
|
||||||
devconcenter \
|
devconcenter \
|
||||||
dlvision \
|
|
||||||
DP405 \
|
|
||||||
DU405 \
|
|
||||||
DU440 \
|
|
||||||
ebony \
|
|
||||||
ERIC \
|
|
||||||
fx12mm \
|
fx12mm \
|
||||||
G2000 \
|
|
||||||
gdppc440etx \
|
|
||||||
glacier \
|
glacier \
|
||||||
haleakala \
|
haleakala \
|
||||||
haleakala_nand \
|
haleakala_nand \
|
||||||
hcu4 \
|
hcu4 \
|
||||||
hcu5 \
|
hcu5 \
|
||||||
HH405 \
|
|
||||||
HUB405 \
|
|
||||||
icon \
|
|
||||||
intip \
|
intip \
|
||||||
JSE \
|
|
||||||
KAREF \
|
|
||||||
katmai \
|
|
||||||
kilauea \
|
kilauea \
|
||||||
kilauea_nand \
|
kilauea_nand \
|
||||||
korat \
|
|
||||||
luan \
|
|
||||||
lwmon5 \
|
|
||||||
makalu \
|
|
||||||
mcu25 \
|
mcu25 \
|
||||||
METROBOX \
|
|
||||||
MIP405 \
|
|
||||||
MIP405T \
|
MIP405T \
|
||||||
ML2 \
|
|
||||||
ml507 \
|
ml507 \
|
||||||
ml507_flash \
|
ml507_flash \
|
||||||
neo \
|
|
||||||
ocotea \
|
|
||||||
OCRTC \
|
OCRTC \
|
||||||
ORSG \
|
ORSG \
|
||||||
p3p440 \
|
|
||||||
PCI405 \
|
|
||||||
pcs440ep \
|
|
||||||
PIP405 \
|
|
||||||
PLU405 \
|
|
||||||
PMC405 \
|
|
||||||
PMC405DE \
|
|
||||||
PMC440 \
|
|
||||||
PPChameleonEVB \
|
PPChameleonEVB \
|
||||||
quad100hd \
|
|
||||||
rainier \
|
rainier \
|
||||||
redwood \
|
|
||||||
sbc405 \
|
|
||||||
sc3 \
|
|
||||||
sequoia \
|
sequoia \
|
||||||
sequoia_nand \
|
sequoia_nand \
|
||||||
t3corp \
|
|
||||||
taihu \
|
|
||||||
taishan \
|
|
||||||
v5fx30teval \
|
v5fx30teval \
|
||||||
v5fx30teval_flash \
|
v5fx30teval_flash \
|
||||||
VOH405 \
|
|
||||||
VOM405 \
|
|
||||||
W7OLMC \
|
W7OLMC \
|
||||||
W7OLMG \
|
W7OLMG \
|
||||||
walnut \
|
walnut \
|
||||||
WUH405 \
|
|
||||||
xilinx-ppc440-generic \
|
xilinx-ppc440-generic \
|
||||||
xilinx-ppc440-generic_flash \
|
xilinx-ppc440-generic_flash \
|
||||||
XPEDITE1000 \
|
|
||||||
yellowstone \
|
yellowstone \
|
||||||
yosemite \
|
yosemite \
|
||||||
yucca \
|
|
||||||
zeus \
|
|
||||||
"
|
"
|
||||||
|
|
||||||
#########################################################################
|
#########################################################################
|
||||||
## MPC8220 Systems
|
## MPC8220 Systems
|
||||||
#########################################################################
|
#########################################################################
|
||||||
|
|
||||||
LIST_8220=" \
|
LIST_8220="$(boards_by_cpu mpc8220)"
|
||||||
Alaska8220 \
|
|
||||||
Yukon8220 \
|
|
||||||
"
|
|
||||||
|
|
||||||
#########################################################################
|
#########################################################################
|
||||||
## MPC824x Systems
|
## MPC824x Systems
|
||||||
#########################################################################
|
#########################################################################
|
||||||
|
|
||||||
LIST_824x=" \
|
LIST_824x="$(boards_by_cpu mpc824x)
|
||||||
A3000 \
|
|
||||||
barco \
|
|
||||||
BMW \
|
|
||||||
CPC45 \
|
CPC45 \
|
||||||
CU824 \
|
|
||||||
debris \
|
|
||||||
eXalion \
|
eXalion \
|
||||||
HIDDEN_DRAGON \
|
|
||||||
IDS8247 \
|
IDS8247 \
|
||||||
linkstation_HGLAN \
|
linkstation_HGLAN \
|
||||||
MOUSSE \
|
|
||||||
MUSENKI \
|
|
||||||
MVBLUE \
|
|
||||||
OXC \
|
|
||||||
PN62 \
|
|
||||||
Sandpoint8240 \
|
Sandpoint8240 \
|
||||||
Sandpoint8245 \
|
Sandpoint8245 \
|
||||||
sbc8240 \
|
|
||||||
utx8245 \
|
|
||||||
"
|
"
|
||||||
|
|
||||||
#########################################################################
|
#########################################################################
|
||||||
## MPC8260 Systems (includes 8250, 8255 etc.)
|
## MPC8260 Systems (includes 8250, 8255 etc.)
|
||||||
#########################################################################
|
#########################################################################
|
||||||
|
|
||||||
LIST_8260=" \
|
LIST_8260="$(boards_by_cpu mpc8260)
|
||||||
atc \
|
|
||||||
cogent_mpc8260 \
|
cogent_mpc8260 \
|
||||||
CPU86 \
|
CPU86 \
|
||||||
CPU87 \
|
CPU87 \
|
||||||
ep8248 \
|
ep8248 \
|
||||||
ep8260 \
|
|
||||||
ep82xxm \
|
|
||||||
gw8260 \
|
|
||||||
hymod \
|
|
||||||
IPHASE4539 \
|
|
||||||
ISPAN \
|
ISPAN \
|
||||||
mgcoge \
|
|
||||||
MPC8260ADS \
|
MPC8260ADS \
|
||||||
MPC8266ADS \
|
|
||||||
MPC8272ADS \
|
MPC8272ADS \
|
||||||
PM826 \
|
PM826 \
|
||||||
PM828 \
|
PM828 \
|
||||||
ppmc8260 \
|
|
||||||
Rattler8248 \
|
Rattler8248 \
|
||||||
RPXsuper \
|
|
||||||
rsdproto \
|
|
||||||
sacsng \
|
|
||||||
sbc8260 \
|
|
||||||
SCM \
|
|
||||||
TQM8260_AC \
|
TQM8260_AC \
|
||||||
TQM8260_AD \
|
TQM8260_AD \
|
||||||
TQM8260_AE \
|
TQM8260_AE \
|
||||||
TQM8272 \
|
|
||||||
ZPC1900 \
|
|
||||||
"
|
"
|
||||||
|
|
||||||
#########################################################################
|
#########################################################################
|
||||||
## MPC83xx Systems (includes 8349, etc.)
|
## MPC83xx Systems (includes 8349, etc.)
|
||||||
#########################################################################
|
#########################################################################
|
||||||
|
|
||||||
LIST_83xx=" \
|
LIST_83xx="$(boards_by_cpu mpc83xx)
|
||||||
caddy2 \
|
caddy2 \
|
||||||
kmeter1 \
|
|
||||||
MPC8308RDB \
|
|
||||||
MPC8313ERDB_33 \
|
MPC8313ERDB_33 \
|
||||||
MPC8313ERDB_NAND_66 \
|
MPC8313ERDB_NAND_66 \
|
||||||
MPC8315ERDB \
|
MPC8315ERDB \
|
||||||
MPC8315ERDB_NAND \
|
MPC8315ERDB_NAND \
|
||||||
MPC8323ERDB \
|
|
||||||
MPC832XEMDS \
|
MPC832XEMDS \
|
||||||
MPC832XEMDS_ATM \
|
MPC832XEMDS_ATM \
|
||||||
MPC8349EMDS \
|
|
||||||
MPC8349ITX \
|
MPC8349ITX \
|
||||||
MPC8349ITXGP \
|
MPC8349ITXGP \
|
||||||
MPC8360EMDS \
|
MPC8360EMDS \
|
||||||
@ -375,12 +238,8 @@ LIST_83xx=" \
|
|||||||
MPC8360ERDK_33 \
|
MPC8360ERDK_33 \
|
||||||
MPC8360ERDK_66 \
|
MPC8360ERDK_66 \
|
||||||
MPC837XEMDS \
|
MPC837XEMDS \
|
||||||
MPC837XERDB \
|
|
||||||
MVBLM7 \
|
|
||||||
sbc8349 \
|
sbc8349 \
|
||||||
SIMPC8313_LP \
|
SIMPC8313_LP \
|
||||||
TQM834x \
|
|
||||||
ve8313 \
|
|
||||||
vme8349 \
|
vme8349 \
|
||||||
"
|
"
|
||||||
|
|
||||||
@ -389,27 +248,21 @@ LIST_83xx=" \
|
|||||||
## MPC85xx Systems (includes 8540, 8560 etc.)
|
## MPC85xx Systems (includes 8540, 8560 etc.)
|
||||||
#########################################################################
|
#########################################################################
|
||||||
|
|
||||||
LIST_85xx=" \
|
LIST_85xx="$(boards_by_cpu mpc85xx)
|
||||||
ATUM8548 \
|
|
||||||
MPC8536DS \
|
MPC8536DS \
|
||||||
MPC8536DS_NAND \
|
MPC8536DS_NAND \
|
||||||
MPC8536DS_SDCARD \
|
MPC8536DS_SDCARD \
|
||||||
MPC8536DS_SPIFLASH \
|
MPC8536DS_SPIFLASH \
|
||||||
MPC8536DS_36BIT \
|
MPC8536DS_36BIT \
|
||||||
MPC8540ADS \
|
|
||||||
MPC8540EVAL \
|
MPC8540EVAL \
|
||||||
MPC8541CDS \
|
MPC8541CDS \
|
||||||
MPC8544DS \
|
|
||||||
MPC8548CDS \
|
MPC8548CDS \
|
||||||
MPC8555CDS \
|
MPC8555CDS \
|
||||||
MPC8560ADS \
|
|
||||||
MPC8568MDS \
|
|
||||||
MPC8569MDS \
|
MPC8569MDS \
|
||||||
MPC8569MDS_ATM \
|
MPC8569MDS_ATM \
|
||||||
MPC8569MDS_NAND \
|
MPC8569MDS_NAND \
|
||||||
MPC8572DS \
|
MPC8572DS \
|
||||||
MPC8572DS_36BIT \
|
MPC8572DS_36BIT \
|
||||||
P1022DS \
|
|
||||||
P2020DS \
|
P2020DS \
|
||||||
P2020DS_36BIT \
|
P2020DS_36BIT \
|
||||||
P1011RDB \
|
P1011RDB \
|
||||||
@ -428,9 +281,6 @@ LIST_85xx=" \
|
|||||||
P2020RDB_NAND \
|
P2020RDB_NAND \
|
||||||
P2020RDB_SDCARD \
|
P2020RDB_SDCARD \
|
||||||
P2020RDB_SPIFLASH \
|
P2020RDB_SPIFLASH \
|
||||||
P4080DS \
|
|
||||||
PM854 \
|
|
||||||
PM856 \
|
|
||||||
sbc8540 \
|
sbc8540 \
|
||||||
sbc8548 \
|
sbc8548 \
|
||||||
sbc8548_PCI_33 \
|
sbc8548_PCI_33 \
|
||||||
@ -438,8 +288,6 @@ LIST_85xx=" \
|
|||||||
sbc8548_PCI_33_PCIE \
|
sbc8548_PCI_33_PCIE \
|
||||||
sbc8548_PCI_66_PCIE \
|
sbc8548_PCI_66_PCIE \
|
||||||
sbc8560 \
|
sbc8560 \
|
||||||
socrates \
|
|
||||||
stxgp3 \
|
|
||||||
stxssa \
|
stxssa \
|
||||||
TQM8540 \
|
TQM8540 \
|
||||||
TQM8541 \
|
TQM8541 \
|
||||||
@ -448,20 +296,15 @@ LIST_85xx=" \
|
|||||||
TQM8548_BE \
|
TQM8548_BE \
|
||||||
TQM8555 \
|
TQM8555 \
|
||||||
TQM8560 \
|
TQM8560 \
|
||||||
XPEDITE5200 \
|
|
||||||
XPEDITE5370 \
|
|
||||||
"
|
"
|
||||||
|
|
||||||
#########################################################################
|
#########################################################################
|
||||||
## MPC86xx Systems
|
## MPC86xx Systems
|
||||||
#########################################################################
|
#########################################################################
|
||||||
|
|
||||||
LIST_86xx=" \
|
LIST_86xx="$(boards_by_cpu mpc86xx)
|
||||||
MPC8610HPCD \
|
|
||||||
MPC8641HPCN_36BIT \
|
MPC8641HPCN_36BIT \
|
||||||
MPC8641HPCN \
|
MPC8641HPCN \
|
||||||
sbc8641d \
|
|
||||||
XPEDITE5170 \
|
|
||||||
"
|
"
|
||||||
|
|
||||||
#########################################################################
|
#########################################################################
|
||||||
@ -524,13 +367,7 @@ LIST_ppc=" \
|
|||||||
## StrongARM Systems
|
## StrongARM Systems
|
||||||
#########################################################################
|
#########################################################################
|
||||||
|
|
||||||
LIST_SA=" \
|
LIST_SA="$(boards_by_cpu sa1100)"
|
||||||
assabet \
|
|
||||||
dnp1110 \
|
|
||||||
gcplus \
|
|
||||||
lart \
|
|
||||||
shannon \
|
|
||||||
"
|
|
||||||
|
|
||||||
#########################################################################
|
#########################################################################
|
||||||
## ARM7 Systems
|
## ARM7 Systems
|
||||||
@ -706,35 +543,14 @@ LIST_at91=" \
|
|||||||
## Xscale Systems
|
## Xscale Systems
|
||||||
#########################################################################
|
#########################################################################
|
||||||
|
|
||||||
LIST_pxa=" \
|
LIST_pxa="$(boards_by_cpu pxa)
|
||||||
cerf250 \
|
|
||||||
colibri_pxa270 \
|
|
||||||
cradle \
|
|
||||||
csb226 \
|
|
||||||
delta \
|
|
||||||
innokom \
|
|
||||||
lubbock \
|
|
||||||
pleb2 \
|
|
||||||
polaris \
|
polaris \
|
||||||
pxa255_idp \
|
|
||||||
trizepsiv \
|
trizepsiv \
|
||||||
vpac270_nor \
|
vpac270_nor \
|
||||||
vpac270_onenand \
|
vpac270_onenand \
|
||||||
wepep250 \
|
|
||||||
xaeniax \
|
|
||||||
xm250 \
|
|
||||||
xsengine \
|
|
||||||
zipitz2 \
|
|
||||||
zylonite \
|
|
||||||
"
|
"
|
||||||
|
|
||||||
LIST_ixp=" \
|
LIST_ixp="$(boards_by_cpu ixp)
|
||||||
actux1 \
|
|
||||||
actux2 \
|
|
||||||
actux3 \
|
|
||||||
actux4 \
|
|
||||||
ixdp425 \
|
|
||||||
ixdpg425 \
|
|
||||||
pdnb3 \
|
pdnb3 \
|
||||||
scpu \
|
scpu \
|
||||||
"
|
"
|
||||||
@ -818,21 +634,15 @@ LIST_mips_el=" \
|
|||||||
## i386 Systems
|
## i386 Systems
|
||||||
#########################################################################
|
#########################################################################
|
||||||
|
|
||||||
LIST_I486=" \
|
LIST_x86="$(boards_by_arch i386)
|
||||||
sc520_eNET \
|
sc520_eNET \
|
||||||
"
|
"
|
||||||
|
|
||||||
LIST_x86=" \
|
|
||||||
${LIST_I486} \
|
|
||||||
"
|
|
||||||
|
|
||||||
#########################################################################
|
#########################################################################
|
||||||
## Nios-II Systems
|
## Nios-II Systems
|
||||||
#########################################################################
|
#########################################################################
|
||||||
|
|
||||||
LIST_nios2=" \
|
LIST_nios2="$(boards_by_arch nios2)
|
||||||
PCI5441 \
|
|
||||||
PK1C20 \
|
|
||||||
nios2-generic \
|
nios2-generic \
|
||||||
"
|
"
|
||||||
|
|
||||||
@ -840,86 +650,39 @@ LIST_nios2=" \
|
|||||||
## MicroBlaze Systems
|
## MicroBlaze Systems
|
||||||
#########################################################################
|
#########################################################################
|
||||||
|
|
||||||
LIST_microblaze=" \
|
LIST_microblaze="$(boards_by_arch microblaze)"
|
||||||
microblaze-generic \
|
|
||||||
"
|
|
||||||
|
|
||||||
#########################################################################
|
#########################################################################
|
||||||
## ColdFire Systems
|
## ColdFire Systems
|
||||||
#########################################################################
|
#########################################################################
|
||||||
|
|
||||||
LIST_coldfire=" \
|
LIST_coldfire="$(boards_by_arch m68k)
|
||||||
astro_mcf5373l \
|
astro_mcf5373l \
|
||||||
cobra5272 \
|
cobra5272 \
|
||||||
EB+MCF-EV123 \
|
EB+MCF-EV123 \
|
||||||
EB+MCF-EV123_internal \
|
EB+MCF-EV123_internal \
|
||||||
idmr \
|
|
||||||
M5208EVBE \
|
|
||||||
M52277EVB \
|
M52277EVB \
|
||||||
M5235EVB \
|
M5235EVB \
|
||||||
M5249EVB \
|
|
||||||
M5253DEMO \
|
|
||||||
M5253EVBE \
|
|
||||||
M5271EVB \
|
|
||||||
M5272C3 \
|
|
||||||
M5275EVB \
|
|
||||||
M5282EVB \
|
|
||||||
M53017EVB \
|
|
||||||
M5329AFEE \
|
M5329AFEE \
|
||||||
M5373EVB \
|
M5373EVB \
|
||||||
M54451EVB \
|
M54451EVB \
|
||||||
M54455EVB \
|
M54455EVB \
|
||||||
M5475AFE \
|
M5475AFE \
|
||||||
M5485AFE \
|
M5485AFE \
|
||||||
TASREG \
|
|
||||||
"
|
"
|
||||||
|
|
||||||
#########################################################################
|
#########################################################################
|
||||||
## AVR32 Systems
|
## AVR32 Systems
|
||||||
#########################################################################
|
#########################################################################
|
||||||
|
|
||||||
LIST_avr32=" \
|
LIST_avr32="$(boards_by_arch avr32)"
|
||||||
atstk1002 \
|
|
||||||
atstk1003 \
|
|
||||||
atstk1004 \
|
|
||||||
atstk1006 \
|
|
||||||
atngw100 \
|
|
||||||
favr-32-ezkit \
|
|
||||||
hammerhead \
|
|
||||||
mimc200 \
|
|
||||||
"
|
|
||||||
|
|
||||||
#########################################################################
|
#########################################################################
|
||||||
## Blackfin Systems
|
## Blackfin Systems
|
||||||
#########################################################################
|
#########################################################################
|
||||||
|
|
||||||
LIST_blackfin=" \
|
LIST_blackfin="$(boards_by_arch blackfin)
|
||||||
bf518f-ezbrd \
|
bf527-ezkit-v2
|
||||||
bf526-ezbrd \
|
|
||||||
bf527-ad7160-eval \
|
|
||||||
bf527-ezkit \
|
|
||||||
bf527-ezkit-v2 \
|
|
||||||
bf533-ezkit \
|
|
||||||
bf533-stamp \
|
|
||||||
bf537-minotaur \
|
|
||||||
bf537-pnav \
|
|
||||||
bf537-srv1 \
|
|
||||||
bf537-stamp \
|
|
||||||
bf538f-ezkit \
|
|
||||||
bf548-ezkit \
|
|
||||||
bf561-acvilon \
|
|
||||||
bf561-ezkit \
|
|
||||||
blackstamp \
|
|
||||||
cm-bf527 \
|
|
||||||
cm-bf533 \
|
|
||||||
cm-bf537e \
|
|
||||||
cm-bf537u \
|
|
||||||
cm-bf548 \
|
|
||||||
cm-bf561 \
|
|
||||||
ibf-dsp561 \
|
|
||||||
ip04 \
|
|
||||||
tcm-bf518 \
|
|
||||||
tcm-bf537 \
|
|
||||||
"
|
"
|
||||||
|
|
||||||
#########################################################################
|
#########################################################################
|
||||||
@ -956,12 +719,7 @@ LIST_sh=" \
|
|||||||
## SPARC Systems
|
## SPARC Systems
|
||||||
#########################################################################
|
#########################################################################
|
||||||
|
|
||||||
LIST_sparc="gr_xc3s_1500 gr_cpci_ax2000 gr_ep2s60 grsim grsim_leon2"
|
LIST_sparc="$(boards_by_arch sparc)"
|
||||||
|
|
||||||
#-----------------------------------------------------------------------
|
|
||||||
|
|
||||||
#----- for now, just run PowerPC by default -----
|
|
||||||
[ $# = 0 ] && set $LIST_powerpc
|
|
||||||
|
|
||||||
#-----------------------------------------------------------------------
|
#-----------------------------------------------------------------------
|
||||||
|
|
||||||
@ -969,7 +727,7 @@ build_target() {
|
|||||||
target=$1
|
target=$1
|
||||||
|
|
||||||
${MAKE} distclean >/dev/null
|
${MAKE} distclean >/dev/null
|
||||||
${MAKE} ${target}_config
|
${MAKE} -s ${target}_config
|
||||||
|
|
||||||
${MAKE} ${JOBS} all 2>&1 >${LOG_DIR}/$target.MAKELOG \
|
${MAKE} ${JOBS} all 2>&1 >${LOG_DIR}/$target.MAKELOG \
|
||||||
| tee ${LOG_DIR}/$target.ERR
|
| tee ${LOG_DIR}/$target.ERR
|
||||||
@ -991,6 +749,22 @@ build_target() {
|
|||||||
${CROSS_COMPILE}size ${BUILD_DIR}/u-boot \
|
${CROSS_COMPILE}size ${BUILD_DIR}/u-boot \
|
||||||
| tee -a ${LOG_DIR}/$target.MAKELOG
|
| tee -a ${LOG_DIR}/$target.MAKELOG
|
||||||
}
|
}
|
||||||
|
build_targets() {
|
||||||
|
for t in "$@" ; do
|
||||||
|
# If a LIST_xxx var exists, use it. But avoid variable
|
||||||
|
# expansion in the eval when a board name contains certain
|
||||||
|
# characters that the shell interprets.
|
||||||
|
case ${t} in
|
||||||
|
*[-+=]*) list= ;;
|
||||||
|
*) list=$(eval echo '${LIST_'$t'}') ;;
|
||||||
|
esac
|
||||||
|
if [ -n "${list}" ] ; then
|
||||||
|
build_targets ${list}
|
||||||
|
else
|
||||||
|
build_target ${t}
|
||||||
|
fi
|
||||||
|
done
|
||||||
|
}
|
||||||
|
|
||||||
#-----------------------------------------------------------------------
|
#-----------------------------------------------------------------------
|
||||||
|
|
||||||
@ -1007,27 +781,8 @@ print_stats() {
|
|||||||
}
|
}
|
||||||
|
|
||||||
#-----------------------------------------------------------------------
|
#-----------------------------------------------------------------------
|
||||||
for arg in $@
|
|
||||||
do
|
#----- for now, just run PowerPC by default -----
|
||||||
case "$arg" in
|
[ $# = 0 ] && set -- powerpc
|
||||||
arm|SA|ARM7|ARM9|ARM10|ARM11|ARMV7|at91|ixp|pxa \
|
|
||||||
|avr32 \
|
build_targets "$@"
|
||||||
|blackfin \
|
|
||||||
|coldfire \
|
|
||||||
|microblaze \
|
|
||||||
|mips|mips_el \
|
|
||||||
|nios2 \
|
|
||||||
|ppc|powerpc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx|TSEC \
|
|
||||||
|sh|sh2|sh3|sh4 \
|
|
||||||
|sparc \
|
|
||||||
|x86|I486 \
|
|
||||||
)
|
|
||||||
for target in `eval echo '$LIST_'${arg}`
|
|
||||||
do
|
|
||||||
build_target ${target}
|
|
||||||
done
|
|
||||||
;;
|
|
||||||
*) build_target ${arg}
|
|
||||||
;;
|
|
||||||
esac
|
|
||||||
done
|
|
||||||
|
30
Makefile
30
Makefile
@ -404,14 +404,8 @@ $(TIMESTAMP_FILE):
|
|||||||
@LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"' > $@
|
@LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"' > $@
|
||||||
@LC_ALL=C date +'#define U_BOOT_TIME "%T"' >> $@
|
@LC_ALL=C date +'#define U_BOOT_TIME "%T"' >> $@
|
||||||
|
|
||||||
gdbtools:
|
|
||||||
$(MAKE) -C tools/gdb all || exit 1
|
|
||||||
|
|
||||||
updater:
|
updater:
|
||||||
$(MAKE) -C tools/updater all || exit 1
|
$(MAKE) -C tools/updater all
|
||||||
|
|
||||||
env:
|
|
||||||
$(MAKE) -C tools/env all MTD_VERSION=${MTD_VERSION} || exit 1
|
|
||||||
|
|
||||||
# Explicitly make _depend in subdirs containing multiple targets to prevent
|
# Explicitly make _depend in subdirs containing multiple targets to prevent
|
||||||
# parallel sub-makes creating .depend files simultaneously.
|
# parallel sub-makes creating .depend files simultaneously.
|
||||||
@ -466,17 +460,22 @@ $(obj)include/autoconf.mk: $(obj)include/config.h
|
|||||||
else # !config.mk
|
else # !config.mk
|
||||||
all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \
|
all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \
|
||||||
$(obj)u-boot.img $(obj)u-boot.dis $(obj)u-boot \
|
$(obj)u-boot.img $(obj)u-boot.dis $(obj)u-boot \
|
||||||
$(filter-out tools,$(SUBDIRS)) $(TIMESTAMP_FILE) $(VERSION_FILE) gdbtools \
|
$(filter-out tools,$(SUBDIRS)) $(TIMESTAMP_FILE) $(VERSION_FILE) \
|
||||||
updater env depend dep tags ctags etags cscope $(obj)System.map:
|
updater depend dep tags ctags etags cscope $(obj)System.map:
|
||||||
@echo "System not configured - see README" >&2
|
@echo "System not configured - see README" >&2
|
||||||
@ exit 1
|
@ exit 1
|
||||||
|
|
||||||
tools:
|
tools:
|
||||||
$(MAKE) -C tools
|
$(MAKE) -C $@ all
|
||||||
tools-all:
|
|
||||||
$(MAKE) -C tools HOST_TOOLS_ALL=y
|
|
||||||
endif # config.mk
|
endif # config.mk
|
||||||
|
|
||||||
|
easylogo env gdb:
|
||||||
|
$(MAKE) -C tools/$@ all MTD_VERSION=${MTD_VERSION}
|
||||||
|
gdbtools: gdb
|
||||||
|
|
||||||
|
tools-all: easylogo env gdb
|
||||||
|
$(MAKE) -C tools HOST_TOOLS_ALL=y
|
||||||
|
|
||||||
.PHONY : CHANGELOG
|
.PHONY : CHANGELOG
|
||||||
CHANGELOG:
|
CHANGELOG:
|
||||||
git log --no-merges U-Boot-1_1_5.. | \
|
git log --no-merges U-Boot-1_1_5.. | \
|
||||||
@ -494,8 +493,9 @@ unconfig:
|
|||||||
%_config:: unconfig
|
%_config:: unconfig
|
||||||
@$(MKCONFIG) -A $(@:_config=)
|
@$(MKCONFIG) -A $(@:_config=)
|
||||||
|
|
||||||
##%: %_config
|
sinclude .boards.depend
|
||||||
## $(MAKE)
|
.boards.depend: boards.cfg
|
||||||
|
awk '(NF && $$1 !~ /^#/) { print $$1 ": " $$1 "_config; $$(MAKE)" }' $< > $@
|
||||||
|
|
||||||
#
|
#
|
||||||
# Functions to generate common board directory names
|
# Functions to generate common board directory names
|
||||||
@ -2475,7 +2475,7 @@ clean:
|
|||||||
| xargs rm -f
|
| xargs rm -f
|
||||||
|
|
||||||
clobber: clean
|
clobber: clean
|
||||||
@find $(OBJTREE) -type f \( -name .depend \
|
@find $(OBJTREE) -type f \( -name '*.depend' \
|
||||||
-o -name '*.srec' -o -name '*.bin' -o -name u-boot.img \) \
|
-o -name '*.srec' -o -name '*.bin' -o -name u-boot.img \) \
|
||||||
-print0 \
|
-print0 \
|
||||||
| xargs -0 rm -f
|
| xargs -0 rm -f
|
||||||
|
27
README
27
README
@ -536,25 +536,6 @@ The following options need to be configured:
|
|||||||
must be defined, to setup the maximum idle timeout for
|
must be defined, to setup the maximum idle timeout for
|
||||||
the SMC.
|
the SMC.
|
||||||
|
|
||||||
- Interrupt driven serial port input:
|
|
||||||
CONFIG_SERIAL_SOFTWARE_FIFO
|
|
||||||
|
|
||||||
PPC405GP only.
|
|
||||||
Use an interrupt handler for receiving data on the
|
|
||||||
serial port. It also enables using hardware handshake
|
|
||||||
(RTS/CTS) and UART's built-in FIFO. Set the number of
|
|
||||||
bytes the interrupt driven input buffer should have.
|
|
||||||
|
|
||||||
Leave undefined to disable this feature, including
|
|
||||||
disable the buffer and hardware handshake.
|
|
||||||
|
|
||||||
- Console UART Number:
|
|
||||||
CONFIG_UART1_CONSOLE
|
|
||||||
|
|
||||||
AMCC PPC4xx only.
|
|
||||||
If defined internal UART1 (and not UART0) is used
|
|
||||||
as default U-Boot console.
|
|
||||||
|
|
||||||
- Boot Delay: CONFIG_BOOTDELAY - in seconds
|
- Boot Delay: CONFIG_BOOTDELAY - in seconds
|
||||||
Delay before automatically booting the default image;
|
Delay before automatically booting the default image;
|
||||||
set to -1 to disable autoboot.
|
set to -1 to disable autoboot.
|
||||||
@ -2368,6 +2349,14 @@ Configuration Settings:
|
|||||||
on high Ethernet traffic.
|
on high Ethernet traffic.
|
||||||
Defaults to 4 if not defined.
|
Defaults to 4 if not defined.
|
||||||
|
|
||||||
|
- CONFIG_ENV_MAX_ENTRIES
|
||||||
|
|
||||||
|
Maximum number of entries in the hash table that is used
|
||||||
|
internally to store the environment settings. The default
|
||||||
|
setting is supposed to be generous and should work in most
|
||||||
|
cases. This setting can be used to tune behaviour; see
|
||||||
|
lib/hashtable.c for details.
|
||||||
|
|
||||||
The following definitions that deal with the placement and management
|
The following definitions that deal with the placement and management
|
||||||
of environment data (variable area); in general, we support the
|
of environment data (variable area); in general, we support the
|
||||||
following configurations:
|
following configurations:
|
||||||
|
@ -33,6 +33,14 @@ STANDALONE_LOAD_ADDR = 0xc100000
|
|||||||
endif
|
endif
|
||||||
endif
|
endif
|
||||||
|
|
||||||
|
ifndef CONFIG_SYS_ARM_WITHOUT_RELOC
|
||||||
|
# needed for relocation
|
||||||
|
PLATFORM_RELFLAGS += -fPIC
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifdef CONFIG_SYS_ARM_WITHOUT_RELOC
|
||||||
|
PLATFORM_CPPFLAGS += -DCONFIG_SYS_ARM_WITHOUT_RELOC
|
||||||
|
endif
|
||||||
PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__
|
PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__
|
||||||
|
|
||||||
# Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb:
|
# Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb:
|
||||||
|
@ -85,12 +85,15 @@ _end_vect:
|
|||||||
*************************************************************************
|
*************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
.globl _TEXT_BASE
|
||||||
_TEXT_BASE:
|
_TEXT_BASE:
|
||||||
.word TEXT_BASE
|
.word TEXT_BASE
|
||||||
|
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
.globl _armboot_start
|
.globl _armboot_start
|
||||||
_armboot_start:
|
_armboot_start:
|
||||||
.word _start
|
.word _start
|
||||||
|
#endif
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* These are defined in the board-specific linker script.
|
* These are defined in the board-specific linker script.
|
||||||
@ -103,6 +106,32 @@ _bss_start:
|
|||||||
_bss_end:
|
_bss_end:
|
||||||
.word _end
|
.word _end
|
||||||
|
|
||||||
|
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
|
.globl _datarel_start
|
||||||
|
_datarel_start:
|
||||||
|
.word __datarel_start
|
||||||
|
|
||||||
|
.globl _datarelrolocal_start
|
||||||
|
_datarelrolocal_start:
|
||||||
|
.word __datarelrolocal_start
|
||||||
|
|
||||||
|
.globl _datarellocal_start
|
||||||
|
_datarellocal_start:
|
||||||
|
.word __datarellocal_start
|
||||||
|
|
||||||
|
.globl _datarelro_start
|
||||||
|
_datarelro_start:
|
||||||
|
.word __datarelro_start
|
||||||
|
|
||||||
|
.globl _got_start
|
||||||
|
_got_start:
|
||||||
|
.word __got_start
|
||||||
|
|
||||||
|
.globl _got_end
|
||||||
|
_got_end:
|
||||||
|
.word __got_end
|
||||||
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_USE_IRQ
|
#ifdef CONFIG_USE_IRQ
|
||||||
/* IRQ stack memory (calculated at run-time) */
|
/* IRQ stack memory (calculated at run-time) */
|
||||||
.globl IRQ_STACK_START
|
.globl IRQ_STACK_START
|
||||||
@ -115,6 +144,164 @@ FIQ_STACK_START:
|
|||||||
.word 0x0badc0de
|
.word 0x0badc0de
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
|
/* IRQ stack memory (calculated at run-time) + 8 bytes */
|
||||||
|
.globl IRQ_STACK_START_IN
|
||||||
|
IRQ_STACK_START_IN:
|
||||||
|
.word 0x0badc0de
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
|
/*
|
||||||
|
* the actual reset code
|
||||||
|
*/
|
||||||
|
|
||||||
|
reset:
|
||||||
|
/*
|
||||||
|
* set the cpu to SVC32 mode
|
||||||
|
*/
|
||||||
|
mrs r0,cpsr
|
||||||
|
bic r0,r0,#0x1f
|
||||||
|
orr r0,r0,#0xd3
|
||||||
|
msr cpsr,r0
|
||||||
|
|
||||||
|
#ifdef CONFIG_OMAP2420H4
|
||||||
|
/* Copy vectors to mask ROM indirect addr */
|
||||||
|
adr r0, _start /* r0 <- current position of code */
|
||||||
|
add r0, r0, #4 /* skip reset vector */
|
||||||
|
mov r2, #64 /* r2 <- size to copy */
|
||||||
|
add r2, r0, r2 /* r2 <- source end address */
|
||||||
|
mov r1, #SRAM_OFFSET0 /* build vect addr */
|
||||||
|
mov r3, #SRAM_OFFSET1
|
||||||
|
add r1, r1, r3
|
||||||
|
mov r3, #SRAM_OFFSET2
|
||||||
|
add r1, r1, r3
|
||||||
|
next:
|
||||||
|
ldmia r0!, {r3-r10} /* copy from source address [r0] */
|
||||||
|
stmia r1!, {r3-r10} /* copy to target address [r1] */
|
||||||
|
cmp r0, r2 /* until source end address [r2] */
|
||||||
|
bne next /* loop until equal */
|
||||||
|
bl cpy_clk_code /* put dpll adjust code behind vectors */
|
||||||
|
#endif
|
||||||
|
/* the mask ROM code should have PLL and others stable */
|
||||||
|
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||||
|
bl cpu_init_crit
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Set stackpointer in internal RAM to call board_init_f */
|
||||||
|
call_board_init_f:
|
||||||
|
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
|
||||||
|
ldr r0,=0x00000000
|
||||||
|
|
||||||
|
#ifdef CONFIG_NAND_SPL
|
||||||
|
bl nand_boot
|
||||||
|
#else
|
||||||
|
#ifdef CONFIG_ONENAND_IPL
|
||||||
|
bl start_oneboot
|
||||||
|
#else
|
||||||
|
bl board_init_f
|
||||||
|
#endif /* CONFIG_ONENAND_IPL */
|
||||||
|
#endif /* CONFIG_NAND_SPL */
|
||||||
|
|
||||||
|
/*------------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* void relocate_code (addr_sp, gd, addr_moni)
|
||||||
|
*
|
||||||
|
* This "function" does not return, instead it continues in RAM
|
||||||
|
* after relocating the monitor code.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
.globl relocate_code
|
||||||
|
relocate_code:
|
||||||
|
mov r4, r0 /* save addr_sp */
|
||||||
|
mov r5, r1 /* save addr of gd */
|
||||||
|
mov r6, r2 /* save addr of destination */
|
||||||
|
mov r7, r2 /* save addr of destination */
|
||||||
|
|
||||||
|
/* Set up the stack */
|
||||||
|
stack_setup:
|
||||||
|
mov sp, r4
|
||||||
|
|
||||||
|
adr r0, _start
|
||||||
|
ldr r2, _TEXT_BASE
|
||||||
|
ldr r3, _bss_start
|
||||||
|
sub r2, r3, r2 /* r2 <- size of armboot */
|
||||||
|
add r2, r0, r2 /* r2 <- source end address */
|
||||||
|
cmp r0, r6
|
||||||
|
beq clear_bss
|
||||||
|
|
||||||
|
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
|
||||||
|
copy_loop:
|
||||||
|
ldmia r0!, {r9-r10} /* copy from source address [r0] */
|
||||||
|
stmia r6!, {r9-r10} /* copy to target address [r1] */
|
||||||
|
cmp r0, r2 /* until source end addreee [r2] */
|
||||||
|
ble copy_loop
|
||||||
|
|
||||||
|
#ifndef CONFIG_PRELOADER
|
||||||
|
/* fix got entries */
|
||||||
|
ldr r1, _TEXT_BASE
|
||||||
|
mov r0, r7 /* reloc addr */
|
||||||
|
ldr r2, _got_start /* addr in Flash */
|
||||||
|
ldr r3, _got_end /* addr in Flash */
|
||||||
|
sub r3, r3, r1
|
||||||
|
add r3, r3, r0
|
||||||
|
sub r2, r2, r1
|
||||||
|
add r2, r2, r0
|
||||||
|
|
||||||
|
fixloop:
|
||||||
|
ldr r4, [r2]
|
||||||
|
sub r4, r4, r1
|
||||||
|
add r4, r4, r0
|
||||||
|
str r4, [r2]
|
||||||
|
add r2, r2, #4
|
||||||
|
cmp r2, r3
|
||||||
|
bne fixloop
|
||||||
|
#endif
|
||||||
|
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
|
||||||
|
|
||||||
|
clear_bss:
|
||||||
|
#ifndef CONFIG_PRELOADER
|
||||||
|
ldr r0, _bss_start
|
||||||
|
ldr r1, _bss_end
|
||||||
|
ldr r3, _TEXT_BASE /* Text base */
|
||||||
|
mov r4, r7 /* reloc addr */
|
||||||
|
sub r0, r0, r3
|
||||||
|
add r0, r0, r4
|
||||||
|
sub r1, r1, r3
|
||||||
|
add r1, r1, r4
|
||||||
|
mov r2, #0x00000000 /* clear */
|
||||||
|
|
||||||
|
clbss_l:str r2, [r0] /* clear loop... */
|
||||||
|
add r0, r0, #4
|
||||||
|
cmp r0, r1
|
||||||
|
bne clbss_l
|
||||||
|
#endif /* #ifndef CONFIG_PRELOADER */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We are done. Do not return, instead branch to second part of board
|
||||||
|
* initialization, now running from RAM.
|
||||||
|
*/
|
||||||
|
#ifdef CONFIG_NAND_SPL
|
||||||
|
ldr pc, _nand_boot
|
||||||
|
|
||||||
|
_nand_boot: .word nand_boot
|
||||||
|
#else
|
||||||
|
jump_2_ram:
|
||||||
|
ldr r0, _TEXT_BASE
|
||||||
|
ldr r2, _board_init_r
|
||||||
|
sub r2, r2, r0
|
||||||
|
add r2, r2, r7 /* position from board_init_r in RAM */
|
||||||
|
/* setup parameters for board_init_r */
|
||||||
|
mov r0, r5 /* gd_t */
|
||||||
|
mov r1, r7 /* dest_addr */
|
||||||
|
/* jump to it ... */
|
||||||
|
mov lr, r2
|
||||||
|
mov pc, lr
|
||||||
|
|
||||||
|
_board_init_r: .word board_init_r
|
||||||
|
#endif
|
||||||
|
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||||
/*
|
/*
|
||||||
* the actual reset code
|
* the actual reset code
|
||||||
*/
|
*/
|
||||||
@ -211,6 +398,8 @@ _start_armboot: .word start_armboot
|
|||||||
#endif /* CONFIG_ONENAND_IPL */
|
#endif /* CONFIG_ONENAND_IPL */
|
||||||
#endif /* CONFIG_NAND_SPL */
|
#endif /* CONFIG_NAND_SPL */
|
||||||
|
|
||||||
|
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
*************************************************************************
|
*************************************************************************
|
||||||
*
|
*
|
||||||
@ -295,9 +484,13 @@ cpu_init_crit:
|
|||||||
sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
|
sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
|
||||||
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
|
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
|
||||||
|
|
||||||
|
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
|
ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack
|
||||||
|
#else
|
||||||
ldr r2, _armboot_start
|
ldr r2, _armboot_start
|
||||||
sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
|
sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
|
||||||
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
|
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
|
||||||
|
#endif
|
||||||
ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
|
ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
|
||||||
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
|
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
|
||||||
|
|
||||||
@ -328,9 +521,13 @@ cpu_init_crit:
|
|||||||
.endm
|
.endm
|
||||||
|
|
||||||
.macro get_bad_stack
|
.macro get_bad_stack
|
||||||
|
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
|
ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode)
|
||||||
|
#else
|
||||||
ldr r13, _armboot_start @ setup our mode stack (enter in banked mode)
|
ldr r13, _armboot_start @ setup our mode stack (enter in banked mode)
|
||||||
sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
|
sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
|
||||||
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ move to reserved a couple spots for abort stack
|
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ move to reserved a couple spots for abort stack
|
||||||
|
#endif
|
||||||
|
|
||||||
str lr, [r13] @ save caller lr in position 0 of saved stack
|
str lr, [r13] @ save caller lr in position 0 of saved stack
|
||||||
mrs lr, spsr @ get the spsr
|
mrs lr, spsr @ get the spsr
|
||||||
@ -346,9 +543,13 @@ cpu_init_crit:
|
|||||||
.macro get_bad_stack_swi
|
.macro get_bad_stack_swi
|
||||||
sub r13, r13, #4 @ space on current stack for scratch reg.
|
sub r13, r13, #4 @ space on current stack for scratch reg.
|
||||||
str r0, [r13] @ save R0's value.
|
str r0, [r13] @ save R0's value.
|
||||||
|
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
|
ldr r0, IRQ_STACK_START_IN @ get data regions start
|
||||||
|
#else
|
||||||
ldr r0, _armboot_start @ get data regions start
|
ldr r0, _armboot_start @ get data regions start
|
||||||
sub r0, r0, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
|
sub r0, r0, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
|
||||||
sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ move past gbl and a couple spots for abort stack
|
sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ move past gbl and a couple spots for abort stack
|
||||||
|
#endif
|
||||||
str lr, [r0] @ save caller lr in position 0 of saved stack
|
str lr, [r0] @ save caller lr in position 0 of saved stack
|
||||||
mrs r0, spsr @ get the spsr
|
mrs r0, spsr @ get the spsr
|
||||||
str lr, [r0, #4] @ save spsr in position 1 of saved stack
|
str lr, [r0, #4] @ save spsr in position 1 of saved stack
|
||||||
@ -439,6 +640,11 @@ fiq:
|
|||||||
.align 5
|
.align 5
|
||||||
.global arm1136_cache_flush
|
.global arm1136_cache_flush
|
||||||
arm1136_cache_flush:
|
arm1136_cache_flush:
|
||||||
|
#if !defined(CONFIG_SYS_NO_ICACHE)
|
||||||
mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
|
mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
|
||||||
|
#endif
|
||||||
|
#if !defined(CONFIG_SYS_NO_DCACHE)
|
||||||
|
mcr p15, 0, r1, c7, c14, 0 @ invalidate D cache
|
||||||
|
#endif
|
||||||
mov pc, lr @ back to caller
|
mov pc, lr @ back to caller
|
||||||
#endif /* CONFIG_PRELOADER */
|
#endif /* CONFIG_PRELOADER */
|
||||||
|
@ -47,11 +47,23 @@ SECTIONS
|
|||||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||||
|
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
.data : { *(.data) }
|
.data : {
|
||||||
|
*(.data)
|
||||||
|
__datarel_start = .;
|
||||||
|
*(.data.rel)
|
||||||
|
__datarelrolocal_start = .;
|
||||||
|
*(.data.rel.ro.local)
|
||||||
|
__datarellocal_start = .;
|
||||||
|
*(.data.rel.local)
|
||||||
|
__datarelro_start = .;
|
||||||
|
*(.data.rel.ro)
|
||||||
|
}
|
||||||
|
|
||||||
|
__got_start = .;
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
.got : { *(.got) }
|
.got : { *(.got) }
|
||||||
|
|
||||||
|
__got_end = .;
|
||||||
. = .;
|
. = .;
|
||||||
__u_boot_cmd_start = .;
|
__u_boot_cmd_start = .;
|
||||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||||
|
@ -95,6 +95,7 @@ _end_vect:
|
|||||||
*************************************************************************
|
*************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
.globl _TEXT_BASE
|
||||||
_TEXT_BASE:
|
_TEXT_BASE:
|
||||||
.word TEXT_BASE
|
.word TEXT_BASE
|
||||||
|
|
||||||
@ -106,9 +107,11 @@ _TEXT_BASE:
|
|||||||
_TEXT_PHY_BASE:
|
_TEXT_PHY_BASE:
|
||||||
.word CONFIG_SYS_PHY_UBOOT_BASE
|
.word CONFIG_SYS_PHY_UBOOT_BASE
|
||||||
|
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
.globl _armboot_start
|
.globl _armboot_start
|
||||||
_armboot_start:
|
_armboot_start:
|
||||||
.word _start
|
.word _start
|
||||||
|
#endif
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* These are defined in the board-specific linker script.
|
* These are defined in the board-specific linker script.
|
||||||
@ -121,6 +124,275 @@ _bss_start:
|
|||||||
_bss_end:
|
_bss_end:
|
||||||
.word _end
|
.word _end
|
||||||
|
|
||||||
|
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
|
/* IRQ stack memory (calculated at run-time) + 8 bytes */
|
||||||
|
.globl IRQ_STACK_START_IN
|
||||||
|
IRQ_STACK_START_IN:
|
||||||
|
.word 0x0badc0de
|
||||||
|
|
||||||
|
.globl _datarel_start
|
||||||
|
_datarel_start:
|
||||||
|
.word __datarel_start
|
||||||
|
|
||||||
|
.globl _datarelrolocal_start
|
||||||
|
_datarelrolocal_start:
|
||||||
|
.word __datarelrolocal_start
|
||||||
|
|
||||||
|
.globl _datarellocal_start
|
||||||
|
_datarellocal_start:
|
||||||
|
.word __datarellocal_start
|
||||||
|
|
||||||
|
.globl _datarelro_start
|
||||||
|
_datarelro_start:
|
||||||
|
.word __datarelro_start
|
||||||
|
|
||||||
|
.globl _got_start
|
||||||
|
_got_start:
|
||||||
|
.word __got_start
|
||||||
|
|
||||||
|
.globl _got_end
|
||||||
|
_got_end:
|
||||||
|
.word __got_end
|
||||||
|
|
||||||
|
/*
|
||||||
|
* the actual reset code
|
||||||
|
*/
|
||||||
|
|
||||||
|
reset:
|
||||||
|
/*
|
||||||
|
* set the cpu to SVC32 mode
|
||||||
|
*/
|
||||||
|
mrs r0, cpsr
|
||||||
|
bic r0, r0, #0x3f
|
||||||
|
orr r0, r0, #0xd3
|
||||||
|
msr cpsr, r0
|
||||||
|
|
||||||
|
/*
|
||||||
|
*************************************************************************
|
||||||
|
*
|
||||||
|
* CPU_init_critical registers
|
||||||
|
*
|
||||||
|
* setup important registers
|
||||||
|
* setup memory timing
|
||||||
|
*
|
||||||
|
*************************************************************************
|
||||||
|
*/
|
||||||
|
/*
|
||||||
|
* we do sys-critical inits only at reboot,
|
||||||
|
* not when booting from ram!
|
||||||
|
*/
|
||||||
|
cpu_init_crit:
|
||||||
|
/*
|
||||||
|
* When booting from NAND - it has definitely been a reset, so, no need
|
||||||
|
* to flush caches and disable the MMU
|
||||||
|
*/
|
||||||
|
#ifndef CONFIG_NAND_SPL
|
||||||
|
/*
|
||||||
|
* flush v4 I/D caches
|
||||||
|
*/
|
||||||
|
mov r0, #0
|
||||||
|
mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
|
||||||
|
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* disable MMU stuff and caches
|
||||||
|
*/
|
||||||
|
mrc p15, 0, r0, c1, c0, 0
|
||||||
|
bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
|
||||||
|
bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
|
||||||
|
orr r0, r0, #0x00000002 @ set bit 2 (A) Align
|
||||||
|
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
|
||||||
|
|
||||||
|
/* Prepare to disable the MMU */
|
||||||
|
adr r2, mmu_disable_phys
|
||||||
|
sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - TEXT_BASE)
|
||||||
|
b mmu_disable
|
||||||
|
|
||||||
|
.align 5
|
||||||
|
/* Run in a single cache-line */
|
||||||
|
mmu_disable:
|
||||||
|
mcr p15, 0, r0, c1, c0, 0
|
||||||
|
nop
|
||||||
|
nop
|
||||||
|
mov pc, r2
|
||||||
|
mmu_disable_phys:
|
||||||
|
|
||||||
|
#ifdef CONFIG_DISABLE_TCM
|
||||||
|
/*
|
||||||
|
* Disable the TCMs
|
||||||
|
*/
|
||||||
|
mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */
|
||||||
|
cmp r0, #0
|
||||||
|
beq skip_tcmdisable
|
||||||
|
mov r1, #0
|
||||||
|
mov r2, #1
|
||||||
|
tst r0, r2
|
||||||
|
mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/
|
||||||
|
tst r0, r2, LSL #16
|
||||||
|
mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/
|
||||||
|
skip_tcmdisable:
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_PERIPORT_REMAP
|
||||||
|
/* Peri port setup */
|
||||||
|
ldr r0, =CONFIG_PERIPORT_BASE
|
||||||
|
orr r0, r0, #CONFIG_PERIPORT_SIZE
|
||||||
|
mcr p15,0,r0,c15,c2,4
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Go setup Memory and board specific bits prior to relocation.
|
||||||
|
*/
|
||||||
|
bl lowlevel_init /* go setup pll,mux,memory */
|
||||||
|
|
||||||
|
/* Set stackpointer in internal RAM to call board_init_f */
|
||||||
|
call_board_init_f:
|
||||||
|
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
|
||||||
|
ldr r0,=0x00000000
|
||||||
|
bl board_init_f
|
||||||
|
|
||||||
|
/*------------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* void relocate_code (addr_sp, gd, addr_moni)
|
||||||
|
*
|
||||||
|
* This "function" does not return, instead it continues in RAM
|
||||||
|
* after relocating the monitor code.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
.globl relocate_code
|
||||||
|
relocate_code:
|
||||||
|
mov r4, r0 /* save addr_sp */
|
||||||
|
mov r5, r1 /* save addr of gd */
|
||||||
|
mov r6, r2 /* save addr of destination */
|
||||||
|
mov r7, r2 /* save addr of destination */
|
||||||
|
|
||||||
|
/* Set up the stack */
|
||||||
|
stack_setup:
|
||||||
|
mov sp, r4
|
||||||
|
|
||||||
|
adr r0, _start
|
||||||
|
ldr r2, _TEXT_BASE
|
||||||
|
ldr r3, _bss_start
|
||||||
|
sub r2, r3, r2 /* r2 <- size of armboot */
|
||||||
|
add r2, r0, r2 /* r2 <- source end address */
|
||||||
|
cmp r0, r6
|
||||||
|
beq clear_bss
|
||||||
|
|
||||||
|
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
|
||||||
|
copy_loop:
|
||||||
|
ldmia r0!, {r9-r10} /* copy from source address [r0] */
|
||||||
|
stmia r6!, {r9-r10} /* copy to target address [r1] */
|
||||||
|
cmp r0, r2 /* until source end addreee [r2] */
|
||||||
|
ble copy_loop
|
||||||
|
|
||||||
|
#ifndef CONFIG_PRELOADER
|
||||||
|
/* fix got entries */
|
||||||
|
ldr r1, _TEXT_BASE /* Text base */
|
||||||
|
mov r0, r7 /* reloc addr */
|
||||||
|
ldr r2, _got_start /* addr in Flash */
|
||||||
|
ldr r3, _got_end /* addr in Flash */
|
||||||
|
sub r3, r3, r1
|
||||||
|
add r3, r3, r0
|
||||||
|
sub r2, r2, r1
|
||||||
|
add r2, r2, r0
|
||||||
|
|
||||||
|
fixloop:
|
||||||
|
ldr r4, [r2]
|
||||||
|
sub r4, r4, r1
|
||||||
|
add r4, r4, r0
|
||||||
|
str r4, [r2]
|
||||||
|
add r2, r2, #4
|
||||||
|
cmp r2, r3
|
||||||
|
bne fixloop
|
||||||
|
#endif
|
||||||
|
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
|
||||||
|
|
||||||
|
#ifdef CONFIG_ENABLE_MMU
|
||||||
|
enable_mmu:
|
||||||
|
/* enable domain access */
|
||||||
|
ldr r5, =0x0000ffff
|
||||||
|
mcr p15, 0, r5, c3, c0, 0 /* load domain access register */
|
||||||
|
|
||||||
|
/* Set the TTB register */
|
||||||
|
ldr r0, _mmu_table_base
|
||||||
|
ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE
|
||||||
|
ldr r2, =0xfff00000
|
||||||
|
bic r0, r0, r2
|
||||||
|
orr r1, r0, r1
|
||||||
|
mcr p15, 0, r1, c2, c0, 0
|
||||||
|
|
||||||
|
/* Enable the MMU */
|
||||||
|
mrc p15, 0, r0, c1, c0, 0
|
||||||
|
orr r0, r0, #1 /* Set CR_M to enable MMU */
|
||||||
|
|
||||||
|
/* Prepare to enable the MMU */
|
||||||
|
adr r1, skip_hw_init
|
||||||
|
and r1, r1, #0x3fc
|
||||||
|
ldr r2, _TEXT_BASE
|
||||||
|
ldr r3, =0xfff00000
|
||||||
|
and r2, r2, r3
|
||||||
|
orr r2, r2, r1
|
||||||
|
b mmu_enable
|
||||||
|
|
||||||
|
.align 5
|
||||||
|
/* Run in a single cache-line */
|
||||||
|
mmu_enable:
|
||||||
|
|
||||||
|
mcr p15, 0, r0, c1, c0, 0
|
||||||
|
nop
|
||||||
|
nop
|
||||||
|
mov pc, r2
|
||||||
|
skip_hw_init:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
clear_bss:
|
||||||
|
#ifndef CONFIG_PRELOADER
|
||||||
|
ldr r0, _bss_start
|
||||||
|
ldr r1, _bss_end
|
||||||
|
ldr r3, _TEXT_BASE /* Text base */
|
||||||
|
mov r4, r7 /* reloc addr */
|
||||||
|
sub r0, r0, r3
|
||||||
|
add r0, r0, r4
|
||||||
|
sub r1, r1, r3
|
||||||
|
add r1, r1, r4
|
||||||
|
mov r2, #0x00000000 /* clear */
|
||||||
|
|
||||||
|
clbss_l:str r2, [r0] /* clear loop... */
|
||||||
|
add r0, r0, #4
|
||||||
|
cmp r0, r1
|
||||||
|
bne clbss_l
|
||||||
|
|
||||||
|
bl coloured_LED_init
|
||||||
|
bl red_LED_on
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We are done. Do not return, instead branch to second part of board
|
||||||
|
* initialization, now running from RAM.
|
||||||
|
*/
|
||||||
|
#ifdef CONFIG_NAND_SPL
|
||||||
|
ldr pc, _nand_boot
|
||||||
|
|
||||||
|
_nand_boot: .word nand_boot
|
||||||
|
#else
|
||||||
|
ldr r0, _TEXT_BASE
|
||||||
|
ldr r2, _board_init_r
|
||||||
|
sub r2, r2, r0
|
||||||
|
add r2, r2, r7 /* position from board_init_r in RAM */
|
||||||
|
/* setup parameters for board_init_r */
|
||||||
|
mov r0, r5 /* gd_t */
|
||||||
|
mov r1, r7 /* dest_addr */
|
||||||
|
/* jump to it ... */
|
||||||
|
mov lr, r2
|
||||||
|
mov pc, lr
|
||||||
|
|
||||||
|
_board_init_r: .word board_init_r
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* the actual reset code
|
* the actual reset code
|
||||||
*/
|
*/
|
||||||
@ -299,6 +571,8 @@ _start_armboot:
|
|||||||
/* .word nand_boot*/
|
/* .word nand_boot*/
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||||
|
|
||||||
#ifdef CONFIG_ENABLE_MMU
|
#ifdef CONFIG_ENABLE_MMU
|
||||||
_mmu_table_base:
|
_mmu_table_base:
|
||||||
.word mmu_table
|
.word mmu_table
|
||||||
@ -385,10 +659,14 @@ phy_last_jump:
|
|||||||
/* Save user registers (now in svc mode) r0-r12 */
|
/* Save user registers (now in svc mode) r0-r12 */
|
||||||
stmia sp, {r0 - r12}
|
stmia sp, {r0 - r12}
|
||||||
|
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
ldr r2, _armboot_start
|
ldr r2, _armboot_start
|
||||||
sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
|
sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
|
||||||
/* set base 2 words into abort stack */
|
/* set base 2 words into abort stack */
|
||||||
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)
|
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)
|
||||||
|
#else
|
||||||
|
ldr r2, IRQ_STACK_START_IN
|
||||||
|
#endif
|
||||||
/* get values for "aborted" pc and cpsr (into parm regs) */
|
/* get values for "aborted" pc and cpsr (into parm regs) */
|
||||||
ldmia r2, {r2 - r3}
|
ldmia r2, {r2 - r3}
|
||||||
/* grab pointer to old stack */
|
/* grab pointer to old stack */
|
||||||
@ -403,12 +681,16 @@ phy_last_jump:
|
|||||||
.endm
|
.endm
|
||||||
|
|
||||||
.macro get_bad_stack
|
.macro get_bad_stack
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
/* setup our mode stack (enter in banked mode) */
|
/* setup our mode stack (enter in banked mode) */
|
||||||
ldr r13, _armboot_start
|
ldr r13, _armboot_start
|
||||||
/* move past malloc pool */
|
/* move past malloc pool */
|
||||||
sub r13, r13, #(CONFIG_SYS_MALLOC_LEN)
|
sub r13, r13, #(CONFIG_SYS_MALLOC_LEN)
|
||||||
/* move to reserved a couple spots for abort stack */
|
/* move to reserved a couple spots for abort stack */
|
||||||
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE + 8)
|
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE + 8)
|
||||||
|
#else
|
||||||
|
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
|
||||||
|
#endif
|
||||||
|
|
||||||
/* save caller lr in position 0 of saved stack */
|
/* save caller lr in position 0 of saved stack */
|
||||||
str lr, [r13]
|
str lr, [r13]
|
||||||
@ -433,12 +715,16 @@ phy_last_jump:
|
|||||||
sub r13, r13, #4
|
sub r13, r13, #4
|
||||||
/* save R0's value. */
|
/* save R0's value. */
|
||||||
str r0, [r13]
|
str r0, [r13]
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
/* get data regions start */
|
/* get data regions start */
|
||||||
ldr r0, _armboot_start
|
ldr r0, _armboot_start
|
||||||
/* move past malloc pool */
|
/* move past malloc pool */
|
||||||
sub r0, r0, #(CONFIG_SYS_MALLOC_LEN)
|
sub r0, r0, #(CONFIG_SYS_MALLOC_LEN)
|
||||||
/* move past gbl and a couple spots for abort stack */
|
/* move past gbl and a couple spots for abort stack */
|
||||||
sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE + 8)
|
sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE + 8)
|
||||||
|
#else
|
||||||
|
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
|
||||||
|
#endif
|
||||||
/* save caller lr in position 0 of saved stack */
|
/* save caller lr in position 0 of saved stack */
|
||||||
str lr, [r0]
|
str lr, [r0]
|
||||||
/* get the spsr */
|
/* get the spsr */
|
||||||
|
@ -39,11 +39,23 @@ SECTIONS
|
|||||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||||
|
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
.data : { *(.data) }
|
.data : {
|
||||||
|
*(.data)
|
||||||
|
__datarel_start = .;
|
||||||
|
*(.data.rel)
|
||||||
|
__datarelrolocal_start = .;
|
||||||
|
*(.data.rel.ro.local)
|
||||||
|
__datarellocal_start = .;
|
||||||
|
*(.data.rel.local)
|
||||||
|
__datarelro_start = .;
|
||||||
|
*(.data.rel.ro)
|
||||||
|
}
|
||||||
|
|
||||||
|
__got_start = .;
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
.got : { *(.got) }
|
.got : { *(.got) }
|
||||||
|
|
||||||
|
__got_end = .;
|
||||||
. = .;
|
. = .;
|
||||||
__u_boot_cmd_start = .;
|
__u_boot_cmd_start = .;
|
||||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||||
|
@ -75,12 +75,15 @@ _fiq: .word fiq
|
|||||||
*************************************************************************
|
*************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
.globl _TEXT_BASE
|
||||||
_TEXT_BASE:
|
_TEXT_BASE:
|
||||||
.word TEXT_BASE
|
.word TEXT_BASE
|
||||||
|
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
.globl _armboot_start
|
.globl _armboot_start
|
||||||
_armboot_start:
|
_armboot_start:
|
||||||
.word _start
|
.word _start
|
||||||
|
#endif
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* These are defined in the board-specific linker script.
|
* These are defined in the board-specific linker script.
|
||||||
@ -105,6 +108,163 @@ FIQ_STACK_START:
|
|||||||
.word 0x0badc0de
|
.word 0x0badc0de
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
|
/* IRQ stack memory (calculated at run-time) + 8 bytes */
|
||||||
|
.globl IRQ_STACK_START_IN
|
||||||
|
IRQ_STACK_START_IN:
|
||||||
|
.word 0x0badc0de
|
||||||
|
|
||||||
|
.globl _datarel_start
|
||||||
|
_datarel_start:
|
||||||
|
.word __datarel_start
|
||||||
|
|
||||||
|
.globl _datarelrolocal_start
|
||||||
|
_datarelrolocal_start:
|
||||||
|
.word __datarelrolocal_start
|
||||||
|
|
||||||
|
.globl _datarellocal_start
|
||||||
|
_datarellocal_start:
|
||||||
|
.word __datarellocal_start
|
||||||
|
|
||||||
|
.globl _datarelro_start
|
||||||
|
_datarelro_start:
|
||||||
|
.word __datarelro_start
|
||||||
|
|
||||||
|
.globl _got_start
|
||||||
|
_got_start:
|
||||||
|
.word __got_start
|
||||||
|
|
||||||
|
.globl _got_end
|
||||||
|
_got_end:
|
||||||
|
.word __got_end
|
||||||
|
|
||||||
|
/*
|
||||||
|
* the actual reset code
|
||||||
|
*/
|
||||||
|
|
||||||
|
reset:
|
||||||
|
/*
|
||||||
|
* set the cpu to SVC32 mode
|
||||||
|
*/
|
||||||
|
mrs r0,cpsr
|
||||||
|
bic r0,r0,#0x1f
|
||||||
|
orr r0,r0,#0xd3
|
||||||
|
msr cpsr,r0
|
||||||
|
|
||||||
|
/*
|
||||||
|
* we do sys-critical inits only at reboot,
|
||||||
|
* not when booting from ram!
|
||||||
|
*/
|
||||||
|
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||||
|
bl cpu_init_crit
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_LPC2292
|
||||||
|
bl lowlevel_init
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Set stackpointer in internal RAM to call board_init_f */
|
||||||
|
call_board_init_f:
|
||||||
|
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
|
||||||
|
ldr r0,=0x00000000
|
||||||
|
bl board_init_f
|
||||||
|
|
||||||
|
/*------------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* void relocate_code (addr_sp, gd, addr_moni)
|
||||||
|
*
|
||||||
|
* This "function" does not return, instead it continues in RAM
|
||||||
|
* after relocating the monitor code.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
.globl relocate_code
|
||||||
|
relocate_code:
|
||||||
|
mov r4, r0 /* save addr_sp */
|
||||||
|
mov r5, r1 /* save addr of gd */
|
||||||
|
mov r6, r2 /* save addr of destination */
|
||||||
|
mov r7, r2 /* save addr of destination */
|
||||||
|
|
||||||
|
/* Set up the stack */
|
||||||
|
stack_setup:
|
||||||
|
mov sp, r4
|
||||||
|
|
||||||
|
adr r0, _start
|
||||||
|
ldr r2, _TEXT_BASE
|
||||||
|
ldr r3, _bss_start
|
||||||
|
sub r2, r3, r2 /* r2 <- size of armboot */
|
||||||
|
add r2, r0, r2 /* r2 <- source end address */
|
||||||
|
cmp r0, r6
|
||||||
|
beq clear_bss
|
||||||
|
|
||||||
|
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
|
||||||
|
copy_loop:
|
||||||
|
ldmia r0!, {r9-r10} /* copy from source address [r0] */
|
||||||
|
stmia r6!, {r9-r10} /* copy to target address [r1] */
|
||||||
|
cmp r0, r2 /* until source end addreee [r2] */
|
||||||
|
ble copy_loop
|
||||||
|
|
||||||
|
#ifndef CONFIG_PRELOADER
|
||||||
|
/* fix got entries */
|
||||||
|
ldr r1, _TEXT_BASE /* Text base */
|
||||||
|
mov r0, r7 /* reloc addr */
|
||||||
|
ldr r2, _got_start /* addr in Flash */
|
||||||
|
ldr r3, _got_end /* addr in Flash */
|
||||||
|
sub r3, r3, r1
|
||||||
|
add r3, r3, r0
|
||||||
|
sub r2, r2, r1
|
||||||
|
add r2, r2, r0
|
||||||
|
|
||||||
|
fixloop:
|
||||||
|
ldr r4, [r2]
|
||||||
|
sub r4, r4, r1
|
||||||
|
add r4, r4, r0
|
||||||
|
str r4, [r2]
|
||||||
|
add r2, r2, #4
|
||||||
|
cmp r2, r3
|
||||||
|
bne fixloop
|
||||||
|
#endif
|
||||||
|
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
|
||||||
|
|
||||||
|
clear_bss:
|
||||||
|
#ifndef CONFIG_PRELOADER
|
||||||
|
ldr r0, _bss_start
|
||||||
|
ldr r1, _bss_end
|
||||||
|
ldr r3, _TEXT_BASE /* Text base */
|
||||||
|
mov r4, r7 /* reloc addr */
|
||||||
|
sub r0, r0, r3
|
||||||
|
add r0, r0, r4
|
||||||
|
sub r1, r1, r3
|
||||||
|
add r1, r1, r4
|
||||||
|
mov r2, #0x00000000 /* clear */
|
||||||
|
|
||||||
|
clbss_l:str r2, [r0] /* clear loop... */
|
||||||
|
add r0, r0, #4
|
||||||
|
cmp r0, r1
|
||||||
|
bne clbss_l
|
||||||
|
|
||||||
|
bl coloured_LED_init
|
||||||
|
bl red_LED_on
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We are done. Do not return, instead branch to second part of board
|
||||||
|
* initialization, now running from RAM.
|
||||||
|
*/
|
||||||
|
ldr r0, _TEXT_BASE
|
||||||
|
ldr r2, _board_init_r
|
||||||
|
sub r2, r2, r0
|
||||||
|
add r2, r2, r7 /* position from board_init_r in RAM */
|
||||||
|
/* setup parameters for board_init_r */
|
||||||
|
mov r0, r5 /* gd_t */
|
||||||
|
mov r1, r7 /* dest_addr */
|
||||||
|
/* jump to it ... */
|
||||||
|
mov lr, r2
|
||||||
|
mov pc, lr
|
||||||
|
|
||||||
|
_board_init_r: .word board_init_r
|
||||||
|
|
||||||
|
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* the actual reset code
|
* the actual reset code
|
||||||
@ -188,6 +348,8 @@ clbss_l:str r2, [r0] /* clear loop... */
|
|||||||
|
|
||||||
_start_armboot: .word start_armboot
|
_start_armboot: .word start_armboot
|
||||||
|
|
||||||
|
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
*************************************************************************
|
*************************************************************************
|
||||||
*
|
*
|
||||||
@ -444,9 +606,13 @@ lock_loop:
|
|||||||
stmia sp, {r0 - r12} @ Calling r0-r12
|
stmia sp, {r0 - r12} @ Calling r0-r12
|
||||||
add r8, sp, #S_PC
|
add r8, sp, #S_PC
|
||||||
|
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
ldr r2, _armboot_start
|
ldr r2, _armboot_start
|
||||||
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
||||||
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
|
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
|
||||||
|
#else
|
||||||
|
ldr r2, IRQ_STACK_START_IN
|
||||||
|
#endif
|
||||||
ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
|
ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
|
||||||
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
|
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
|
||||||
|
|
||||||
@ -477,9 +643,13 @@ lock_loop:
|
|||||||
.endm
|
.endm
|
||||||
|
|
||||||
.macro get_bad_stack
|
.macro get_bad_stack
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
ldr r13, _armboot_start @ setup our mode stack
|
ldr r13, _armboot_start @ setup our mode stack
|
||||||
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
||||||
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
|
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
|
||||||
|
#else
|
||||||
|
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
|
||||||
|
#endif
|
||||||
|
|
||||||
str lr, [r13] @ save caller lr / spsr
|
str lr, [r13] @ save caller lr / spsr
|
||||||
mrs lr, spsr
|
mrs lr, spsr
|
||||||
|
@ -39,11 +39,23 @@ SECTIONS
|
|||||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||||
|
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
.data : { *(.data) }
|
.data : {
|
||||||
|
*(.data)
|
||||||
|
__datarel_start = .;
|
||||||
|
*(.data.rel)
|
||||||
|
__datarelrolocal_start = .;
|
||||||
|
*(.data.rel.ro.local)
|
||||||
|
__datarellocal_start = .;
|
||||||
|
*(.data.rel.local)
|
||||||
|
__datarelro_start = .;
|
||||||
|
*(.data.rel.ro)
|
||||||
|
}
|
||||||
|
|
||||||
|
__got_start = .;
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
.got : { *(.got) }
|
.got : { *(.got) }
|
||||||
|
|
||||||
|
__got_end = .;
|
||||||
. = .;
|
. = .;
|
||||||
__u_boot_cmd_start = .;
|
__u_boot_cmd_start = .;
|
||||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||||
|
@ -70,12 +70,15 @@ _fiq: .word fiq
|
|||||||
*************************************************************************
|
*************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
.globl _TEXT_BASE
|
||||||
_TEXT_BASE:
|
_TEXT_BASE:
|
||||||
.word TEXT_BASE
|
.word TEXT_BASE
|
||||||
|
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
.globl _armboot_start
|
.globl _armboot_start
|
||||||
_armboot_start:
|
_armboot_start:
|
||||||
.word _start
|
.word _start
|
||||||
|
#endif
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* These are defined in the board-specific linker script.
|
* These are defined in the board-specific linker script.
|
||||||
@ -100,7 +103,219 @@ FIQ_STACK_START:
|
|||||||
.word 0x0badc0de
|
.word 0x0badc0de
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
|
/* IRQ stack memory (calculated at run-time) + 8 bytes */
|
||||||
|
.globl IRQ_STACK_START_IN
|
||||||
|
IRQ_STACK_START_IN:
|
||||||
|
.word 0x0badc0de
|
||||||
|
|
||||||
|
.globl _datarel_start
|
||||||
|
_datarel_start:
|
||||||
|
.word __datarel_start
|
||||||
|
|
||||||
|
.globl _datarelrolocal_start
|
||||||
|
_datarelrolocal_start:
|
||||||
|
.word __datarelrolocal_start
|
||||||
|
|
||||||
|
.globl _datarellocal_start
|
||||||
|
_datarellocal_start:
|
||||||
|
.word __datarellocal_start
|
||||||
|
|
||||||
|
.globl _datarelro_start
|
||||||
|
_datarelro_start:
|
||||||
|
.word __datarelro_start
|
||||||
|
|
||||||
|
.globl _got_start
|
||||||
|
_got_start:
|
||||||
|
.word __got_start
|
||||||
|
|
||||||
|
.globl _got_end
|
||||||
|
_got_end:
|
||||||
|
.word __got_end
|
||||||
|
|
||||||
|
/*
|
||||||
|
* the actual start code
|
||||||
|
*/
|
||||||
|
|
||||||
|
start_code:
|
||||||
|
/*
|
||||||
|
* set the cpu to SVC32 mode
|
||||||
|
*/
|
||||||
|
mrs r0, cpsr
|
||||||
|
bic r0, r0, #0x1f
|
||||||
|
orr r0, r0, #0xd3
|
||||||
|
msr cpsr, r0
|
||||||
|
|
||||||
|
bl coloured_LED_init
|
||||||
|
bl red_LED_on
|
||||||
|
|
||||||
|
#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
|
||||||
|
/*
|
||||||
|
* relocate exception table
|
||||||
|
*/
|
||||||
|
ldr r0, =_start
|
||||||
|
ldr r1, =0x0
|
||||||
|
mov r2, #16
|
||||||
|
copyex:
|
||||||
|
subs r2, r2, #1
|
||||||
|
ldr r3, [r0], #4
|
||||||
|
str r3, [r1], #4
|
||||||
|
bne copyex
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_S3C24X0
|
||||||
|
/* turn off the watchdog */
|
||||||
|
|
||||||
|
# if defined(CONFIG_S3C2400)
|
||||||
|
# define pWTCON 0x15300000
|
||||||
|
# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
|
||||||
|
# define CLKDIVN 0x14800014 /* clock divisor register */
|
||||||
|
#else
|
||||||
|
# define pWTCON 0x53000000
|
||||||
|
# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
|
||||||
|
# define INTSUBMSK 0x4A00001C
|
||||||
|
# define CLKDIVN 0x4C000014 /* clock divisor register */
|
||||||
|
# endif
|
||||||
|
|
||||||
|
ldr r0, =pWTCON
|
||||||
|
mov r1, #0x0
|
||||||
|
str r1, [r0]
|
||||||
|
|
||||||
|
/*
|
||||||
|
* mask all IRQs by setting all bits in the INTMR - default
|
||||||
|
*/
|
||||||
|
mov r1, #0xffffffff
|
||||||
|
ldr r0, =INTMSK
|
||||||
|
str r1, [r0]
|
||||||
|
# if defined(CONFIG_S3C2410)
|
||||||
|
ldr r1, =0x3ff
|
||||||
|
ldr r0, =INTSUBMSK
|
||||||
|
str r1, [r0]
|
||||||
|
# endif
|
||||||
|
|
||||||
|
/* FCLK:HCLK:PCLK = 1:2:4 */
|
||||||
|
/* default FCLK is 120 MHz ! */
|
||||||
|
ldr r0, =CLKDIVN
|
||||||
|
mov r1, #3
|
||||||
|
str r1, [r0]
|
||||||
|
#endif /* CONFIG_S3C24X0 */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* we do sys-critical inits only at reboot,
|
||||||
|
* not when booting from ram!
|
||||||
|
*/
|
||||||
|
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||||
|
bl cpu_init_crit
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Set stackpointer in internal RAM to call board_init_f */
|
||||||
|
call_board_init_f:
|
||||||
|
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
|
||||||
|
ldr r0,=0x00000000
|
||||||
|
bl board_init_f
|
||||||
|
|
||||||
|
/*------------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* void relocate_code (addr_sp, gd, addr_moni)
|
||||||
|
*
|
||||||
|
* This "function" does not return, instead it continues in RAM
|
||||||
|
* after relocating the monitor code.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
.globl relocate_code
|
||||||
|
relocate_code:
|
||||||
|
mov r4, r0 /* save addr_sp */
|
||||||
|
mov r5, r1 /* save addr of gd */
|
||||||
|
mov r6, r2 /* save addr of destination */
|
||||||
|
mov r7, r2 /* save addr of destination */
|
||||||
|
|
||||||
|
/* Set up the stack */
|
||||||
|
stack_setup:
|
||||||
|
mov sp, r4
|
||||||
|
|
||||||
|
adr r0, _start
|
||||||
|
ldr r2, _TEXT_BASE
|
||||||
|
ldr r3, _bss_start
|
||||||
|
sub r2, r3, r2 /* r2 <- size of armboot */
|
||||||
|
add r2, r0, r2 /* r2 <- source end address */
|
||||||
|
cmp r0, r6
|
||||||
|
beq clear_bss
|
||||||
|
|
||||||
|
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
|
||||||
|
copy_loop:
|
||||||
|
ldmia r0!, {r9-r10} /* copy from source address [r0] */
|
||||||
|
stmia r6!, {r9-r10} /* copy to target address [r1] */
|
||||||
|
cmp r0, r2 /* until source end addreee [r2] */
|
||||||
|
ble copy_loop
|
||||||
|
|
||||||
|
#ifndef CONFIG_PRELOADER
|
||||||
|
/* fix got entries */
|
||||||
|
ldr r1, _TEXT_BASE /* Text base */
|
||||||
|
mov r0, r7 /* reloc addr */
|
||||||
|
ldr r2, _got_start /* addr in Flash */
|
||||||
|
ldr r3, _got_end /* addr in Flash */
|
||||||
|
sub r3, r3, r1
|
||||||
|
add r3, r3, r0
|
||||||
|
sub r2, r2, r1
|
||||||
|
add r2, r2, r0
|
||||||
|
|
||||||
|
fixloop:
|
||||||
|
ldr r4, [r2]
|
||||||
|
sub r4, r4, r1
|
||||||
|
add r4, r4, r0
|
||||||
|
str r4, [r2]
|
||||||
|
add r2, r2, #4
|
||||||
|
cmp r2, r3
|
||||||
|
bne fixloop
|
||||||
|
#endif
|
||||||
|
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
|
||||||
|
|
||||||
|
clear_bss:
|
||||||
|
#ifndef CONFIG_PRELOADER
|
||||||
|
ldr r0, _bss_start
|
||||||
|
ldr r1, _bss_end
|
||||||
|
ldr r3, _TEXT_BASE /* Text base */
|
||||||
|
mov r4, r7 /* reloc addr */
|
||||||
|
sub r0, r0, r3
|
||||||
|
add r0, r0, r4
|
||||||
|
sub r1, r1, r3
|
||||||
|
add r1, r1, r4
|
||||||
|
mov r2, #0x00000000 /* clear */
|
||||||
|
|
||||||
|
clbss_l:str r2, [r0] /* clear loop... */
|
||||||
|
add r0, r0, #4
|
||||||
|
cmp r0, r1
|
||||||
|
bne clbss_l
|
||||||
|
|
||||||
|
bl coloured_LED_init
|
||||||
|
bl red_LED_on
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We are done. Do not return, instead branch to second part of board
|
||||||
|
* initialization, now running from RAM.
|
||||||
|
*/
|
||||||
|
#ifdef CONFIG_NAND_SPL
|
||||||
|
ldr pc, _nand_boot
|
||||||
|
|
||||||
|
_nand_boot: .word nand_boot
|
||||||
|
#else
|
||||||
|
ldr r0, _TEXT_BASE
|
||||||
|
ldr r2, _board_init_r
|
||||||
|
sub r2, r2, r0
|
||||||
|
add r2, r2, r7 /* position from board_init_r in RAM */
|
||||||
|
/* setup parameters for board_init_r */
|
||||||
|
mov r0, r5 /* gd_t */
|
||||||
|
mov r1, r7 /* dest_addr */
|
||||||
|
/* jump to it ... */
|
||||||
|
mov lr, r2
|
||||||
|
mov pc, lr
|
||||||
|
|
||||||
|
_board_init_r: .word board_init_r
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||||
/*
|
/*
|
||||||
* the actual start code
|
* the actual start code
|
||||||
*/
|
*/
|
||||||
@ -219,7 +434,7 @@ clbss_l:str r2, [r0] /* clear loop... */
|
|||||||
ldr pc, _start_armboot
|
ldr pc, _start_armboot
|
||||||
|
|
||||||
_start_armboot: .word start_armboot
|
_start_armboot: .word start_armboot
|
||||||
|
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
*************************************************************************
|
*************************************************************************
|
||||||
@ -309,11 +524,15 @@ cpu_init_crit:
|
|||||||
.macro bad_save_user_regs
|
.macro bad_save_user_regs
|
||||||
sub sp, sp, #S_FRAME_SIZE
|
sub sp, sp, #S_FRAME_SIZE
|
||||||
stmia sp, {r0 - r12} @ Calling r0-r12
|
stmia sp, {r0 - r12} @ Calling r0-r12
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
ldr r2, _armboot_start
|
ldr r2, _armboot_start
|
||||||
sub r2, r2, #(CONFIG_STACKSIZE)
|
sub r2, r2, #(CONFIG_STACKSIZE)
|
||||||
sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
|
sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
|
||||||
/* set base 2 words into abort stack */
|
/* set base 2 words into abort stack */
|
||||||
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)
|
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)
|
||||||
|
#else
|
||||||
|
ldr r2, IRQ_STACK_START_IN
|
||||||
|
#endif
|
||||||
ldmia r2, {r2 - r3} @ get pc, cpsr
|
ldmia r2, {r2 - r3} @ get pc, cpsr
|
||||||
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
|
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
|
||||||
|
|
||||||
@ -345,11 +564,15 @@ cpu_init_crit:
|
|||||||
.endm
|
.endm
|
||||||
|
|
||||||
.macro get_bad_stack
|
.macro get_bad_stack
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
ldr r13, _armboot_start @ setup our mode stack
|
ldr r13, _armboot_start @ setup our mode stack
|
||||||
sub r13, r13, #(CONFIG_STACKSIZE)
|
sub r13, r13, #(CONFIG_STACKSIZE)
|
||||||
sub r13, r13, #(CONFIG_SYS_MALLOC_LEN)
|
sub r13, r13, #(CONFIG_SYS_MALLOC_LEN)
|
||||||
/* reserve a couple spots in abort stack */
|
/* reserve a couple spots in abort stack */
|
||||||
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8)
|
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8)
|
||||||
|
#else
|
||||||
|
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
|
||||||
|
#endif
|
||||||
|
|
||||||
str lr, [r13] @ save caller lr / spsr
|
str lr, [r13] @ save caller lr / spsr
|
||||||
mrs lr, spsr
|
mrs lr, spsr
|
||||||
|
@ -47,11 +47,23 @@ SECTIONS
|
|||||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||||
|
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
.data : { *(.data) }
|
.data : {
|
||||||
|
*(.data)
|
||||||
|
__datarel_start = .;
|
||||||
|
*(.data.rel)
|
||||||
|
__datarelrolocal_start = .;
|
||||||
|
*(.data.rel.ro.local)
|
||||||
|
__datarellocal_start = .;
|
||||||
|
*(.data.rel.local)
|
||||||
|
__datarelro_start = .;
|
||||||
|
*(.data.rel.ro)
|
||||||
|
}
|
||||||
|
|
||||||
|
__got_start = .;
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
.got : { *(.got) }
|
.got : { *(.got) }
|
||||||
|
|
||||||
|
__got_end = .;
|
||||||
. = .;
|
. = .;
|
||||||
__u_boot_cmd_start = .;
|
__u_boot_cmd_start = .;
|
||||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||||
|
@ -81,12 +81,15 @@ _fiq: .word fiq
|
|||||||
*************************************************************************
|
*************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
.globl _TEXT_BASE
|
||||||
_TEXT_BASE:
|
_TEXT_BASE:
|
||||||
.word TEXT_BASE
|
.word TEXT_BASE
|
||||||
|
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
.globl _armboot_start
|
.globl _armboot_start
|
||||||
_armboot_start:
|
_armboot_start:
|
||||||
.word _start
|
.word _start
|
||||||
|
#endif
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* These are defined in the board-specific linker script.
|
* These are defined in the board-specific linker script.
|
||||||
@ -111,7 +114,198 @@ FIQ_STACK_START:
|
|||||||
.word 0x0badc0de
|
.word 0x0badc0de
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
|
/* IRQ stack memory (calculated at run-time) + 8 bytes */
|
||||||
|
.globl IRQ_STACK_START_IN
|
||||||
|
IRQ_STACK_START_IN:
|
||||||
|
.word 0x0badc0de
|
||||||
|
|
||||||
|
.globl _datarel_start
|
||||||
|
_datarel_start:
|
||||||
|
.word __datarel_start
|
||||||
|
|
||||||
|
.globl _datarelrolocal_start
|
||||||
|
_datarelrolocal_start:
|
||||||
|
.word __datarelrolocal_start
|
||||||
|
|
||||||
|
.globl _datarellocal_start
|
||||||
|
_datarellocal_start:
|
||||||
|
.word __datarellocal_start
|
||||||
|
|
||||||
|
.globl _datarelro_start
|
||||||
|
_datarelro_start:
|
||||||
|
.word __datarelro_start
|
||||||
|
|
||||||
|
.globl _got_start
|
||||||
|
_got_start:
|
||||||
|
.word __got_start
|
||||||
|
|
||||||
|
.globl _got_end
|
||||||
|
_got_end:
|
||||||
|
.word __got_end
|
||||||
|
|
||||||
|
/*
|
||||||
|
* the actual reset code
|
||||||
|
*/
|
||||||
|
|
||||||
|
reset:
|
||||||
|
/*
|
||||||
|
* set the cpu to SVC32 mode
|
||||||
|
*/
|
||||||
|
mrs r0,cpsr
|
||||||
|
bic r0,r0,#0x1f
|
||||||
|
orr r0,r0,#0xd3
|
||||||
|
msr cpsr,r0
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Set up 925T mode
|
||||||
|
*/
|
||||||
|
mov r1, #0x81 /* Set ARM925T configuration. */
|
||||||
|
mcr p15, 0, r1, c15, c1, 0 /* Write ARM925T configuration register. */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* turn off the watchdog, unlock/diable sequence
|
||||||
|
*/
|
||||||
|
mov r1, #0xF5
|
||||||
|
ldr r0, =WDTIM_MODE
|
||||||
|
strh r1, [r0]
|
||||||
|
mov r1, #0xA0
|
||||||
|
strh r1, [r0]
|
||||||
|
|
||||||
|
/*
|
||||||
|
* mask all IRQs by setting all bits in the INTMR - default
|
||||||
|
*/
|
||||||
|
mov r1, #0xffffffff
|
||||||
|
ldr r0, =REG_IHL1_MIR
|
||||||
|
str r1, [r0]
|
||||||
|
ldr r0, =REG_IHL2_MIR
|
||||||
|
str r1, [r0]
|
||||||
|
|
||||||
|
/*
|
||||||
|
* wait for dpll to lock
|
||||||
|
*/
|
||||||
|
ldr r0, =CK_DPLL1
|
||||||
|
mov r1, #0x10
|
||||||
|
strh r1, [r0]
|
||||||
|
poll1:
|
||||||
|
ldrh r1, [r0]
|
||||||
|
ands r1, r1, #0x01
|
||||||
|
beq poll1
|
||||||
|
|
||||||
|
/*
|
||||||
|
* we do sys-critical inits only at reboot,
|
||||||
|
* not when booting from ram!
|
||||||
|
*/
|
||||||
|
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||||
|
bl cpu_init_crit
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Set stackpointer in internal RAM to call board_init_f */
|
||||||
|
call_board_init_f:
|
||||||
|
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
|
||||||
|
ldr r0,=0x00000000
|
||||||
|
bl board_init_f
|
||||||
|
|
||||||
|
/*------------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* void relocate_code (addr_sp, gd, addr_moni)
|
||||||
|
*
|
||||||
|
* This "function" does not return, instead it continues in RAM
|
||||||
|
* after relocating the monitor code.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
.globl relocate_code
|
||||||
|
relocate_code:
|
||||||
|
mov r4, r0 /* save addr_sp */
|
||||||
|
mov r5, r1 /* save addr of gd */
|
||||||
|
mov r6, r2 /* save addr of destination */
|
||||||
|
mov r7, r2 /* save addr of destination */
|
||||||
|
|
||||||
|
/* Set up the stack */
|
||||||
|
stack_setup:
|
||||||
|
mov sp, r4
|
||||||
|
|
||||||
|
adr r0, _start
|
||||||
|
ldr r2, _TEXT_BASE
|
||||||
|
ldr r3, _bss_start
|
||||||
|
sub r2, r3, r2 /* r2 <- size of armboot */
|
||||||
|
add r2, r0, r2 /* r2 <- source end address */
|
||||||
|
cmp r0, r6
|
||||||
|
beq clear_bss
|
||||||
|
|
||||||
|
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
|
||||||
|
copy_loop:
|
||||||
|
ldmia r0!, {r9-r10} /* copy from source address [r0] */
|
||||||
|
stmia r6!, {r9-r10} /* copy to target address [r1] */
|
||||||
|
cmp r0, r2 /* until source end addreee [r2] */
|
||||||
|
ble copy_loop
|
||||||
|
|
||||||
|
#ifndef CONFIG_PRELOADER
|
||||||
|
/* fix got entries */
|
||||||
|
ldr r1, _TEXT_BASE /* Text base */
|
||||||
|
mov r0, r7 /* reloc addr */
|
||||||
|
ldr r2, _got_start /* addr in Flash */
|
||||||
|
ldr r3, _got_end /* addr in Flash */
|
||||||
|
sub r3, r3, r1
|
||||||
|
add r3, r3, r0
|
||||||
|
sub r2, r2, r1
|
||||||
|
add r2, r2, r0
|
||||||
|
|
||||||
|
fixloop:
|
||||||
|
ldr r4, [r2]
|
||||||
|
sub r4, r4, r1
|
||||||
|
add r4, r4, r0
|
||||||
|
str r4, [r2]
|
||||||
|
add r2, r2, #4
|
||||||
|
cmp r2, r3
|
||||||
|
bne fixloop
|
||||||
|
#endif
|
||||||
|
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
|
||||||
|
|
||||||
|
clear_bss:
|
||||||
|
#ifndef CONFIG_PRELOADER
|
||||||
|
ldr r0, _bss_start
|
||||||
|
ldr r1, _bss_end
|
||||||
|
ldr r3, _TEXT_BASE /* Text base */
|
||||||
|
mov r4, r7 /* reloc addr */
|
||||||
|
sub r0, r0, r3
|
||||||
|
add r0, r0, r4
|
||||||
|
sub r1, r1, r3
|
||||||
|
add r1, r1, r4
|
||||||
|
mov r2, #0x00000000 /* clear */
|
||||||
|
|
||||||
|
clbss_l:str r2, [r0] /* clear loop... */
|
||||||
|
add r0, r0, #4
|
||||||
|
cmp r0, r1
|
||||||
|
bne clbss_l
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We are done. Do not return, instead branch to second part of board
|
||||||
|
* initialization, now running from RAM.
|
||||||
|
*/
|
||||||
|
#ifdef CONFIG_NAND_SPL
|
||||||
|
ldr pc, _nand_boot
|
||||||
|
|
||||||
|
_nand_boot: .word nand_boot
|
||||||
|
#else
|
||||||
|
ldr r0, _TEXT_BASE
|
||||||
|
ldr r2, _board_init_r
|
||||||
|
sub r2, r2, r0
|
||||||
|
add r2, r2, r7 /* position from board_init_r in RAM */
|
||||||
|
/* setup parameters for board_init_r */
|
||||||
|
mov r0, r5 /* gd_t */
|
||||||
|
mov r1, r7 /* dest_addr */
|
||||||
|
/* jump to it ... */
|
||||||
|
mov lr, r2
|
||||||
|
mov pc, lr
|
||||||
|
|
||||||
|
_board_init_r: .word board_init_r
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||||
/*
|
/*
|
||||||
* the actual reset code
|
* the actual reset code
|
||||||
*/
|
*/
|
||||||
@ -211,7 +405,7 @@ clbss_l:str r2, [r0] /* clear loop... */
|
|||||||
ldr pc, _start_armboot
|
ldr pc, _start_armboot
|
||||||
|
|
||||||
_start_armboot: .word start_armboot
|
_start_armboot: .word start_armboot
|
||||||
|
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
*************************************************************************
|
*************************************************************************
|
||||||
@ -295,9 +489,13 @@ cpu_init_crit:
|
|||||||
sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
|
sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
|
||||||
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
|
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
|
||||||
|
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
ldr r2, _armboot_start
|
ldr r2, _armboot_start
|
||||||
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
||||||
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
|
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
|
||||||
|
#else
|
||||||
|
ldr r2, IRQ_STACK_START_IN
|
||||||
|
#endif
|
||||||
ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
|
ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
|
||||||
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
|
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
|
||||||
|
|
||||||
@ -328,9 +526,13 @@ cpu_init_crit:
|
|||||||
.endm
|
.endm
|
||||||
|
|
||||||
.macro get_bad_stack
|
.macro get_bad_stack
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
ldr r13, _armboot_start @ setup our mode stack
|
ldr r13, _armboot_start @ setup our mode stack
|
||||||
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
||||||
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
|
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
|
||||||
|
#else
|
||||||
|
ldr r13, IRQ_STACK_START_IN
|
||||||
|
#endif
|
||||||
|
|
||||||
str lr, [r13] @ save caller lr in position 0 of saved stack
|
str lr, [r13] @ save caller lr in position 0 of saved stack
|
||||||
mrs lr, spsr @ get the spsr
|
mrs lr, spsr @ get the spsr
|
||||||
|
@ -42,11 +42,23 @@ SECTIONS
|
|||||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||||
|
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
.data : { *(.data) }
|
.data : {
|
||||||
|
*(.data)
|
||||||
|
__datarel_start = .;
|
||||||
|
*(.data.rel)
|
||||||
|
__datarelrolocal_start = .;
|
||||||
|
*(.data.rel.ro.local)
|
||||||
|
__datarellocal_start = .;
|
||||||
|
*(.data.rel.local)
|
||||||
|
__datarelro_start = .;
|
||||||
|
*(.data.rel.ro)
|
||||||
|
}
|
||||||
|
|
||||||
|
__got_start = .;
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
.got : { *(.got) }
|
.got : { *(.got) }
|
||||||
|
|
||||||
|
__got_end = .;
|
||||||
. = .;
|
. = .;
|
||||||
__u_boot_cmd_start = .;
|
__u_boot_cmd_start = .;
|
||||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||||
|
@ -49,7 +49,7 @@ u32 orion5x_sdram_bar(enum memory_bank bank)
|
|||||||
result = winregs[bank].base;
|
result = winregs[bank].base;
|
||||||
return result;
|
return result;
|
||||||
}
|
}
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
int dram_init(void)
|
int dram_init(void)
|
||||||
{
|
{
|
||||||
int i;
|
int i;
|
||||||
@ -62,3 +62,25 @@ int dram_init(void)
|
|||||||
}
|
}
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
#else
|
||||||
|
int dram_init (void)
|
||||||
|
{
|
||||||
|
/* dram_init must store complete ramsize in gd->ram_size */
|
||||||
|
gd->ram_size = get_ram_size(
|
||||||
|
(volatile long *) orion5x_sdram_bar(0),
|
||||||
|
CONFIG_MAX_RAM_BANK_SIZE);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void dram_init_banksize (void)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
|
||||||
|
gd->bd->bi_dram[i].start = orion5x_sdram_bar(i);
|
||||||
|
gd->bd->bi_dram[i].size = get_ram_size(
|
||||||
|
(volatile long *) (gd->bd->bi_dram[i].start),
|
||||||
|
CONFIG_MAX_RAM_BANK_SIZE);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
@ -114,12 +114,15 @@ _fiq:
|
|||||||
*************************************************************************
|
*************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
.globl _TEXT_BASE
|
||||||
_TEXT_BASE:
|
_TEXT_BASE:
|
||||||
.word TEXT_BASE
|
.word TEXT_BASE
|
||||||
|
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
.globl _armboot_start
|
.globl _armboot_start
|
||||||
_armboot_start:
|
_armboot_start:
|
||||||
.word _start
|
.word _start
|
||||||
|
#endif
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* These are defined in the board-specific linker script.
|
* These are defined in the board-specific linker script.
|
||||||
@ -144,7 +147,165 @@ FIQ_STACK_START:
|
|||||||
.word 0x0badc0de
|
.word 0x0badc0de
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
|
/* IRQ stack memory (calculated at run-time) + 8 bytes */
|
||||||
|
.globl IRQ_STACK_START_IN
|
||||||
|
IRQ_STACK_START_IN:
|
||||||
|
.word 0x0badc0de
|
||||||
|
|
||||||
|
.globl _datarel_start
|
||||||
|
_datarel_start:
|
||||||
|
.word __datarel_start
|
||||||
|
|
||||||
|
.globl _datarelrolocal_start
|
||||||
|
_datarelrolocal_start:
|
||||||
|
.word __datarelrolocal_start
|
||||||
|
|
||||||
|
.globl _datarellocal_start
|
||||||
|
_datarellocal_start:
|
||||||
|
.word __datarellocal_start
|
||||||
|
|
||||||
|
.globl _datarelro_start
|
||||||
|
_datarelro_start:
|
||||||
|
.word __datarelro_start
|
||||||
|
|
||||||
|
.globl _got_start
|
||||||
|
_got_start:
|
||||||
|
.word __got_start
|
||||||
|
|
||||||
|
.globl _got_end
|
||||||
|
_got_end:
|
||||||
|
.word __got_end
|
||||||
|
|
||||||
|
/*
|
||||||
|
* the actual reset code
|
||||||
|
*/
|
||||||
|
|
||||||
|
reset:
|
||||||
|
/*
|
||||||
|
* set the cpu to SVC32 mode
|
||||||
|
*/
|
||||||
|
mrs r0,cpsr
|
||||||
|
bic r0,r0,#0x1f
|
||||||
|
orr r0,r0,#0xd3
|
||||||
|
msr cpsr,r0
|
||||||
|
|
||||||
|
/*
|
||||||
|
* we do sys-critical inits only at reboot,
|
||||||
|
* not when booting from ram!
|
||||||
|
*/
|
||||||
|
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||||
|
bl cpu_init_crit
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Set stackpointer in internal RAM to call board_init_f */
|
||||||
|
call_board_init_f:
|
||||||
|
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
|
||||||
|
ldr r0,=0x00000000
|
||||||
|
bl board_init_f
|
||||||
|
|
||||||
|
/*------------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* void relocate_code (addr_sp, gd, addr_moni)
|
||||||
|
*
|
||||||
|
* This "function" does not return, instead it continues in RAM
|
||||||
|
* after relocating the monitor code.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
.globl relocate_code
|
||||||
|
relocate_code:
|
||||||
|
mov r4, r0 /* save addr_sp */
|
||||||
|
mov r5, r1 /* save addr of gd */
|
||||||
|
mov r6, r2 /* save addr of destination */
|
||||||
|
mov r7, r2 /* save addr of destination */
|
||||||
|
|
||||||
|
/* Set up the stack */
|
||||||
|
stack_setup:
|
||||||
|
mov sp, r4
|
||||||
|
|
||||||
|
adr r0, _start
|
||||||
|
ldr r2, _TEXT_BASE
|
||||||
|
ldr r3, _bss_start
|
||||||
|
sub r2, r3, r2 /* r2 <- size of armboot */
|
||||||
|
add r2, r0, r2 /* r2 <- source end address */
|
||||||
|
cmp r0, r6
|
||||||
|
beq clear_bss
|
||||||
|
|
||||||
|
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
|
||||||
|
copy_loop:
|
||||||
|
ldmia r0!, {r9-r10} /* copy from source address [r0] */
|
||||||
|
stmia r6!, {r9-r10} /* copy to target address [r1] */
|
||||||
|
cmp r0, r2 /* until source end addreee [r2] */
|
||||||
|
ble copy_loop
|
||||||
|
|
||||||
|
#ifndef CONFIG_PRELOADER
|
||||||
|
/* fix got entries */
|
||||||
|
ldr r1, _TEXT_BASE /* Text base */
|
||||||
|
mov r0, r7 /* reloc addr */
|
||||||
|
ldr r2, _got_start /* addr in Flash */
|
||||||
|
ldr r3, _got_end /* addr in Flash */
|
||||||
|
sub r3, r3, r1
|
||||||
|
add r3, r3, r0
|
||||||
|
sub r2, r2, r1
|
||||||
|
add r2, r2, r0
|
||||||
|
|
||||||
|
fixloop:
|
||||||
|
ldr r4, [r2]
|
||||||
|
sub r4, r4, r1
|
||||||
|
add r4, r4, r0
|
||||||
|
str r4, [r2]
|
||||||
|
add r2, r2, #4
|
||||||
|
cmp r2, r3
|
||||||
|
bne fixloop
|
||||||
|
#endif
|
||||||
|
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
|
||||||
|
|
||||||
|
clear_bss:
|
||||||
|
#ifndef CONFIG_PRELOADER
|
||||||
|
ldr r0, _bss_start
|
||||||
|
ldr r1, _bss_end
|
||||||
|
ldr r3, _TEXT_BASE /* Text base */
|
||||||
|
mov r4, r7 /* reloc addr */
|
||||||
|
sub r0, r0, r3
|
||||||
|
add r0, r0, r4
|
||||||
|
sub r1, r1, r3
|
||||||
|
add r1, r1, r4
|
||||||
|
mov r2, #0x00000000 /* clear */
|
||||||
|
|
||||||
|
clbss_l:str r2, [r0] /* clear loop... */
|
||||||
|
add r0, r0, #4
|
||||||
|
cmp r0, r1
|
||||||
|
bne clbss_l
|
||||||
|
|
||||||
|
bl coloured_LED_init
|
||||||
|
bl red_LED_on
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We are done. Do not return, instead branch to second part of board
|
||||||
|
* initialization, now running from RAM.
|
||||||
|
*/
|
||||||
|
#ifdef CONFIG_NAND_SPL
|
||||||
|
ldr pc, _nand_boot
|
||||||
|
|
||||||
|
_nand_boot: .word nand_boot
|
||||||
|
#else
|
||||||
|
ldr r0, _TEXT_BASE
|
||||||
|
ldr r2, _board_init_r
|
||||||
|
sub r2, r2, r0
|
||||||
|
add r2, r2, r7 /* position from board_init_r in RAM */
|
||||||
|
/* setup parameters for board_init_r */
|
||||||
|
mov r0, r5 /* gd_t */
|
||||||
|
mov r1, r7 /* dest_addr */
|
||||||
|
/* jump to it ... */
|
||||||
|
mov lr, r2
|
||||||
|
mov pc, lr
|
||||||
|
|
||||||
|
_board_init_r: .word board_init_r
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||||
/*
|
/*
|
||||||
* the actual reset code
|
* the actual reset code
|
||||||
*/
|
*/
|
||||||
@ -221,7 +382,7 @@ _start_armboot:
|
|||||||
#else
|
#else
|
||||||
.word start_armboot
|
.word start_armboot
|
||||||
#endif /* CONFIG_NAND_SPL */
|
#endif /* CONFIG_NAND_SPL */
|
||||||
|
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
*************************************************************************
|
*************************************************************************
|
||||||
@ -307,10 +468,13 @@ cpu_init_crit:
|
|||||||
@ carve out a frame on current user stack
|
@ carve out a frame on current user stack
|
||||||
sub sp, sp, #S_FRAME_SIZE
|
sub sp, sp, #S_FRAME_SIZE
|
||||||
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
|
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
ldr r2, _armboot_start
|
ldr r2, _armboot_start
|
||||||
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
||||||
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
|
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
|
||||||
|
#else
|
||||||
|
ldr r2, IRQ_STACK_START_IN
|
||||||
|
#endif
|
||||||
@ get values for "aborted" pc and cpsr (into parm regs)
|
@ get values for "aborted" pc and cpsr (into parm regs)
|
||||||
ldmia r2, {r2 - r3}
|
ldmia r2, {r2 - r3}
|
||||||
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
|
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
|
||||||
@ -342,9 +506,13 @@ cpu_init_crit:
|
|||||||
.endm
|
.endm
|
||||||
|
|
||||||
.macro get_bad_stack
|
.macro get_bad_stack
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
ldr r13, _armboot_start @ setup our mode stack
|
ldr r13, _armboot_start @ setup our mode stack
|
||||||
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
||||||
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
|
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
|
||||||
|
#else
|
||||||
|
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
|
||||||
|
#endif
|
||||||
|
|
||||||
str lr, [r13] @ save caller lr in position 0 of saved stack
|
str lr, [r13] @ save caller lr in position 0 of saved stack
|
||||||
mrs lr, spsr @ get the spsr
|
mrs lr, spsr @ get the spsr
|
||||||
|
@ -39,11 +39,23 @@ SECTIONS
|
|||||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||||
|
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
.data : { *(.data) }
|
.data : {
|
||||||
|
*(.data)
|
||||||
|
__datarel_start = .;
|
||||||
|
*(.data.rel)
|
||||||
|
__datarelrolocal_start = .;
|
||||||
|
*(.data.rel.ro.local)
|
||||||
|
__datarellocal_start = .;
|
||||||
|
*(.data.rel.local)
|
||||||
|
__datarelro_start = .;
|
||||||
|
*(.data.rel.ro)
|
||||||
|
}
|
||||||
|
|
||||||
|
__got_start = .;
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
.got : { *(.got) }
|
.got : { *(.got) }
|
||||||
|
|
||||||
|
__got_end = .;
|
||||||
. = .;
|
. = .;
|
||||||
__u_boot_cmd_start = .;
|
__u_boot_cmd_start = .;
|
||||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||||
|
@ -85,12 +85,15 @@ _fiq:
|
|||||||
*************************************************************************
|
*************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
.globl _TEXT_BASE
|
||||||
_TEXT_BASE:
|
_TEXT_BASE:
|
||||||
.word TEXT_BASE
|
.word TEXT_BASE
|
||||||
|
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
.globl _armboot_start
|
.globl _armboot_start
|
||||||
_armboot_start:
|
_armboot_start:
|
||||||
.word _start
|
.word _start
|
||||||
|
#endif
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* These are defined in the board-specific linker script.
|
* These are defined in the board-specific linker script.
|
||||||
@ -115,7 +118,162 @@ FIQ_STACK_START:
|
|||||||
.word 0x0badc0de
|
.word 0x0badc0de
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
|
/* IRQ stack memory (calculated at run-time) + 8 bytes */
|
||||||
|
.globl IRQ_STACK_START_IN
|
||||||
|
IRQ_STACK_START_IN:
|
||||||
|
.word 0x0badc0de
|
||||||
|
|
||||||
|
.globl _datarel_start
|
||||||
|
_datarel_start:
|
||||||
|
.word __datarel_start
|
||||||
|
|
||||||
|
.globl _datarelrolocal_start
|
||||||
|
_datarelrolocal_start:
|
||||||
|
.word __datarelrolocal_start
|
||||||
|
|
||||||
|
.globl _datarellocal_start
|
||||||
|
_datarellocal_start:
|
||||||
|
.word __datarellocal_start
|
||||||
|
|
||||||
|
.globl _datarelro_start
|
||||||
|
_datarelro_start:
|
||||||
|
.word __datarelro_start
|
||||||
|
|
||||||
|
.globl _got_start
|
||||||
|
_got_start:
|
||||||
|
.word __got_start
|
||||||
|
|
||||||
|
.globl _got_end
|
||||||
|
_got_end:
|
||||||
|
.word __got_end
|
||||||
|
|
||||||
|
/*
|
||||||
|
* the actual reset code
|
||||||
|
*/
|
||||||
|
|
||||||
|
reset:
|
||||||
|
/*
|
||||||
|
* set the cpu to SVC32 mode
|
||||||
|
*/
|
||||||
|
mrs r0,cpsr
|
||||||
|
bic r0,r0,#0x1f
|
||||||
|
orr r0,r0,#0xd3
|
||||||
|
msr cpsr,r0
|
||||||
|
|
||||||
|
/*
|
||||||
|
* we do sys-critical inits only at reboot,
|
||||||
|
* not when booting from ram!
|
||||||
|
*/
|
||||||
|
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||||
|
bl cpu_init_crit
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Set stackpointer in internal RAM to call board_init_f */
|
||||||
|
call_board_init_f:
|
||||||
|
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
|
||||||
|
ldr r0,=0x00000000
|
||||||
|
bl board_init_f
|
||||||
|
|
||||||
|
/*------------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* void relocate_code (addr_sp, gd, addr_moni)
|
||||||
|
*
|
||||||
|
* This "function" does not return, instead it continues in RAM
|
||||||
|
* after relocating the monitor code.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
.globl relocate_code
|
||||||
|
relocate_code:
|
||||||
|
mov r4, r0 /* save addr_sp */
|
||||||
|
mov r5, r1 /* save addr of gd */
|
||||||
|
mov r6, r2 /* save addr of destination */
|
||||||
|
mov r7, r2 /* save addr of destination */
|
||||||
|
|
||||||
|
/* Set up the stack */
|
||||||
|
stack_setup:
|
||||||
|
mov sp, r4
|
||||||
|
|
||||||
|
adr r0, _start
|
||||||
|
ldr r2, _TEXT_BASE
|
||||||
|
ldr r3, _bss_start
|
||||||
|
sub r2, r3, r2 /* r2 <- size of armboot */
|
||||||
|
add r2, r0, r2 /* r2 <- source end address */
|
||||||
|
cmp r0, r6
|
||||||
|
beq clear_bss
|
||||||
|
|
||||||
|
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
|
||||||
|
copy_loop:
|
||||||
|
ldmia r0!, {r9-r10} /* copy from source address [r0] */
|
||||||
|
stmia r6!, {r9-r10} /* copy to target address [r1] */
|
||||||
|
cmp r0, r2 /* until source end addreee [r2] */
|
||||||
|
ble copy_loop
|
||||||
|
|
||||||
|
#ifndef CONFIG_PRELOADER
|
||||||
|
/* fix got entries */
|
||||||
|
ldr r1, _TEXT_BASE /* Text base */
|
||||||
|
mov r0, r7 /* reloc addr */
|
||||||
|
ldr r2, _got_start /* addr in Flash */
|
||||||
|
ldr r3, _got_end /* addr in Flash */
|
||||||
|
sub r3, r3, r1
|
||||||
|
add r3, r3, r0
|
||||||
|
sub r2, r2, r1
|
||||||
|
add r2, r2, r0
|
||||||
|
|
||||||
|
fixloop:
|
||||||
|
ldr r4, [r2]
|
||||||
|
sub r4, r4, r1
|
||||||
|
add r4, r4, r0
|
||||||
|
str r4, [r2]
|
||||||
|
add r2, r2, #4
|
||||||
|
cmp r2, r3
|
||||||
|
bne fixloop
|
||||||
|
#endif
|
||||||
|
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
|
||||||
|
|
||||||
|
clear_bss:
|
||||||
|
#ifndef CONFIG_PRELOADER
|
||||||
|
ldr r0, _bss_start
|
||||||
|
ldr r1, _bss_end
|
||||||
|
ldr r3, _TEXT_BASE /* Text base */
|
||||||
|
mov r4, r7 /* reloc addr */
|
||||||
|
sub r0, r0, r3
|
||||||
|
add r0, r0, r4
|
||||||
|
sub r1, r1, r3
|
||||||
|
add r1, r1, r4
|
||||||
|
mov r2, #0x00000000 /* clear */
|
||||||
|
|
||||||
|
clbss_l:str r2, [r0] /* clear loop... */
|
||||||
|
add r0, r0, #4
|
||||||
|
cmp r0, r1
|
||||||
|
bne clbss_l
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We are done. Do not return, instead branch to second part of board
|
||||||
|
* initialization, now running from RAM.
|
||||||
|
*/
|
||||||
|
#ifdef CONFIG_NAND_SPL
|
||||||
|
ldr pc, _nand_boot
|
||||||
|
|
||||||
|
_nand_boot: .word nand_boot
|
||||||
|
#else
|
||||||
|
ldr r0, _TEXT_BASE
|
||||||
|
ldr r2, _board_init_r
|
||||||
|
sub r2, r2, r0
|
||||||
|
add r2, r2, r7 /* position from board_init_r in RAM */
|
||||||
|
/* setup parameters for board_init_r */
|
||||||
|
mov r0, r5 /* gd_t */
|
||||||
|
mov r1, r7 /* dest_addr */
|
||||||
|
/* jump to it ... */
|
||||||
|
mov lr, r2
|
||||||
|
mov pc, lr
|
||||||
|
|
||||||
|
_board_init_r: .word board_init_r
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||||
/*
|
/*
|
||||||
* the actual reset code
|
* the actual reset code
|
||||||
*/
|
*/
|
||||||
@ -179,7 +337,7 @@ clbss_l:str r2, [r0] /* clear loop... */
|
|||||||
|
|
||||||
_start_armboot:
|
_start_armboot:
|
||||||
.word start_armboot
|
.word start_armboot
|
||||||
|
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
*************************************************************************
|
*************************************************************************
|
||||||
@ -266,9 +424,13 @@ cpu_init_crit:
|
|||||||
sub sp, sp, #S_FRAME_SIZE
|
sub sp, sp, #S_FRAME_SIZE
|
||||||
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
|
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
|
||||||
|
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
ldr r2, _armboot_start
|
ldr r2, _armboot_start
|
||||||
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
||||||
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
|
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
|
||||||
|
#else
|
||||||
|
ldr r2, IRQ_STACK_START_IN
|
||||||
|
#endif
|
||||||
@ get values for "aborted" pc and cpsr (into parm regs)
|
@ get values for "aborted" pc and cpsr (into parm regs)
|
||||||
ldmia r2, {r2 - r3}
|
ldmia r2, {r2 - r3}
|
||||||
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
|
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
|
||||||
@ -300,9 +462,13 @@ cpu_init_crit:
|
|||||||
.endm
|
.endm
|
||||||
|
|
||||||
.macro get_bad_stack
|
.macro get_bad_stack
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
ldr r13, _armboot_start @ setup our mode stack
|
ldr r13, _armboot_start @ setup our mode stack
|
||||||
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
||||||
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
|
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
|
||||||
|
#else
|
||||||
|
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
|
||||||
|
#endif
|
||||||
|
|
||||||
str lr, [r13] @ save caller lr in position 0 of saved stack
|
str lr, [r13] @ save caller lr in position 0 of saved stack
|
||||||
mrs lr, spsr @ get the spsr
|
mrs lr, spsr @ get the spsr
|
||||||
|
@ -39,11 +39,23 @@ SECTIONS
|
|||||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||||
|
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
.data : { *(.data) }
|
.data : {
|
||||||
|
*(.data)
|
||||||
|
__datarel_start = .;
|
||||||
|
*(.data.rel)
|
||||||
|
__datarelrolocal_start = .;
|
||||||
|
*(.data.rel.ro.local)
|
||||||
|
__datarellocal_start = .;
|
||||||
|
*(.data.rel.local)
|
||||||
|
__datarelro_start = .;
|
||||||
|
*(.data.rel.ro)
|
||||||
|
}
|
||||||
|
|
||||||
|
__got_start = .;
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
.got : { *(.got) }
|
.got : { *(.got) }
|
||||||
|
|
||||||
|
__got_end = .;
|
||||||
. = .;
|
. = .;
|
||||||
__u_boot_cmd_start = .;
|
__u_boot_cmd_start = .;
|
||||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||||
|
@ -83,12 +83,15 @@ _fiq:
|
|||||||
*************************************************************************
|
*************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
.globl _TEXT_BASE
|
||||||
_TEXT_BASE:
|
_TEXT_BASE:
|
||||||
.word TEXT_BASE /* address of _start in the linked image */
|
.word TEXT_BASE /* address of _start in the linked image */
|
||||||
|
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
.globl _armboot_start
|
.globl _armboot_start
|
||||||
_armboot_start:
|
_armboot_start:
|
||||||
.word _start
|
.word _start
|
||||||
|
#endif
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* These are defined in the board-specific linker script.
|
* These are defined in the board-specific linker script.
|
||||||
@ -113,6 +116,159 @@ FIQ_STACK_START:
|
|||||||
.word 0x0badc0de
|
.word 0x0badc0de
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
|
/* IRQ stack memory (calculated at run-time) + 8 bytes */
|
||||||
|
.globl IRQ_STACK_START_IN
|
||||||
|
IRQ_STACK_START_IN:
|
||||||
|
.word 0x0badc0de
|
||||||
|
|
||||||
|
.globl _datarel_start
|
||||||
|
_datarel_start:
|
||||||
|
.word __datarel_start
|
||||||
|
|
||||||
|
.globl _datarelrolocal_start
|
||||||
|
_datarelrolocal_start:
|
||||||
|
.word __datarelrolocal_start
|
||||||
|
|
||||||
|
.globl _datarellocal_start
|
||||||
|
_datarellocal_start:
|
||||||
|
.word __datarellocal_start
|
||||||
|
|
||||||
|
.globl _datarelro_start
|
||||||
|
_datarelro_start:
|
||||||
|
.word __datarelro_start
|
||||||
|
|
||||||
|
.globl _got_start
|
||||||
|
_got_start:
|
||||||
|
.word __got_start
|
||||||
|
|
||||||
|
.globl _got_end
|
||||||
|
_got_end:
|
||||||
|
.word __got_end
|
||||||
|
|
||||||
|
/*
|
||||||
|
* the actual reset code
|
||||||
|
*/
|
||||||
|
|
||||||
|
reset:
|
||||||
|
/*
|
||||||
|
* set the cpu to SVC32 mode
|
||||||
|
*/
|
||||||
|
mrs r0,cpsr
|
||||||
|
bic r0,r0,#0x1f
|
||||||
|
orr r0,r0,#0xd3
|
||||||
|
msr cpsr,r0
|
||||||
|
|
||||||
|
/*
|
||||||
|
* we do sys-critical inits only at reboot,
|
||||||
|
* not when booting from ram!
|
||||||
|
*/
|
||||||
|
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||||
|
bl cpu_init_crit
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Set stackpointer in internal RAM to call board_init_f */
|
||||||
|
call_board_init_f:
|
||||||
|
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
|
||||||
|
ldr r0,=0x00000000
|
||||||
|
bl board_init_f
|
||||||
|
|
||||||
|
/*------------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* void relocate_code (addr_sp, gd, addr_moni)
|
||||||
|
*
|
||||||
|
* This "function" does not return, instead it continues in RAM
|
||||||
|
* after relocating the monitor code.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
.globl relocate_code
|
||||||
|
relocate_code:
|
||||||
|
mov r4, r0 /* save addr_sp */
|
||||||
|
mov r5, r1 /* save addr of gd */
|
||||||
|
mov r6, r2 /* save addr of destination */
|
||||||
|
mov r7, r2 /* save addr of destination */
|
||||||
|
|
||||||
|
/* Set up the stack */
|
||||||
|
stack_setup:
|
||||||
|
mov sp, r4
|
||||||
|
|
||||||
|
adr r0, _start
|
||||||
|
ldr r2, _TEXT_BASE
|
||||||
|
ldr r3, _bss_start
|
||||||
|
sub r2, r3, r2 /* r2 <- size of armboot */
|
||||||
|
add r2, r0, r2 /* r2 <- source end address */
|
||||||
|
cmp r0, r6
|
||||||
|
beq clear_bss
|
||||||
|
|
||||||
|
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
|
||||||
|
copy_loop:
|
||||||
|
ldmia r0!, {r9-r10} /* copy from source address [r0] */
|
||||||
|
stmia r6!, {r9-r10} /* copy to target address [r1] */
|
||||||
|
cmp r0, r2 /* until source end addreee [r2] */
|
||||||
|
ble copy_loop
|
||||||
|
|
||||||
|
#ifndef CONFIG_PRELOADER
|
||||||
|
/* fix got entries */
|
||||||
|
ldr r1, _TEXT_BASE /* Text base */
|
||||||
|
mov r0, r7 /* reloc addr */
|
||||||
|
ldr r2, _got_start /* addr in Flash */
|
||||||
|
ldr r3, _got_end /* addr in Flash */
|
||||||
|
sub r3, r3, r1
|
||||||
|
add r3, r3, r0
|
||||||
|
sub r2, r2, r1
|
||||||
|
add r2, r2, r0
|
||||||
|
|
||||||
|
fixloop:
|
||||||
|
ldr r4, [r2]
|
||||||
|
sub r4, r4, r1
|
||||||
|
add r4, r4, r0
|
||||||
|
str r4, [r2]
|
||||||
|
add r2, r2, #4
|
||||||
|
cmp r2, r3
|
||||||
|
bne fixloop
|
||||||
|
#endif
|
||||||
|
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
|
||||||
|
|
||||||
|
clear_bss:
|
||||||
|
#ifndef CONFIG_PRELOADER
|
||||||
|
ldr r0, _bss_start
|
||||||
|
ldr r1, _bss_end
|
||||||
|
ldr r3, _TEXT_BASE /* Text base */
|
||||||
|
mov r4, r7 /* reloc addr */
|
||||||
|
sub r0, r0, r3
|
||||||
|
add r0, r0, r4
|
||||||
|
sub r1, r1, r3
|
||||||
|
add r1, r1, r4
|
||||||
|
mov r2, #0x00000000 /* clear */
|
||||||
|
|
||||||
|
clbss_l:str r2, [r0] /* clear loop... */
|
||||||
|
add r0, r0, #4
|
||||||
|
cmp r0, r1
|
||||||
|
bne clbss_l
|
||||||
|
|
||||||
|
bl coloured_LED_init
|
||||||
|
bl red_LED_on
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We are done. Do not return, instead branch to second part of board
|
||||||
|
* initialization, now running from RAM.
|
||||||
|
*/
|
||||||
|
ldr r0, _TEXT_BASE
|
||||||
|
ldr r2, _board_init_r
|
||||||
|
sub r2, r2, r0
|
||||||
|
add r2, r2, r7 /* position from board_init_r in RAM */
|
||||||
|
/* setup parameters for board_init_r */
|
||||||
|
mov r0, r5 /* gd_t */
|
||||||
|
mov r1, r7 /* dest_addr */
|
||||||
|
/* jump to it ... */
|
||||||
|
mov lr, r2
|
||||||
|
mov pc, lr
|
||||||
|
|
||||||
|
_board_init_r: .word board_init_r
|
||||||
|
|
||||||
|
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* the actual reset code
|
* the actual reset code
|
||||||
@ -178,6 +334,8 @@ clbss_l:str r2, [r0] /* clear loop... */
|
|||||||
_start_armboot:
|
_start_armboot:
|
||||||
.word start_armboot
|
.word start_armboot
|
||||||
|
|
||||||
|
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
*************************************************************************
|
*************************************************************************
|
||||||
*
|
*
|
||||||
@ -242,9 +400,13 @@ cpu_init_crit:
|
|||||||
sub sp, sp, #S_FRAME_SIZE
|
sub sp, sp, #S_FRAME_SIZE
|
||||||
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
|
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
|
||||||
|
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
ldr r2, _armboot_start
|
ldr r2, _armboot_start
|
||||||
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
||||||
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
|
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
|
||||||
|
#else
|
||||||
|
ldr r2, IRQ_STACK_START_IN
|
||||||
|
#endif
|
||||||
@ get values for "aborted" pc and cpsr (into parm regs)
|
@ get values for "aborted" pc and cpsr (into parm regs)
|
||||||
ldmia r2, {r2 - r3}
|
ldmia r2, {r2 - r3}
|
||||||
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
|
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
|
||||||
@ -276,9 +438,13 @@ cpu_init_crit:
|
|||||||
.endm
|
.endm
|
||||||
|
|
||||||
.macro get_bad_stack
|
.macro get_bad_stack
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
ldr r13, _armboot_start @ setup our mode stack
|
ldr r13, _armboot_start @ setup our mode stack
|
||||||
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
||||||
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
|
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
|
||||||
|
#else
|
||||||
|
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
|
||||||
|
#endif
|
||||||
|
|
||||||
str lr, [r13] @ save caller lr in position 0 of saved stack
|
str lr, [r13] @ save caller lr in position 0 of saved stack
|
||||||
mrs lr, spsr @ get the spsr
|
mrs lr, spsr @ get the spsr
|
||||||
|
@ -39,11 +39,23 @@ SECTIONS
|
|||||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||||
|
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
.data : { *(.data) }
|
.data : {
|
||||||
|
*(.data)
|
||||||
|
__datarel_start = .;
|
||||||
|
*(.data.rel)
|
||||||
|
__datarelrolocal_start = .;
|
||||||
|
*(.data.rel.ro.local)
|
||||||
|
__datarellocal_start = .;
|
||||||
|
*(.data.rel.local)
|
||||||
|
__datarelro_start = .;
|
||||||
|
*(.data.rel.ro)
|
||||||
|
}
|
||||||
|
|
||||||
|
__got_start = .;
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
.got : { *(.got) }
|
.got : { *(.got) }
|
||||||
|
|
||||||
|
__got_end = .;
|
||||||
. = .;
|
. = .;
|
||||||
__u_boot_cmd_start = .;
|
__u_boot_cmd_start = .;
|
||||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||||
|
@ -44,10 +44,22 @@ SECTIONS
|
|||||||
.rodata : { *(.rodata) }
|
.rodata : { *(.rodata) }
|
||||||
|
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
.data : { *(.data) }
|
.data : {
|
||||||
|
*(.data)
|
||||||
|
__datarel_start = .;
|
||||||
|
*(.data.rel)
|
||||||
|
__datarelrolocal_start = .;
|
||||||
|
*(.data.rel.ro.local)
|
||||||
|
__datarellocal_start = .;
|
||||||
|
*(.data.rel.local)
|
||||||
|
__datarelro_start = .;
|
||||||
|
*(.data.rel.ro)
|
||||||
|
}
|
||||||
|
|
||||||
|
__got_start = .;
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
.got : { *(.got) }
|
.got : { *(.got) }
|
||||||
|
__got_end = .;
|
||||||
|
|
||||||
. = .;
|
. = .;
|
||||||
__u_boot_cmd_start = .;
|
__u_boot_cmd_start = .;
|
||||||
|
@ -181,3 +181,83 @@ setup_auxcr:
|
|||||||
orrlt r0, r0, #1 << 27
|
orrlt r0, r0, #1 << 27
|
||||||
.word 0xE1600070 @ SMC
|
.word 0xE1600070 @ SMC
|
||||||
bx lr
|
bx lr
|
||||||
|
|
||||||
|
.align 5
|
||||||
|
.global v7_flush_dcache_all
|
||||||
|
.global v7_flush_cache_all
|
||||||
|
|
||||||
|
/*
|
||||||
|
* v7_flush_dcache_all()
|
||||||
|
*
|
||||||
|
* Flush the whole D-cache.
|
||||||
|
*
|
||||||
|
* Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
|
||||||
|
*
|
||||||
|
* - mm - mm_struct describing address space
|
||||||
|
*/
|
||||||
|
v7_flush_dcache_all:
|
||||||
|
# dmb @ ensure ordering with previous memory accesses
|
||||||
|
mrc p15, 1, r0, c0, c0, 1 @ read clidr
|
||||||
|
ands r3, r0, #0x7000000 @ extract loc from clidr
|
||||||
|
mov r3, r3, lsr #23 @ left align loc bit field
|
||||||
|
beq finished @ if loc is 0, then no need to clean
|
||||||
|
mov r10, #0 @ start clean at cache level 0
|
||||||
|
loop1:
|
||||||
|
add r2, r10, r10, lsr #1 @ work out 3x current cache level
|
||||||
|
mov r1, r0, lsr r2 @ extract cache type bits from clidr
|
||||||
|
and r1, r1, #7 @ mask of the bits for current cache only
|
||||||
|
cmp r1, #2 @ see what cache we have at this level
|
||||||
|
blt skip @ skip if no cache, or just i-cache
|
||||||
|
mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
|
||||||
|
mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer,
|
||||||
|
@ with armv7 this is 'isb',
|
||||||
|
@ but we compile with armv5
|
||||||
|
mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
|
||||||
|
and r2, r1, #7 @ extract the length of the cache lines
|
||||||
|
add r2, r2, #4 @ add 4 (line length offset)
|
||||||
|
ldr r4, =0x3ff
|
||||||
|
ands r4, r4, r1, lsr #3 @ find maximum number on the way size
|
||||||
|
clz r5, r4 @ find bit position of way size increment
|
||||||
|
ldr r7, =0x7fff
|
||||||
|
ands r7, r7, r1, lsr #13 @ extract max number of the index size
|
||||||
|
loop2:
|
||||||
|
mov r9, r4 @ create working copy of max way size
|
||||||
|
loop3:
|
||||||
|
orr r11, r10, r9, lsl r5 @ factor way and cache number into r11
|
||||||
|
orr r11, r11, r7, lsl r2 @ factor index number into r11
|
||||||
|
mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
|
||||||
|
subs r9, r9, #1 @ decrement the way
|
||||||
|
bge loop3
|
||||||
|
subs r7, r7, #1 @ decrement the index
|
||||||
|
bge loop2
|
||||||
|
skip:
|
||||||
|
add r10, r10, #2 @ increment cache number
|
||||||
|
cmp r3, r10
|
||||||
|
bgt loop1
|
||||||
|
finished:
|
||||||
|
mov r10, #0 @ swith back to cache level 0
|
||||||
|
mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
|
||||||
|
# dsb
|
||||||
|
mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer,
|
||||||
|
@ with armv7 this is 'isb',
|
||||||
|
@ but we compile with armv5
|
||||||
|
mov pc, lr
|
||||||
|
|
||||||
|
/*
|
||||||
|
* v7_flush_cache_all()
|
||||||
|
*
|
||||||
|
* Flush the entire cache system.
|
||||||
|
* The data cache flush is now achieved using atomic clean / invalidates
|
||||||
|
* working outwards from L1 cache. This is done using Set/Way based cache
|
||||||
|
* maintainance instructions.
|
||||||
|
* The instruction cache can still be invalidated back to the point of
|
||||||
|
* unification in a single instruction.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
v7_flush_cache_all:
|
||||||
|
stmfd sp!, {r0-r7, r9-r11, lr}
|
||||||
|
bl v7_flush_dcache_all
|
||||||
|
mov r0, #0
|
||||||
|
mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
|
||||||
|
ldmfd sp!, {r0-r7, r9-r11, lr}
|
||||||
|
mov pc, lr
|
||||||
|
@ -136,6 +136,7 @@ void do_emif4_init(void)
|
|||||||
* dram_init -
|
* dram_init -
|
||||||
* - Sets uboots idea of sdram size
|
* - Sets uboots idea of sdram size
|
||||||
*/
|
*/
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
int dram_init(void)
|
int dram_init(void)
|
||||||
{
|
{
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
@ -157,6 +158,39 @@ int dram_init(void)
|
|||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
#else
|
||||||
|
int dram_init(void)
|
||||||
|
{
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
unsigned int size0 = 0, size1 = 0;
|
||||||
|
|
||||||
|
size0 = get_sdr_cs_size(CS0);
|
||||||
|
/*
|
||||||
|
* If a second bank of DDR is attached to CS1 this is
|
||||||
|
* where it can be started. Early init code will init
|
||||||
|
* memory on CS0.
|
||||||
|
*/
|
||||||
|
if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED))
|
||||||
|
size1 = get_sdr_cs_size(CS1);
|
||||||
|
|
||||||
|
gd->ram_size = size0 + size1;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void dram_init_banksize (void)
|
||||||
|
{
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
unsigned int size0 = 0, size1 = 0;
|
||||||
|
|
||||||
|
size0 = get_sdr_cs_size(CS0);
|
||||||
|
size1 = get_sdr_cs_size(CS1);
|
||||||
|
|
||||||
|
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||||
|
gd->bd->bi_dram[0].size = size0;
|
||||||
|
gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
|
||||||
|
gd->bd->bi_dram[1].size = size1;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* mem_init() -
|
* mem_init() -
|
||||||
|
@ -163,6 +163,7 @@ void do_sdrc_init(u32 cs, u32 early)
|
|||||||
* dram_init -
|
* dram_init -
|
||||||
* - Sets uboots idea of sdram size
|
* - Sets uboots idea of sdram size
|
||||||
*/
|
*/
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
int dram_init(void)
|
int dram_init(void)
|
||||||
{
|
{
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
@ -188,6 +189,43 @@ int dram_init(void)
|
|||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
#else
|
||||||
|
int dram_init(void)
|
||||||
|
{
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
unsigned int size0 = 0, size1 = 0;
|
||||||
|
|
||||||
|
size0 = get_sdr_cs_size(CS0);
|
||||||
|
/*
|
||||||
|
* If a second bank of DDR is attached to CS1 this is
|
||||||
|
* where it can be started. Early init code will init
|
||||||
|
* memory on CS0.
|
||||||
|
*/
|
||||||
|
if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
|
||||||
|
do_sdrc_init(CS1, NOT_EARLY);
|
||||||
|
make_cs1_contiguous();
|
||||||
|
|
||||||
|
size1 = get_sdr_cs_size(CS1);
|
||||||
|
}
|
||||||
|
gd->ram_size = size0 + size1;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void dram_init_banksize (void)
|
||||||
|
{
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
unsigned int size0 = 0, size1 = 0;
|
||||||
|
|
||||||
|
size0 = get_sdr_cs_size(CS0);
|
||||||
|
size1 = get_sdr_cs_size(CS1);
|
||||||
|
|
||||||
|
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||||
|
gd->bd->bi_dram[0].size = size0;
|
||||||
|
gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
|
||||||
|
gd->bd->bi_dram[1].size = size1;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* mem_init -
|
* mem_init -
|
||||||
|
@ -65,12 +65,15 @@ _end_vect:
|
|||||||
*
|
*
|
||||||
*************************************************************************/
|
*************************************************************************/
|
||||||
|
|
||||||
|
.globl _TEXT_BASE
|
||||||
_TEXT_BASE:
|
_TEXT_BASE:
|
||||||
.word TEXT_BASE
|
.word TEXT_BASE
|
||||||
|
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
.globl _armboot_start
|
.globl _armboot_start
|
||||||
_armboot_start:
|
_armboot_start:
|
||||||
.word _start
|
.word _start
|
||||||
|
#endif
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* These are defined in the board-specific linker script.
|
* These are defined in the board-specific linker script.
|
||||||
@ -95,6 +98,176 @@ FIQ_STACK_START:
|
|||||||
.word 0x0badc0de
|
.word 0x0badc0de
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
|
/* IRQ stack memory (calculated at run-time) + 8 bytes */
|
||||||
|
.globl IRQ_STACK_START_IN
|
||||||
|
IRQ_STACK_START_IN:
|
||||||
|
.word 0x0badc0de
|
||||||
|
|
||||||
|
.globl _datarel_start
|
||||||
|
_datarel_start:
|
||||||
|
.word __datarel_start
|
||||||
|
|
||||||
|
.globl _datarelrolocal_start
|
||||||
|
_datarelrolocal_start:
|
||||||
|
.word __datarelrolocal_start
|
||||||
|
|
||||||
|
.globl _datarellocal_start
|
||||||
|
_datarellocal_start:
|
||||||
|
.word __datarellocal_start
|
||||||
|
|
||||||
|
.globl _datarelro_start
|
||||||
|
_datarelro_start:
|
||||||
|
.word __datarelro_start
|
||||||
|
|
||||||
|
.globl _got_start
|
||||||
|
_got_start:
|
||||||
|
.word __got_start
|
||||||
|
|
||||||
|
.globl _got_end
|
||||||
|
_got_end:
|
||||||
|
.word __got_end
|
||||||
|
|
||||||
|
/*
|
||||||
|
* the actual reset code
|
||||||
|
*/
|
||||||
|
|
||||||
|
reset:
|
||||||
|
/*
|
||||||
|
* set the cpu to SVC32 mode
|
||||||
|
*/
|
||||||
|
mrs r0, cpsr
|
||||||
|
bic r0, r0, #0x1f
|
||||||
|
orr r0, r0, #0xd3
|
||||||
|
msr cpsr,r0
|
||||||
|
|
||||||
|
#if (CONFIG_OMAP34XX)
|
||||||
|
/* Copy vectors to mask ROM indirect addr */
|
||||||
|
adr r0, _start @ r0 <- current position of code
|
||||||
|
add r0, r0, #4 @ skip reset vector
|
||||||
|
mov r2, #64 @ r2 <- size to copy
|
||||||
|
add r2, r0, r2 @ r2 <- source end address
|
||||||
|
mov r1, #SRAM_OFFSET0 @ build vect addr
|
||||||
|
mov r3, #SRAM_OFFSET1
|
||||||
|
add r1, r1, r3
|
||||||
|
mov r3, #SRAM_OFFSET2
|
||||||
|
add r1, r1, r3
|
||||||
|
next:
|
||||||
|
ldmia r0!, {r3 - r10} @ copy from source address [r0]
|
||||||
|
stmia r1!, {r3 - r10} @ copy to target address [r1]
|
||||||
|
cmp r0, r2 @ until source end address [r2]
|
||||||
|
bne next @ loop until equal */
|
||||||
|
#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
|
||||||
|
/* No need to copy/exec the clock code - DPLL adjust already done
|
||||||
|
* in NAND/oneNAND Boot.
|
||||||
|
*/
|
||||||
|
bl cpy_clk_code @ put dpll adjust code behind vectors
|
||||||
|
#endif /* NAND Boot */
|
||||||
|
#endif
|
||||||
|
/* the mask ROM code should have PLL and others stable */
|
||||||
|
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||||
|
bl cpu_init_crit
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Set stackpointer in internal RAM to call board_init_f */
|
||||||
|
call_board_init_f:
|
||||||
|
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
|
||||||
|
ldr r0,=0x00000000
|
||||||
|
bl board_init_f
|
||||||
|
|
||||||
|
/*------------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* void relocate_code (addr_sp, gd, addr_moni)
|
||||||
|
*
|
||||||
|
* This "function" does not return, instead it continues in RAM
|
||||||
|
* after relocating the monitor code.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
.globl relocate_code
|
||||||
|
relocate_code:
|
||||||
|
mov r4, r0 /* save addr_sp */
|
||||||
|
mov r5, r1 /* save addr of gd */
|
||||||
|
mov r6, r2 /* save addr of destination */
|
||||||
|
mov r7, r2 /* save addr of destination */
|
||||||
|
|
||||||
|
/* Set up the stack */
|
||||||
|
stack_setup:
|
||||||
|
mov sp, r4
|
||||||
|
|
||||||
|
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
|
||||||
|
adr r0, _start
|
||||||
|
ldr r2, _TEXT_BASE
|
||||||
|
ldr r3, _bss_start
|
||||||
|
sub r2, r3, r2 /* r2 <- size of armboot */
|
||||||
|
add r2, r0, r2 /* r2 <- source end address */
|
||||||
|
cmp r0, r6
|
||||||
|
#ifndef CONFIG_PRELOADER
|
||||||
|
beq jump_2_ram
|
||||||
|
#endif
|
||||||
|
|
||||||
|
copy_loop:
|
||||||
|
ldmia r0!, {r9-r10} /* copy from source address [r0] */
|
||||||
|
stmia r6!, {r9-r10} /* copy to target address [r1] */
|
||||||
|
cmp r0, r2 /* until source end addreee [r2] */
|
||||||
|
ble copy_loop
|
||||||
|
|
||||||
|
#ifndef CONFIG_PRELOADER
|
||||||
|
/* fix got entries */
|
||||||
|
ldr r1, _TEXT_BASE
|
||||||
|
mov r0, r7 /* reloc addr */
|
||||||
|
ldr r2, _got_start /* addr in Flash */
|
||||||
|
ldr r3, _got_end /* addr in Flash */
|
||||||
|
sub r3, r3, r1
|
||||||
|
add r3, r3, r0
|
||||||
|
sub r2, r2, r1
|
||||||
|
add r2, r2, r0
|
||||||
|
|
||||||
|
fixloop:
|
||||||
|
ldr r4, [r2]
|
||||||
|
sub r4, r4, r1
|
||||||
|
add r4, r4, r0
|
||||||
|
str r4, [r2]
|
||||||
|
add r2, r2, #4
|
||||||
|
cmp r2, r3
|
||||||
|
bne fixloop
|
||||||
|
|
||||||
|
clear_bss:
|
||||||
|
ldr r0, _bss_start
|
||||||
|
ldr r1, _bss_end
|
||||||
|
ldr r3, _TEXT_BASE /* Text base */
|
||||||
|
mov r4, r7 /* reloc addr */
|
||||||
|
sub r0, r0, r3
|
||||||
|
add r0, r0, r4
|
||||||
|
sub r1, r1, r3
|
||||||
|
add r1, r1, r4
|
||||||
|
mov r2, #0x00000000 /* clear */
|
||||||
|
|
||||||
|
clbss_l:str r2, [r0] /* clear loop... */
|
||||||
|
add r0, r0, #4
|
||||||
|
cmp r0, r1
|
||||||
|
bne clbss_l
|
||||||
|
#endif /* #ifndef CONFIG_PRELOADER */
|
||||||
|
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We are done. Do not return, instead branch to second part of board
|
||||||
|
* initialization, now running from RAM.
|
||||||
|
*/
|
||||||
|
jump_2_ram:
|
||||||
|
ldr r0, _TEXT_BASE
|
||||||
|
ldr r2, _board_init_r
|
||||||
|
sub r2, r2, r0
|
||||||
|
add r2, r2, r7 /* position from board_init_r in RAM */
|
||||||
|
/* setup parameters for board_init_r */
|
||||||
|
mov r0, r5 /* gd_t */
|
||||||
|
mov r1, r7 /* dest_addr */
|
||||||
|
/* jump to it ... */
|
||||||
|
mov lr, r2
|
||||||
|
mov pc, lr
|
||||||
|
|
||||||
|
_board_init_r: .word board_init_r
|
||||||
|
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||||
/*
|
/*
|
||||||
* the actual reset code
|
* the actual reset code
|
||||||
*/
|
*/
|
||||||
@ -180,7 +353,7 @@ clbss_l:
|
|||||||
ldr pc, _start_armboot @ jump to C code
|
ldr pc, _start_armboot @ jump to C code
|
||||||
|
|
||||||
_start_armboot: .word start_armboot
|
_start_armboot: .word start_armboot
|
||||||
|
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||||
|
|
||||||
/*************************************************************************
|
/*************************************************************************
|
||||||
*
|
*
|
||||||
@ -263,11 +436,14 @@ cpu_init_crit:
|
|||||||
@ user stack
|
@ user stack
|
||||||
stmia sp, {r0 - r12} @ Save user registers (now in
|
stmia sp, {r0 - r12} @ Save user registers (now in
|
||||||
@ svc mode) r0-r12
|
@ svc mode) r0-r12
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
ldr r2, _armboot_start
|
ldr r2, _armboot_start
|
||||||
sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
|
sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
|
||||||
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ set base 2 words into abort
|
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ set base 2 words into abort
|
||||||
|
#else
|
||||||
|
ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort
|
||||||
@ stack
|
@ stack
|
||||||
|
#endif
|
||||||
ldmia r2, {r2 - r3} @ get values for "aborted" pc
|
ldmia r2, {r2 - r3} @ get values for "aborted" pc
|
||||||
@ and cpsr (into parm regs)
|
@ and cpsr (into parm regs)
|
||||||
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
|
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
|
||||||
@ -303,11 +479,14 @@ cpu_init_crit:
|
|||||||
.endm
|
.endm
|
||||||
|
|
||||||
.macro get_bad_stack
|
.macro get_bad_stack
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
ldr r13, _armboot_start @ setup our mode stack (enter
|
ldr r13, _armboot_start @ setup our mode stack (enter
|
||||||
@ in banked mode)
|
|
||||||
sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
|
sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
|
||||||
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ move to reserved a couple
|
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ move to reserved a couple
|
||||||
@ spots for abort stack
|
#else
|
||||||
|
ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter
|
||||||
|
@ in banked mode)
|
||||||
|
#endif
|
||||||
|
|
||||||
str lr, [r13] @ save caller lr in position 0
|
str lr, [r13] @ save caller lr in position 0
|
||||||
@ of saved stack
|
@ of saved stack
|
||||||
@ -328,10 +507,14 @@ cpu_init_crit:
|
|||||||
sub r13, r13, #4 @ space on current stack for
|
sub r13, r13, #4 @ space on current stack for
|
||||||
@ scratch reg.
|
@ scratch reg.
|
||||||
str r0, [r13] @ save R0's value.
|
str r0, [r13] @ save R0's value.
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
ldr r0, _armboot_start @ get data regions start
|
ldr r0, _armboot_start @ get data regions start
|
||||||
sub r0, r0, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
|
sub r0, r0, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
|
||||||
sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ move past gbl and a couple
|
sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ move past gbl and a couple
|
||||||
|
#else
|
||||||
|
ldr r0, IRQ_STACK_START_IN @ get data regions start
|
||||||
@ spots for abort stack
|
@ spots for abort stack
|
||||||
|
#endif
|
||||||
str lr, [r0] @ save caller lr in position 0
|
str lr, [r0] @ save caller lr in position 0
|
||||||
@ of saved stack
|
@ of saved stack
|
||||||
mrs r0, spsr @ get the spsr
|
mrs r0, spsr @ get the spsr
|
||||||
|
@ -42,10 +42,22 @@ SECTIONS
|
|||||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||||
|
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
.data : { *(.data) }
|
.data : {
|
||||||
|
*(.data)
|
||||||
|
__datarel_start = .;
|
||||||
|
*(.data.rel)
|
||||||
|
__datarelrolocal_start = .;
|
||||||
|
*(.data.rel.ro.local)
|
||||||
|
__datarellocal_start = .;
|
||||||
|
*(.data.rel.local)
|
||||||
|
__datarelro_start = .;
|
||||||
|
*(.data.rel.ro)
|
||||||
|
}
|
||||||
|
|
||||||
|
__got_start = .;
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
.got : { *(.got) }
|
.got : { *(.got) }
|
||||||
|
__got_end = .;
|
||||||
|
|
||||||
__u_boot_cmd_start = .;
|
__u_boot_cmd_start = .;
|
||||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||||
|
@ -93,12 +93,15 @@ _fiq: .word fiq
|
|||||||
* - jump to second stage
|
* - jump to second stage
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
.globl _TEXT_BASE
|
||||||
_TEXT_BASE:
|
_TEXT_BASE:
|
||||||
.word TEXT_BASE
|
.word TEXT_BASE
|
||||||
|
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
.globl _armboot_start
|
.globl _armboot_start
|
||||||
_armboot_start:
|
_armboot_start:
|
||||||
.word _start
|
.word _start
|
||||||
|
#endif
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* These are defined in the board-specific linker script.
|
* These are defined in the board-specific linker script.
|
||||||
@ -123,6 +126,274 @@ FIQ_STACK_START:
|
|||||||
.word 0x0badc0de
|
.word 0x0badc0de
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
|
/* IRQ stack memory (calculated at run-time) + 8 bytes */
|
||||||
|
.globl IRQ_STACK_START_IN
|
||||||
|
IRQ_STACK_START_IN:
|
||||||
|
.word 0x0badc0de
|
||||||
|
|
||||||
|
.globl _datarel_start
|
||||||
|
_datarel_start:
|
||||||
|
.word __datarel_start
|
||||||
|
|
||||||
|
.globl _datarelrolocal_start
|
||||||
|
_datarelrolocal_start:
|
||||||
|
.word __datarelrolocal_start
|
||||||
|
|
||||||
|
.globl _datarellocal_start
|
||||||
|
_datarellocal_start:
|
||||||
|
.word __datarellocal_start
|
||||||
|
|
||||||
|
.globl _datarelro_start
|
||||||
|
_datarelro_start:
|
||||||
|
.word __datarelro_start
|
||||||
|
|
||||||
|
.globl _got_start
|
||||||
|
_got_start:
|
||||||
|
.word __got_start
|
||||||
|
|
||||||
|
.globl _got_end
|
||||||
|
_got_end:
|
||||||
|
.word __got_end
|
||||||
|
|
||||||
|
/*
|
||||||
|
* the actual reset code
|
||||||
|
*/
|
||||||
|
|
||||||
|
reset:
|
||||||
|
/* disable mmu, set big-endian */
|
||||||
|
mov r0, #0xf8
|
||||||
|
mcr p15, 0, r0, c1, c0, 0
|
||||||
|
CPWAIT r0
|
||||||
|
|
||||||
|
/* invalidate I & D caches & BTB */
|
||||||
|
mcr p15, 0, r0, c7, c7, 0
|
||||||
|
CPWAIT r0
|
||||||
|
|
||||||
|
/* invalidate I & Data TLB */
|
||||||
|
mcr p15, 0, r0, c8, c7, 0
|
||||||
|
CPWAIT r0
|
||||||
|
|
||||||
|
/* drain write and fill buffers */
|
||||||
|
mcr p15, 0, r0, c7, c10, 4
|
||||||
|
CPWAIT r0
|
||||||
|
|
||||||
|
/* disable write buffer coalescing */
|
||||||
|
mrc p15, 0, r0, c1, c0, 1
|
||||||
|
orr r0, r0, #1
|
||||||
|
mcr p15, 0, r0, c1, c0, 1
|
||||||
|
CPWAIT r0
|
||||||
|
|
||||||
|
/* set EXP CS0 to the optimum timing */
|
||||||
|
ldr r1, =CONFIG_SYS_EXP_CS0
|
||||||
|
ldr r2, =IXP425_EXP_CS0
|
||||||
|
str r1, [r2]
|
||||||
|
|
||||||
|
/* make sure flash is visible at 0 */
|
||||||
|
#if 0
|
||||||
|
ldr r2, =IXP425_EXP_CFG0
|
||||||
|
ldr r1, [r2]
|
||||||
|
orr r1, r1, #0x80000000
|
||||||
|
str r1, [r2]
|
||||||
|
#endif
|
||||||
|
mov r1, #CONFIG_SYS_SDR_CONFIG
|
||||||
|
ldr r2, =IXP425_SDR_CONFIG
|
||||||
|
str r1, [r2]
|
||||||
|
|
||||||
|
/* disable refresh cycles */
|
||||||
|
mov r1, #0
|
||||||
|
ldr r3, =IXP425_SDR_REFRESH
|
||||||
|
str r1, [r3]
|
||||||
|
|
||||||
|
/* send nop command */
|
||||||
|
mov r1, #3
|
||||||
|
ldr r4, =IXP425_SDR_IR
|
||||||
|
str r1, [r4]
|
||||||
|
DELAY_FOR 0x4000, r0
|
||||||
|
|
||||||
|
/* set SDRAM internal refresh val */
|
||||||
|
ldr r1, =CONFIG_SYS_SDRAM_REFRESH_CNT
|
||||||
|
str r1, [r3]
|
||||||
|
DELAY_FOR 0x4000, r0
|
||||||
|
|
||||||
|
/* send precharge-all command to close all open banks */
|
||||||
|
mov r1, #2
|
||||||
|
str r1, [r4]
|
||||||
|
DELAY_FOR 0x4000, r0
|
||||||
|
|
||||||
|
/* provide 8 auto-refresh cycles */
|
||||||
|
mov r1, #4
|
||||||
|
mov r5, #8
|
||||||
|
111: str r1, [r4]
|
||||||
|
DELAY_FOR 0x100, r0
|
||||||
|
subs r5, r5, #1
|
||||||
|
bne 111b
|
||||||
|
|
||||||
|
/* set mode register in sdram */
|
||||||
|
mov r1, #CONFIG_SYS_SDR_MODE_CONFIG
|
||||||
|
str r1, [r4]
|
||||||
|
DELAY_FOR 0x4000, r0
|
||||||
|
|
||||||
|
/* send normal operation command */
|
||||||
|
mov r1, #6
|
||||||
|
str r1, [r4]
|
||||||
|
DELAY_FOR 0x4000, r0
|
||||||
|
|
||||||
|
/* copy */
|
||||||
|
mov r0, #0
|
||||||
|
mov r4, r0
|
||||||
|
add r2, r0, #CONFIG_SYS_MONITOR_LEN
|
||||||
|
mov r1, #0x10000000
|
||||||
|
mov r5, r1
|
||||||
|
|
||||||
|
30:
|
||||||
|
ldr r3, [r0], #4
|
||||||
|
str r3, [r1], #4
|
||||||
|
cmp r0, r2
|
||||||
|
bne 30b
|
||||||
|
|
||||||
|
/* invalidate I & D caches & BTB */
|
||||||
|
mcr p15, 0, r0, c7, c7, 0
|
||||||
|
CPWAIT r0
|
||||||
|
|
||||||
|
/* invalidate I & Data TLB */
|
||||||
|
mcr p15, 0, r0, c8, c7, 0
|
||||||
|
CPWAIT r0
|
||||||
|
|
||||||
|
/* drain write and fill buffers */
|
||||||
|
mcr p15, 0, r0, c7, c10, 4
|
||||||
|
CPWAIT r0
|
||||||
|
|
||||||
|
/* move flash to 0x50000000 */
|
||||||
|
ldr r2, =IXP425_EXP_CFG0
|
||||||
|
ldr r1, [r2]
|
||||||
|
bic r1, r1, #0x80000000
|
||||||
|
str r1, [r2]
|
||||||
|
|
||||||
|
nop
|
||||||
|
nop
|
||||||
|
nop
|
||||||
|
nop
|
||||||
|
nop
|
||||||
|
nop
|
||||||
|
|
||||||
|
/* invalidate I & Data TLB */
|
||||||
|
mcr p15, 0, r0, c8, c7, 0
|
||||||
|
CPWAIT r0
|
||||||
|
|
||||||
|
/* enable I cache */
|
||||||
|
mrc p15, 0, r0, c1, c0, 0
|
||||||
|
orr r0, r0, #MMU_Control_I
|
||||||
|
mcr p15, 0, r0, c1, c0, 0
|
||||||
|
CPWAIT r0
|
||||||
|
|
||||||
|
mrs r0,cpsr /* set the cpu to SVC32 mode */
|
||||||
|
bic r0,r0,#0x1f /* (superviser mode, M=10011) */
|
||||||
|
orr r0,r0,#0x13
|
||||||
|
msr cpsr,r0
|
||||||
|
|
||||||
|
/* Set stackpointer in internal RAM to call board_init_f */
|
||||||
|
call_board_init_f:
|
||||||
|
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
|
||||||
|
ldr r0,=0x00000000
|
||||||
|
bl board_init_f
|
||||||
|
|
||||||
|
/*------------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* void relocate_code (addr_sp, gd, addr_moni)
|
||||||
|
*
|
||||||
|
* This "function" does not return, instead it continues in RAM
|
||||||
|
* after relocating the monitor code.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
.globl relocate_code
|
||||||
|
relocate_code:
|
||||||
|
mov r4, r0 /* save addr_sp */
|
||||||
|
mov r5, r1 /* save addr of gd */
|
||||||
|
mov r6, r2 /* save addr of destination */
|
||||||
|
mov r7, r2 /* save addr of destination */
|
||||||
|
|
||||||
|
/* Set up the stack */
|
||||||
|
stack_setup:
|
||||||
|
mov sp, r4
|
||||||
|
|
||||||
|
adr r0, _start
|
||||||
|
ldr r2, _TEXT_BASE
|
||||||
|
ldr r3, _bss_start
|
||||||
|
sub r2, r3, r2 /* r2 <- size of armboot */
|
||||||
|
add r2, r0, r2 /* r2 <- source end address */
|
||||||
|
cmp r0, r6
|
||||||
|
beq clear_bss
|
||||||
|
|
||||||
|
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
|
||||||
|
copy_loop:
|
||||||
|
ldmia r0!, {r9-r10} /* copy from source address [r0] */
|
||||||
|
stmia r6!, {r9-r10} /* copy to target address [r1] */
|
||||||
|
cmp r0, r2 /* until source end addreee [r2] */
|
||||||
|
ble copy_loop
|
||||||
|
|
||||||
|
#ifndef CONFIG_PRELOADER
|
||||||
|
/* fix got entries */
|
||||||
|
ldr r1, _TEXT_BASE /* Text base */
|
||||||
|
mov r0, r7 /* reloc addr */
|
||||||
|
ldr r2, _got_start /* addr in Flash */
|
||||||
|
ldr r3, _got_end /* addr in Flash */
|
||||||
|
sub r3, r3, r1
|
||||||
|
add r3, r3, r0
|
||||||
|
sub r2, r2, r1
|
||||||
|
add r2, r2, r0
|
||||||
|
|
||||||
|
fixloop:
|
||||||
|
ldr r4, [r2]
|
||||||
|
sub r4, r4, r1
|
||||||
|
add r4, r4, r0
|
||||||
|
str r4, [r2]
|
||||||
|
add r2, r2, #4
|
||||||
|
cmp r2, r3
|
||||||
|
bne fixloop
|
||||||
|
#endif
|
||||||
|
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
|
||||||
|
|
||||||
|
clear_bss:
|
||||||
|
#ifndef CONFIG_PRELOADER
|
||||||
|
ldr r0, _bss_start
|
||||||
|
ldr r1, _bss_end
|
||||||
|
ldr r3, _TEXT_BASE /* Text base */
|
||||||
|
mov r4, r7 /* reloc addr */
|
||||||
|
sub r0, r0, r3
|
||||||
|
add r0, r0, r4
|
||||||
|
sub r1, r1, r3
|
||||||
|
add r1, r1, r4
|
||||||
|
mov r2, #0x00000000 /* clear */
|
||||||
|
|
||||||
|
clbss_l:str r2, [r0] /* clear loop... */
|
||||||
|
add r0, r0, #4
|
||||||
|
cmp r0, r1
|
||||||
|
bne clbss_l
|
||||||
|
|
||||||
|
bl coloured_LED_init
|
||||||
|
bl red_LED_on
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We are done. Do not return, instead branch to second part of board
|
||||||
|
* initialization, now running from RAM.
|
||||||
|
*/
|
||||||
|
ldr r0, _TEXT_BASE
|
||||||
|
ldr r2, _board_init_r
|
||||||
|
sub r2, r2, r0
|
||||||
|
add r2, r2, r7 /* position from board_init_r in RAM */
|
||||||
|
/* setup parameters for board_init_r */
|
||||||
|
mov r0, r5 /* gd_t */
|
||||||
|
mov r1, r7 /* dest_addr */
|
||||||
|
/* jump to it ... */
|
||||||
|
mov lr, r2
|
||||||
|
mov pc, lr
|
||||||
|
|
||||||
|
_board_init_r: .word board_init_r
|
||||||
|
|
||||||
|
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||||
/****************************************************************************/
|
/****************************************************************************/
|
||||||
/* */
|
/* */
|
||||||
/* the actual reset code */
|
/* the actual reset code */
|
||||||
@ -304,6 +575,7 @@ clbss_l:str r2, [r0] /* clear loop... */
|
|||||||
ldr pc, _start_armboot
|
ldr pc, _start_armboot
|
||||||
|
|
||||||
_start_armboot: .word start_armboot
|
_start_armboot: .word start_armboot
|
||||||
|
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||||
|
|
||||||
|
|
||||||
/****************************************************************************/
|
/****************************************************************************/
|
||||||
@ -345,9 +617,13 @@ _start_armboot: .word start_armboot
|
|||||||
stmia sp, {r0 - r12} /* Calling r0-r12 */
|
stmia sp, {r0 - r12} /* Calling r0-r12 */
|
||||||
add r8, sp, #S_PC
|
add r8, sp, #S_PC
|
||||||
|
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
ldr r2, _armboot_start
|
ldr r2, _armboot_start
|
||||||
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
||||||
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
|
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
|
||||||
|
#else
|
||||||
|
ldr r2, IRQ_STACK_START_IN
|
||||||
|
#endif
|
||||||
ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
|
ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
|
||||||
add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
|
add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
|
||||||
|
|
||||||
@ -382,9 +658,13 @@ _start_armboot: .word start_armboot
|
|||||||
.endm
|
.endm
|
||||||
|
|
||||||
.macro get_bad_stack
|
.macro get_bad_stack
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
ldr r13, _armboot_start @ setup our mode stack
|
ldr r13, _armboot_start @ setup our mode stack
|
||||||
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
||||||
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
|
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
|
||||||
|
#else
|
||||||
|
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
|
||||||
|
#endif
|
||||||
|
|
||||||
str lr, [r13] @ save caller lr / spsr
|
str lr, [r13] @ save caller lr / spsr
|
||||||
mrs lr, spsr
|
mrs lr, spsr
|
||||||
|
@ -39,11 +39,23 @@ SECTIONS
|
|||||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||||
|
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
.data : { *(.data) }
|
.data : {
|
||||||
|
*(.data)
|
||||||
|
__datarel_start = .;
|
||||||
|
*(.data.rel)
|
||||||
|
__datarelrolocal_start = .;
|
||||||
|
*(.data.rel.ro.local)
|
||||||
|
__datarellocal_start = .;
|
||||||
|
*(.data.rel.local)
|
||||||
|
__datarelro_start = .;
|
||||||
|
*(.data.rel.ro)
|
||||||
|
}
|
||||||
|
|
||||||
|
__got_start = .;
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
.got : { *(.got) }
|
.got : { *(.got) }
|
||||||
|
|
||||||
|
__got_end = .;
|
||||||
. = .;
|
. = .;
|
||||||
__u_boot_cmd_start = .;
|
__u_boot_cmd_start = .;
|
||||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||||
|
@ -72,12 +72,15 @@ _fiq: .word fiq
|
|||||||
*************************************************************************
|
*************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
.globl _TEXT_BASE
|
||||||
_TEXT_BASE:
|
_TEXT_BASE:
|
||||||
.word TEXT_BASE
|
.word TEXT_BASE
|
||||||
|
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
.globl _armboot_start
|
.globl _armboot_start
|
||||||
_armboot_start:
|
_armboot_start:
|
||||||
.word _start
|
.word _start
|
||||||
|
#endif
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* These are defined in the board-specific linker script.
|
* These are defined in the board-specific linker script.
|
||||||
@ -102,7 +105,181 @@ FIQ_STACK_START:
|
|||||||
.word 0x0badc0de
|
.word 0x0badc0de
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
|
/* IRQ stack memory (calculated at run-time) + 8 bytes */
|
||||||
|
.globl IRQ_STACK_START_IN
|
||||||
|
IRQ_STACK_START_IN:
|
||||||
|
.word 0x0badc0de
|
||||||
|
|
||||||
|
.globl _datarel_start
|
||||||
|
_datarel_start:
|
||||||
|
.word __datarel_start
|
||||||
|
|
||||||
|
.globl _datarelrolocal_start
|
||||||
|
_datarelrolocal_start:
|
||||||
|
.word __datarelrolocal_start
|
||||||
|
|
||||||
|
.globl _datarellocal_start
|
||||||
|
_datarellocal_start:
|
||||||
|
.word __datarellocal_start
|
||||||
|
|
||||||
|
.globl _datarelro_start
|
||||||
|
_datarelro_start:
|
||||||
|
.word __datarelro_start
|
||||||
|
|
||||||
|
.globl _got_start
|
||||||
|
_got_start:
|
||||||
|
.word __got_start
|
||||||
|
|
||||||
|
.globl _got_end
|
||||||
|
_got_end:
|
||||||
|
.word __got_end
|
||||||
|
|
||||||
|
/*
|
||||||
|
* the actual reset code
|
||||||
|
*/
|
||||||
|
|
||||||
|
reset:
|
||||||
|
/*
|
||||||
|
* set the cpu to SVC32 mode
|
||||||
|
*/
|
||||||
|
mrs r0,cpsr
|
||||||
|
bic r0,r0,#0x1f
|
||||||
|
orr r0,r0,#0xd3
|
||||||
|
msr cpsr,r0
|
||||||
|
|
||||||
|
#define pWDTCTL 0x80001400 /* Watchdog Timer control register */
|
||||||
|
#define pINTENC 0x8000050C /* Interupt-Controller enable clear register */
|
||||||
|
#define pCLKSET 0x80000420 /* clock divisor register */
|
||||||
|
|
||||||
|
/* disable watchdog, set watchdog control register to
|
||||||
|
* all zeros (default reset)
|
||||||
|
*/
|
||||||
|
ldr r0, =pWDTCTL
|
||||||
|
mov r1, #0x0
|
||||||
|
str r1, [r0]
|
||||||
|
|
||||||
|
/*
|
||||||
|
* mask all IRQs by setting all bits in the INTENC register (default)
|
||||||
|
*/
|
||||||
|
mov r1, #0xffffffff
|
||||||
|
ldr r0, =pINTENC
|
||||||
|
str r1, [r0]
|
||||||
|
|
||||||
|
/* FCLK:HCLK:PCLK = 1:2:2 */
|
||||||
|
/* default FCLK is 200 MHz, using 14.7456 MHz fin */
|
||||||
|
ldr r0, =pCLKSET
|
||||||
|
ldr r1, =0x0004ee39
|
||||||
|
@ ldr r1, =0x0005ee39 @ 1: 2: 4
|
||||||
|
str r1, [r0]
|
||||||
|
|
||||||
|
/*
|
||||||
|
* we do sys-critical inits only at reboot,
|
||||||
|
* not when booting from ram!
|
||||||
|
*/
|
||||||
|
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||||
|
bl cpu_init_crit
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Set stackpointer in internal RAM to call board_init_f */
|
||||||
|
call_board_init_f:
|
||||||
|
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
|
||||||
|
ldr r0,=0x00000000
|
||||||
|
bl board_init_f
|
||||||
|
|
||||||
|
/*------------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* void relocate_code (addr_sp, gd, addr_moni)
|
||||||
|
*
|
||||||
|
* This "function" does not return, instead it continues in RAM
|
||||||
|
* after relocating the monitor code.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
.globl relocate_code
|
||||||
|
relocate_code:
|
||||||
|
mov r4, r0 /* save addr_sp */
|
||||||
|
mov r5, r1 /* save addr of gd */
|
||||||
|
mov r6, r2 /* save addr of destination */
|
||||||
|
mov r7, r2 /* save addr of destination */
|
||||||
|
|
||||||
|
/* Set up the stack */
|
||||||
|
stack_setup:
|
||||||
|
mov sp, r4
|
||||||
|
|
||||||
|
adr r0, _start
|
||||||
|
ldr r2, _TEXT_BASE
|
||||||
|
ldr r3, _bss_start
|
||||||
|
sub r2, r3, r2 /* r2 <- size of armboot */
|
||||||
|
add r2, r0, r2 /* r2 <- source end address */
|
||||||
|
cmp r0, r6
|
||||||
|
beq clear_bss
|
||||||
|
|
||||||
|
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
|
||||||
|
copy_loop:
|
||||||
|
ldmia r0!, {r9-r10} /* copy from source address [r0] */
|
||||||
|
stmia r6!, {r9-r10} /* copy to target address [r1] */
|
||||||
|
cmp r0, r2 /* until source end addreee [r2] */
|
||||||
|
ble copy_loop
|
||||||
|
|
||||||
|
#ifndef CONFIG_PRELOADER
|
||||||
|
/* fix got entries */
|
||||||
|
ldr r1, _TEXT_BASE /* Text base */
|
||||||
|
mov r0, r7 /* reloc addr */
|
||||||
|
ldr r2, _got_start /* addr in Flash */
|
||||||
|
ldr r3, _got_end /* addr in Flash */
|
||||||
|
sub r3, r3, r1
|
||||||
|
add r3, r3, r0
|
||||||
|
sub r2, r2, r1
|
||||||
|
add r2, r2, r0
|
||||||
|
|
||||||
|
fixloop:
|
||||||
|
ldr r4, [r2]
|
||||||
|
sub r4, r4, r1
|
||||||
|
add r4, r4, r0
|
||||||
|
str r4, [r2]
|
||||||
|
add r2, r2, #4
|
||||||
|
cmp r2, r3
|
||||||
|
bne fixloop
|
||||||
|
#endif
|
||||||
|
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
|
||||||
|
|
||||||
|
clear_bss:
|
||||||
|
#ifndef CONFIG_PRELOADER
|
||||||
|
ldr r0, _bss_start
|
||||||
|
ldr r1, _bss_end
|
||||||
|
ldr r3, _TEXT_BASE /* Text base */
|
||||||
|
mov r4, r7 /* reloc addr */
|
||||||
|
sub r0, r0, r3
|
||||||
|
add r0, r0, r4
|
||||||
|
sub r1, r1, r3
|
||||||
|
add r1, r1, r4
|
||||||
|
mov r2, #0x00000000 /* clear */
|
||||||
|
|
||||||
|
clbss_l:str r2, [r0] /* clear loop... */
|
||||||
|
add r0, r0, #4
|
||||||
|
cmp r0, r1
|
||||||
|
bne clbss_l
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We are done. Do not return, instead branch to second part of board
|
||||||
|
* initialization, now running from RAM.
|
||||||
|
*/
|
||||||
|
ldr r0, _TEXT_BASE
|
||||||
|
ldr r2, _board_init_r
|
||||||
|
sub r2, r2, r0
|
||||||
|
add r2, r2, r7 /* position from board_init_r in RAM */
|
||||||
|
/* setup parameters for board_init_r */
|
||||||
|
mov r0, r5 /* gd_t */
|
||||||
|
mov r1, r7 /* dest_addr */
|
||||||
|
/* jump to it ... */
|
||||||
|
mov lr, r2
|
||||||
|
mov pc, lr
|
||||||
|
|
||||||
|
_board_init_r: .word board_init_r
|
||||||
|
|
||||||
|
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||||
/*
|
/*
|
||||||
* the actual reset code
|
* the actual reset code
|
||||||
*/
|
*/
|
||||||
@ -195,7 +372,7 @@ clbss_l:str r2, [r0] /* clear loop... */
|
|||||||
ldr pc, _start_armboot
|
ldr pc, _start_armboot
|
||||||
|
|
||||||
_start_armboot: .word start_armboot
|
_start_armboot: .word start_armboot
|
||||||
|
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
*************************************************************************
|
*************************************************************************
|
||||||
@ -285,9 +462,13 @@ cpu_init_crit:
|
|||||||
.macro bad_save_user_regs
|
.macro bad_save_user_regs
|
||||||
sub sp, sp, #S_FRAME_SIZE
|
sub sp, sp, #S_FRAME_SIZE
|
||||||
stmia sp, {r0 - r12} @ Calling r0-r12
|
stmia sp, {r0 - r12} @ Calling r0-r12
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
ldr r2, _armboot_start
|
ldr r2, _armboot_start
|
||||||
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
||||||
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
|
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
|
||||||
|
#else
|
||||||
|
ldr r2, IRQ_STACK_START_IN
|
||||||
|
#endif
|
||||||
ldmia r2, {r2 - r3} @ get pc, cpsr
|
ldmia r2, {r2 - r3} @ get pc, cpsr
|
||||||
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
|
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
|
||||||
|
|
||||||
@ -318,9 +499,13 @@ cpu_init_crit:
|
|||||||
.endm
|
.endm
|
||||||
|
|
||||||
.macro get_bad_stack
|
.macro get_bad_stack
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
ldr r13, _armboot_start @ setup our mode stack
|
ldr r13, _armboot_start @ setup our mode stack
|
||||||
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
||||||
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
|
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
|
||||||
|
#else
|
||||||
|
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
|
||||||
|
#endif
|
||||||
|
|
||||||
str lr, [r13] @ save caller lr / spsr
|
str lr, [r13] @ save caller lr / spsr
|
||||||
mrs lr, spsr
|
mrs lr, spsr
|
||||||
|
@ -39,11 +39,23 @@ SECTIONS
|
|||||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||||
|
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
.data : { *(.data) }
|
.data : {
|
||||||
|
*(.data)
|
||||||
|
__datarel_start = .;
|
||||||
|
*(.data.rel)
|
||||||
|
__datarelrolocal_start = .;
|
||||||
|
*(.data.rel.ro.local)
|
||||||
|
__datarellocal_start = .;
|
||||||
|
*(.data.rel.local)
|
||||||
|
__datarelro_start = .;
|
||||||
|
*(.data.rel.ro)
|
||||||
|
}
|
||||||
|
|
||||||
|
__got_start = .;
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
.got : { *(.got) }
|
.got : { *(.got) }
|
||||||
|
|
||||||
|
__got_end = .;
|
||||||
. = .;
|
. = .;
|
||||||
__u_boot_cmd_start = .;
|
__u_boot_cmd_start = .;
|
||||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||||
|
@ -82,12 +82,15 @@ _fiq: .word fiq
|
|||||||
* - jump to second stage
|
* - jump to second stage
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
.globl _TEXT_BASE
|
||||||
_TEXT_BASE:
|
_TEXT_BASE:
|
||||||
.word TEXT_BASE
|
.word TEXT_BASE
|
||||||
|
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
.globl _armboot_start
|
.globl _armboot_start
|
||||||
_armboot_start:
|
_armboot_start:
|
||||||
.word _start
|
.word _start
|
||||||
|
#endif
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* These are defined in the board-specific linker script.
|
* These are defined in the board-specific linker script.
|
||||||
@ -112,6 +115,162 @@ FIQ_STACK_START:
|
|||||||
.word 0x0badc0de
|
.word 0x0badc0de
|
||||||
#endif /* CONFIG_USE_IRQ */
|
#endif /* CONFIG_USE_IRQ */
|
||||||
|
|
||||||
|
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
|
/* IRQ stack memory (calculated at run-time) + 8 bytes */
|
||||||
|
.globl IRQ_STACK_START_IN
|
||||||
|
IRQ_STACK_START_IN:
|
||||||
|
.word 0x0badc0de
|
||||||
|
|
||||||
|
.globl _datarel_start
|
||||||
|
_datarel_start:
|
||||||
|
.word __datarel_start
|
||||||
|
|
||||||
|
.globl _datarelrolocal_start
|
||||||
|
_datarelrolocal_start:
|
||||||
|
.word __datarelrolocal_start
|
||||||
|
|
||||||
|
.globl _datarellocal_start
|
||||||
|
_datarellocal_start:
|
||||||
|
.word __datarellocal_start
|
||||||
|
|
||||||
|
.globl _datarelro_start
|
||||||
|
_datarelro_start:
|
||||||
|
.word __datarelro_start
|
||||||
|
|
||||||
|
.globl _got_start
|
||||||
|
_got_start:
|
||||||
|
.word __got_start
|
||||||
|
|
||||||
|
.globl _got_end
|
||||||
|
_got_end:
|
||||||
|
.word __got_end
|
||||||
|
|
||||||
|
/*
|
||||||
|
* the actual reset code
|
||||||
|
*/
|
||||||
|
|
||||||
|
reset:
|
||||||
|
/*
|
||||||
|
* set the cpu to SVC32 mode
|
||||||
|
*/
|
||||||
|
mrs r0,cpsr
|
||||||
|
bic r0,r0,#0x1f
|
||||||
|
orr r0,r0,#0xd3
|
||||||
|
msr cpsr,r0
|
||||||
|
|
||||||
|
/*
|
||||||
|
* we do sys-critical inits only at reboot,
|
||||||
|
* not when booting from ram!
|
||||||
|
*/
|
||||||
|
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||||
|
bl cpu_init_crit
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Set stackpointer in internal RAM to call board_init_f */
|
||||||
|
call_board_init_f:
|
||||||
|
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
|
||||||
|
ldr r0,=0x00000000
|
||||||
|
bl board_init_f
|
||||||
|
|
||||||
|
/*------------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* void relocate_code (addr_sp, gd, addr_moni)
|
||||||
|
*
|
||||||
|
* This "function" does not return, instead it continues in RAM
|
||||||
|
* after relocating the monitor code.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
.globl relocate_code
|
||||||
|
relocate_code:
|
||||||
|
mov r4, r0 /* save addr_sp */
|
||||||
|
mov r5, r1 /* save addr of gd */
|
||||||
|
mov r6, r2 /* save addr of destination */
|
||||||
|
mov r7, r2 /* save addr of destination */
|
||||||
|
|
||||||
|
/* Set up the stack */
|
||||||
|
stack_setup:
|
||||||
|
mov sp, r4
|
||||||
|
|
||||||
|
adr r0, _start
|
||||||
|
ldr r2, _TEXT_BASE
|
||||||
|
ldr r3, _bss_start
|
||||||
|
sub r2, r3, r2 /* r2 <- size of armboot */
|
||||||
|
add r2, r0, r2 /* r2 <- source end address */
|
||||||
|
cmp r0, r6
|
||||||
|
beq clear_bss
|
||||||
|
|
||||||
|
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
|
||||||
|
copy_loop:
|
||||||
|
ldmia r0!, {r9-r10} /* copy from source address [r0] */
|
||||||
|
stmia r6!, {r9-r10} /* copy to target address [r1] */
|
||||||
|
cmp r0, r2 /* until source end addreee [r2] */
|
||||||
|
ble copy_loop
|
||||||
|
|
||||||
|
#ifndef CONFIG_PRELOADER
|
||||||
|
/* fix got entries */
|
||||||
|
ldr r1, _TEXT_BASE /* Text base */
|
||||||
|
mov r0, r7 /* reloc addr */
|
||||||
|
ldr r2, _got_start /* addr in Flash */
|
||||||
|
ldr r3, _got_end /* addr in Flash */
|
||||||
|
sub r3, r3, r1
|
||||||
|
add r3, r3, r0
|
||||||
|
sub r2, r2, r1
|
||||||
|
add r2, r2, r0
|
||||||
|
|
||||||
|
fixloop:
|
||||||
|
ldr r4, [r2]
|
||||||
|
sub r4, r4, r1
|
||||||
|
add r4, r4, r0
|
||||||
|
str r4, [r2]
|
||||||
|
add r2, r2, #4
|
||||||
|
cmp r2, r3
|
||||||
|
bne fixloop
|
||||||
|
#endif
|
||||||
|
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
|
||||||
|
|
||||||
|
clear_bss:
|
||||||
|
#ifndef CONFIG_PRELOADER
|
||||||
|
ldr r0, _bss_start
|
||||||
|
ldr r1, _bss_end
|
||||||
|
ldr r3, _TEXT_BASE /* Text base */
|
||||||
|
mov r4, r7 /* reloc addr */
|
||||||
|
sub r0, r0, r3
|
||||||
|
add r0, r0, r4
|
||||||
|
sub r1, r1, r3
|
||||||
|
add r1, r1, r4
|
||||||
|
mov r2, #0x00000000 /* clear */
|
||||||
|
|
||||||
|
clbss_l:str r2, [r0] /* clear loop... */
|
||||||
|
add r0, r0, #4
|
||||||
|
cmp r0, r1
|
||||||
|
bne clbss_l
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We are done. Do not return, instead branch to second part of board
|
||||||
|
* initialization, now running from RAM.
|
||||||
|
*/
|
||||||
|
#ifdef CONFIG_ONENAND_IPL
|
||||||
|
ldr pc, _start_oneboot
|
||||||
|
|
||||||
|
_start_oneboot: .word start_oneboot
|
||||||
|
#else
|
||||||
|
ldr r0, _TEXT_BASE
|
||||||
|
ldr r2, _board_init_r
|
||||||
|
sub r2, r2, r0
|
||||||
|
add r2, r2, r7 /* position from board_init_r in RAM */
|
||||||
|
/* setup parameters for board_init_r */
|
||||||
|
mov r0, r5 /* gd_t */
|
||||||
|
mov r1, r7 /* dest_addr */
|
||||||
|
/* jump to it ... */
|
||||||
|
mov lr, r2
|
||||||
|
mov pc, lr
|
||||||
|
|
||||||
|
_board_init_r: .word board_init_r
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||||
|
|
||||||
/****************************************************************************/
|
/****************************************************************************/
|
||||||
/* */
|
/* */
|
||||||
@ -188,6 +347,7 @@ _start_armboot: .word start_oneboot
|
|||||||
#else
|
#else
|
||||||
_start_armboot: .word start_armboot
|
_start_armboot: .word start_armboot
|
||||||
#endif
|
#endif
|
||||||
|
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||||
|
|
||||||
/****************************************************************************/
|
/****************************************************************************/
|
||||||
/* */
|
/* */
|
||||||
@ -367,9 +527,13 @@ setspeed_done:
|
|||||||
stmia sp, {r0 - r12} /* Calling r0-r12 */
|
stmia sp, {r0 - r12} /* Calling r0-r12 */
|
||||||
add r8, sp, #S_PC
|
add r8, sp, #S_PC
|
||||||
|
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
ldr r2, _armboot_start
|
ldr r2, _armboot_start
|
||||||
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
||||||
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
|
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
|
||||||
|
#else
|
||||||
|
ldr r2, IRQ_STACK_START_IN
|
||||||
|
#endif
|
||||||
ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
|
ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
|
||||||
add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
|
add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
|
||||||
|
|
||||||
@ -404,9 +568,13 @@ setspeed_done:
|
|||||||
.endm
|
.endm
|
||||||
|
|
||||||
.macro get_bad_stack
|
.macro get_bad_stack
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
ldr r13, _armboot_start @ setup our mode stack
|
ldr r13, _armboot_start @ setup our mode stack
|
||||||
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
||||||
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
|
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
|
||||||
|
#else
|
||||||
|
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
|
||||||
|
#endif
|
||||||
|
|
||||||
str lr, [r13] @ save caller lr / spsr
|
str lr, [r13] @ save caller lr / spsr
|
||||||
mrs lr, spsr
|
mrs lr, spsr
|
||||||
|
@ -39,11 +39,23 @@ SECTIONS
|
|||||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||||
|
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
.data : { *(.data) }
|
.data : {
|
||||||
|
*(.data)
|
||||||
|
__datarel_start = .;
|
||||||
|
*(.data.rel)
|
||||||
|
__datarelrolocal_start = .;
|
||||||
|
*(.data.rel.ro.local)
|
||||||
|
__datarellocal_start = .;
|
||||||
|
*(.data.rel.local)
|
||||||
|
__datarelro_start = .;
|
||||||
|
*(.data.rel.ro)
|
||||||
|
}
|
||||||
|
|
||||||
|
__got_start = .;
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
.got : { *(.got) }
|
.got : { *(.got) }
|
||||||
|
|
||||||
|
__got_end = .;
|
||||||
. = .;
|
. = .;
|
||||||
__u_boot_cmd_start = .;
|
__u_boot_cmd_start = .;
|
||||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||||
|
@ -63,12 +63,15 @@ _start: b reset
|
|||||||
*************************************************************************
|
*************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
.globl _TEXT_BASE
|
||||||
_TEXT_BASE:
|
_TEXT_BASE:
|
||||||
.word TEXT_BASE
|
.word TEXT_BASE
|
||||||
|
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
.globl _armboot_start
|
.globl _armboot_start
|
||||||
_armboot_start:
|
_armboot_start:
|
||||||
.word _start
|
.word _start
|
||||||
|
#endif
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* These are defined in the board-specific linker script.
|
* These are defined in the board-specific linker script.
|
||||||
@ -93,7 +96,177 @@ FIQ_STACK_START:
|
|||||||
.word 0x0badc0de
|
.word 0x0badc0de
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
|
/* IRQ stack memory (calculated at run-time) + 8 bytes */
|
||||||
|
.globl IRQ_STACK_START_IN
|
||||||
|
IRQ_STACK_START_IN:
|
||||||
|
.word 0x0badc0de
|
||||||
|
|
||||||
|
.globl _datarel_start
|
||||||
|
_datarel_start:
|
||||||
|
.word __datarel_start
|
||||||
|
|
||||||
|
.globl _datarelrolocal_start
|
||||||
|
_datarelrolocal_start:
|
||||||
|
.word __datarelrolocal_start
|
||||||
|
|
||||||
|
.globl _datarellocal_start
|
||||||
|
_datarellocal_start:
|
||||||
|
.word __datarellocal_start
|
||||||
|
|
||||||
|
.globl _datarelro_start
|
||||||
|
_datarelro_start:
|
||||||
|
.word __datarelro_start
|
||||||
|
|
||||||
|
.globl _got_start
|
||||||
|
_got_start:
|
||||||
|
.word __got_start
|
||||||
|
|
||||||
|
.globl _got_end
|
||||||
|
_got_end:
|
||||||
|
.word __got_end
|
||||||
|
|
||||||
|
/*
|
||||||
|
* the actual reset code
|
||||||
|
*/
|
||||||
|
|
||||||
|
reset:
|
||||||
|
/*
|
||||||
|
* set the cpu to SVC32 mode
|
||||||
|
*/
|
||||||
|
mrs r0,cpsr
|
||||||
|
bic r0,r0,#0x1f
|
||||||
|
orr r0,r0,#0xd3
|
||||||
|
msr cpsr,r0
|
||||||
|
|
||||||
|
/*
|
||||||
|
* we do sys-critical inits only at reboot,
|
||||||
|
* not when booting from ram!
|
||||||
|
*/
|
||||||
|
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||||
|
bl cpu_init_crit
|
||||||
|
/*
|
||||||
|
* before relocating, we have to setup RAM timing
|
||||||
|
* because memory timing is board-dependend, you will
|
||||||
|
* find a lowlevel_init.S in your board directory.
|
||||||
|
*/
|
||||||
|
bl lowlevel_init
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Set stackpointer in internal RAM to call board_init_f */
|
||||||
|
call_board_init_f:
|
||||||
|
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
|
||||||
|
ldr r0,=0x00000000
|
||||||
|
bl board_init_f
|
||||||
|
|
||||||
|
/*------------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* void relocate_code (addr_sp, gd, addr_moni)
|
||||||
|
*
|
||||||
|
* This "function" does not return, instead it continues in RAM
|
||||||
|
* after relocating the monitor code.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
.globl relocate_code
|
||||||
|
relocate_code:
|
||||||
|
mov r4, r0 /* save addr_sp */
|
||||||
|
mov r5, r1 /* save addr of gd */
|
||||||
|
mov r6, r2 /* save addr of destination */
|
||||||
|
mov r7, r2 /* save addr of destination */
|
||||||
|
|
||||||
|
/* Set up the stack */
|
||||||
|
stack_setup:
|
||||||
|
mov sp, r4
|
||||||
|
|
||||||
|
adr r0, _start
|
||||||
|
ldr r2, _TEXT_BASE
|
||||||
|
ldr r3, _bss_start
|
||||||
|
sub r2, r3, r2 /* r2 <- size of armboot */
|
||||||
|
add r2, r0, r2 /* r2 <- source end address */
|
||||||
|
cmp r0, r6
|
||||||
|
beq clear_bss
|
||||||
|
|
||||||
|
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
|
||||||
|
copy_loop:
|
||||||
|
ldmia r0!, {r9-r10} /* copy from source address [r0] */
|
||||||
|
stmia r6!, {r9-r10} /* copy to target address [r1] */
|
||||||
|
cmp r0, r2 /* until source end addreee [r2] */
|
||||||
|
ble copy_loop
|
||||||
|
|
||||||
|
#ifndef CONFIG_PRELOADER
|
||||||
|
/* fix got entries */
|
||||||
|
ldr r1, _TEXT_BASE /* Text base */
|
||||||
|
mov r0, r7 /* reloc addr */
|
||||||
|
ldr r2, _got_start /* addr in Flash */
|
||||||
|
ldr r3, _got_end /* addr in Flash */
|
||||||
|
sub r3, r3, r1
|
||||||
|
add r3, r3, r0
|
||||||
|
sub r2, r2, r1
|
||||||
|
add r2, r2, r0
|
||||||
|
|
||||||
|
fixloop:
|
||||||
|
ldr r4, [r2]
|
||||||
|
sub r4, r4, r1
|
||||||
|
add r4, r4, r0
|
||||||
|
str r4, [r2]
|
||||||
|
add r2, r2, #4
|
||||||
|
cmp r2, r3
|
||||||
|
bne fixloop
|
||||||
|
#endif
|
||||||
|
/*
|
||||||
|
now copy to sram the interrupt vector
|
||||||
|
*/
|
||||||
|
adr r0, real_vectors
|
||||||
|
add r2, r0, #1024
|
||||||
|
ldr r1, =0x0c000000
|
||||||
|
add r1, r1, #0x08
|
||||||
|
vector_copy_loop:
|
||||||
|
ldmia r0!, {r3-r10}
|
||||||
|
stmia r1!, {r3-r10}
|
||||||
|
cmp r0, r2
|
||||||
|
ble vector_copy_loop
|
||||||
|
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
|
||||||
|
|
||||||
|
clear_bss:
|
||||||
|
#ifndef CONFIG_PRELOADER
|
||||||
|
ldr r0, _bss_start
|
||||||
|
ldr r1, _bss_end
|
||||||
|
ldr r3, _TEXT_BASE /* Text base */
|
||||||
|
mov r4, r7 /* reloc addr */
|
||||||
|
sub r0, r0, r3
|
||||||
|
add r0, r0, r4
|
||||||
|
sub r1, r1, r3
|
||||||
|
add r1, r1, r4
|
||||||
|
mov r2, #0x00000000 /* clear */
|
||||||
|
|
||||||
|
clbss_l:str r2, [r0] /* clear loop... */
|
||||||
|
add r0, r0, #4
|
||||||
|
cmp r0, r1
|
||||||
|
bne clbss_l
|
||||||
|
|
||||||
|
bl coloured_LED_init
|
||||||
|
bl red_LED_on
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We are done. Do not return, instead branch to second part of board
|
||||||
|
* initialization, now running from RAM.
|
||||||
|
*/
|
||||||
|
ldr r0, _TEXT_BASE
|
||||||
|
ldr r2, _board_init_r
|
||||||
|
sub r2, r2, r0
|
||||||
|
add r2, r2, r7 /* position from board_init_r in RAM */
|
||||||
|
/* setup parameters for board_init_r */
|
||||||
|
mov r0, r5 /* gd_t */
|
||||||
|
mov r1, r7 /* dest_addr */
|
||||||
|
/* jump to it ... */
|
||||||
|
mov lr, r2
|
||||||
|
mov pc, lr
|
||||||
|
|
||||||
|
_board_init_r: .word board_init_r
|
||||||
|
|
||||||
|
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||||
/*
|
/*
|
||||||
* the actual reset code
|
* the actual reset code
|
||||||
*/
|
*/
|
||||||
@ -169,6 +342,7 @@ stack_setup:
|
|||||||
|
|
||||||
_start_armboot: .word start_armboot
|
_start_armboot: .word start_armboot
|
||||||
|
|
||||||
|
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
*************************************************************************
|
*************************************************************************
|
||||||
|
@ -39,11 +39,23 @@ SECTIONS
|
|||||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||||
|
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
.data : { *(.data) }
|
.data : {
|
||||||
|
*(.data)
|
||||||
|
__datarel_start = .;
|
||||||
|
*(.data.rel)
|
||||||
|
__datarelrolocal_start = .;
|
||||||
|
*(.data.rel.ro.local)
|
||||||
|
__datarellocal_start = .;
|
||||||
|
*(.data.rel.local)
|
||||||
|
__datarelro_start = .;
|
||||||
|
*(.data.rel.ro)
|
||||||
|
}
|
||||||
|
|
||||||
|
__got_start = .;
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
.got : { *(.got) }
|
.got : { *(.got) }
|
||||||
|
|
||||||
|
__got_end = .;
|
||||||
. = .;
|
. = .;
|
||||||
__u_boot_cmd_start = .;
|
__u_boot_cmd_start = .;
|
||||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||||
|
@ -73,12 +73,15 @@ _fiq: .word fiq
|
|||||||
*************************************************************************
|
*************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
.globl _TEXT_BASE
|
||||||
_TEXT_BASE:
|
_TEXT_BASE:
|
||||||
.word TEXT_BASE
|
.word TEXT_BASE
|
||||||
|
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
.globl _armboot_start
|
.globl _armboot_start
|
||||||
_armboot_start:
|
_armboot_start:
|
||||||
.word _start
|
.word _start
|
||||||
|
#endif
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* These are defined in the board-specific linker script.
|
* These are defined in the board-specific linker script.
|
||||||
@ -103,6 +106,156 @@ FIQ_STACK_START:
|
|||||||
.word 0x0badc0de
|
.word 0x0badc0de
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
|
/* IRQ stack memory (calculated at run-time) + 8 bytes */
|
||||||
|
.globl IRQ_STACK_START_IN
|
||||||
|
IRQ_STACK_START_IN:
|
||||||
|
.word 0x0badc0de
|
||||||
|
|
||||||
|
.globl _datarel_start
|
||||||
|
_datarel_start:
|
||||||
|
.word __datarel_start
|
||||||
|
|
||||||
|
.globl _datarelrolocal_start
|
||||||
|
_datarelrolocal_start:
|
||||||
|
.word __datarelrolocal_start
|
||||||
|
|
||||||
|
.globl _datarellocal_start
|
||||||
|
_datarellocal_start:
|
||||||
|
.word __datarellocal_start
|
||||||
|
|
||||||
|
.globl _datarelro_start
|
||||||
|
_datarelro_start:
|
||||||
|
.word __datarelro_start
|
||||||
|
|
||||||
|
.globl _got_start
|
||||||
|
_got_start:
|
||||||
|
.word __got_start
|
||||||
|
|
||||||
|
.globl _got_end
|
||||||
|
_got_end:
|
||||||
|
.word __got_end
|
||||||
|
|
||||||
|
/*
|
||||||
|
* the actual reset code
|
||||||
|
*/
|
||||||
|
|
||||||
|
reset:
|
||||||
|
/*
|
||||||
|
* set the cpu to SVC32 mode
|
||||||
|
*/
|
||||||
|
mrs r0,cpsr
|
||||||
|
bic r0,r0,#0x1f
|
||||||
|
orr r0,r0,#0xd3
|
||||||
|
msr cpsr,r0
|
||||||
|
|
||||||
|
/*
|
||||||
|
* we do sys-critical inits only at reboot,
|
||||||
|
* not when booting from ram!
|
||||||
|
*/
|
||||||
|
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||||
|
bl cpu_init_crit
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Set stackpointer in internal RAM to call board_init_f */
|
||||||
|
call_board_init_f:
|
||||||
|
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
|
||||||
|
ldr r0,=0x00000000
|
||||||
|
bl board_init_f
|
||||||
|
|
||||||
|
/*------------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* void relocate_code (addr_sp, gd, addr_moni)
|
||||||
|
*
|
||||||
|
* This "function" does not return, instead it continues in RAM
|
||||||
|
* after relocating the monitor code.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
.globl relocate_code
|
||||||
|
relocate_code:
|
||||||
|
mov r4, r0 /* save addr_sp */
|
||||||
|
mov r5, r1 /* save addr of gd */
|
||||||
|
mov r6, r2 /* save addr of destination */
|
||||||
|
mov r7, r2 /* save addr of destination */
|
||||||
|
|
||||||
|
/* Set up the stack */
|
||||||
|
stack_setup:
|
||||||
|
mov sp, r4
|
||||||
|
|
||||||
|
adr r0, _start
|
||||||
|
ldr r2, _TEXT_BASE
|
||||||
|
ldr r3, _bss_start
|
||||||
|
sub r2, r3, r2 /* r2 <- size of armboot */
|
||||||
|
add r2, r0, r2 /* r2 <- source end address */
|
||||||
|
cmp r0, r6
|
||||||
|
beq clear_bss
|
||||||
|
|
||||||
|
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
|
||||||
|
copy_loop:
|
||||||
|
ldmia r0!, {r9-r10} /* copy from source address [r0] */
|
||||||
|
stmia r6!, {r9-r10} /* copy to target address [r1] */
|
||||||
|
cmp r0, r2 /* until source end addreee [r2] */
|
||||||
|
ble copy_loop
|
||||||
|
|
||||||
|
#ifndef CONFIG_PRELOADER
|
||||||
|
/* fix got entries */
|
||||||
|
ldr r1, _TEXT_BASE /* Text base */
|
||||||
|
mov r0, r7 /* reloc addr */
|
||||||
|
ldr r2, _got_start /* addr in Flash */
|
||||||
|
ldr r3, _got_end /* addr in Flash */
|
||||||
|
sub r3, r3, r1
|
||||||
|
add r3, r3, r0
|
||||||
|
sub r2, r2, r1
|
||||||
|
add r2, r2, r0
|
||||||
|
|
||||||
|
fixloop:
|
||||||
|
ldr r4, [r2]
|
||||||
|
sub r4, r4, r1
|
||||||
|
add r4, r4, r0
|
||||||
|
str r4, [r2]
|
||||||
|
add r2, r2, #4
|
||||||
|
cmp r2, r3
|
||||||
|
bne fixloop
|
||||||
|
#endif
|
||||||
|
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
|
||||||
|
|
||||||
|
clear_bss:
|
||||||
|
#ifndef CONFIG_PRELOADER
|
||||||
|
ldr r0, _bss_start
|
||||||
|
ldr r1, _bss_end
|
||||||
|
ldr r3, _TEXT_BASE /* Text base */
|
||||||
|
mov r4, r7 /* reloc addr */
|
||||||
|
sub r0, r0, r3
|
||||||
|
add r0, r0, r4
|
||||||
|
sub r1, r1, r3
|
||||||
|
add r1, r1, r4
|
||||||
|
mov r2, #0x00000000 /* clear */
|
||||||
|
|
||||||
|
clbss_l:str r2, [r0] /* clear loop... */
|
||||||
|
add r0, r0, #4
|
||||||
|
cmp r0, r1
|
||||||
|
bne clbss_l
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We are done. Do not return, instead branch to second part of board
|
||||||
|
* initialization, now running from RAM.
|
||||||
|
*/
|
||||||
|
ldr r0, _TEXT_BASE
|
||||||
|
ldr r2, _board_init_r
|
||||||
|
sub r2, r2, r0
|
||||||
|
add r2, r2, r7 /* position from board_init_r in RAM */
|
||||||
|
/* setup parameters for board_init_r */
|
||||||
|
mov r0, r5 /* gd_t */
|
||||||
|
mov r1, r7 /* dest_addr */
|
||||||
|
/* jump to it ... */
|
||||||
|
mov lr, r2
|
||||||
|
mov pc, lr
|
||||||
|
|
||||||
|
_board_init_r: .word board_init_r
|
||||||
|
|
||||||
|
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* the actual reset code
|
* the actual reset code
|
||||||
@ -169,6 +322,7 @@ clbss_l:str r2, [r0] /* clear loop... */
|
|||||||
|
|
||||||
_start_armboot: .word start_armboot
|
_start_armboot: .word start_armboot
|
||||||
|
|
||||||
|
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
*************************************************************************
|
*************************************************************************
|
||||||
@ -288,9 +442,13 @@ cpu_init_crit:
|
|||||||
stmia sp, {r0 - r12} @ Calling r0-r12
|
stmia sp, {r0 - r12} @ Calling r0-r12
|
||||||
add r8, sp, #S_PC
|
add r8, sp, #S_PC
|
||||||
|
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
ldr r2, _armboot_start
|
ldr r2, _armboot_start
|
||||||
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
||||||
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
|
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
|
||||||
|
#else
|
||||||
|
ldr r2, IRQ_STACK_START_IN
|
||||||
|
#endif
|
||||||
ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
|
ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
|
||||||
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
|
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
|
||||||
|
|
||||||
@ -321,9 +479,13 @@ cpu_init_crit:
|
|||||||
.endm
|
.endm
|
||||||
|
|
||||||
.macro get_bad_stack
|
.macro get_bad_stack
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
ldr r13, _armboot_start @ setup our mode stack
|
ldr r13, _armboot_start @ setup our mode stack
|
||||||
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
||||||
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
|
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
|
||||||
|
#else
|
||||||
|
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
|
||||||
|
#endif
|
||||||
|
|
||||||
str lr, [r13] @ save caller lr / spsr
|
str lr, [r13] @ save caller lr / spsr
|
||||||
mrs lr, spsr
|
mrs lr, spsr
|
||||||
|
@ -42,11 +42,23 @@ SECTIONS
|
|||||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||||
|
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
.data : { *(.data) }
|
.data : {
|
||||||
|
*(.data)
|
||||||
|
__datarel_start = .;
|
||||||
|
*(.data.rel)
|
||||||
|
__datarelrolocal_start = .;
|
||||||
|
*(.data.rel.ro.local)
|
||||||
|
__datarellocal_start = .;
|
||||||
|
*(.data.rel.local)
|
||||||
|
__datarelro_start = .;
|
||||||
|
*(.data.rel.ro)
|
||||||
|
}
|
||||||
|
|
||||||
|
__got_start = .;
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
.got : { *(.got) }
|
.got : { *(.got) }
|
||||||
|
|
||||||
|
__got_end = .;
|
||||||
. = .;
|
. = .;
|
||||||
__u_boot_cmd_start = .;
|
__u_boot_cmd_start = .;
|
||||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||||
|
@ -21,7 +21,8 @@
|
|||||||
#ifndef _ASM_CONFIG_H_
|
#ifndef _ASM_CONFIG_H_
|
||||||
#define _ASM_CONFIG_H_
|
#define _ASM_CONFIG_H_
|
||||||
|
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
/* Relocation to SDRAM works on all ARM boards */
|
/* Relocation to SDRAM works on all ARM boards */
|
||||||
#define CONFIG_RELOC_FIXUP_WORKS
|
#define CONFIG_RELOC_FIXUP_WORKS
|
||||||
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
* (C) Copyright 2002
|
* (C) Copyright 2002-2010
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
*
|
*
|
||||||
* See file CREDITS for list of people who contributed to this
|
* See file CREDITS for list of people who contributed to this
|
||||||
@ -47,13 +47,19 @@ typedef struct global_data {
|
|||||||
#ifdef CONFIG_FSL_ESDHC
|
#ifdef CONFIG_FSL_ESDHC
|
||||||
unsigned long sdhc_clk;
|
unsigned long sdhc_clk;
|
||||||
#endif
|
#endif
|
||||||
#if 0
|
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
unsigned long cpu_clk; /* CPU clock in Hz! */
|
unsigned long relocaddr; /* Start address of U-Boot in RAM */
|
||||||
unsigned long bus_clk;
|
|
||||||
phys_size_t ram_size; /* RAM size */
|
phys_size_t ram_size; /* RAM size */
|
||||||
unsigned long reset_status; /* reset status register at boot */
|
unsigned long mon_len; /* monitor len */
|
||||||
|
unsigned long irq_sp; /* irq stack pointer */
|
||||||
|
unsigned long start_addr_sp; /* start_addr_stackpointer */
|
||||||
|
unsigned long reloc_off;
|
||||||
|
#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE))
|
||||||
|
unsigned long tlb_addr;
|
||||||
|
#endif
|
||||||
#endif
|
#endif
|
||||||
void **jt; /* jump table */
|
void **jt; /* jump table */
|
||||||
|
char env_buf[32]; /* buffer for getenv() before reloc. */
|
||||||
} gd_t;
|
} gd_t;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -66,6 +72,7 @@ typedef struct global_data {
|
|||||||
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
|
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
|
||||||
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
|
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
|
||||||
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
|
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
|
||||||
|
#define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */
|
||||||
|
|
||||||
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r8")
|
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r8")
|
||||||
|
|
||||||
|
@ -30,11 +30,20 @@
|
|||||||
#define _U_BOOT_ARM_H_ 1
|
#define _U_BOOT_ARM_H_ 1
|
||||||
|
|
||||||
/* for the following variables, see start.S */
|
/* for the following variables, see start.S */
|
||||||
extern ulong _armboot_start; /* code start */
|
|
||||||
extern ulong _bss_start; /* code + data end == BSS start */
|
extern ulong _bss_start; /* code + data end == BSS start */
|
||||||
extern ulong _bss_end; /* BSS end */
|
extern ulong _bss_end; /* BSS end */
|
||||||
extern ulong IRQ_STACK_START; /* top of IRQ stack */
|
extern ulong IRQ_STACK_START; /* top of IRQ stack */
|
||||||
extern ulong FIQ_STACK_START; /* top of FIQ stack */
|
extern ulong FIQ_STACK_START; /* top of FIQ stack */
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
|
extern ulong _armboot_start; /* code start */
|
||||||
|
#else
|
||||||
|
extern ulong _TEXT_BASE; /* code start */
|
||||||
|
extern ulong _datarel_start;
|
||||||
|
extern ulong _datarelrolocal_start;
|
||||||
|
extern ulong _datarellocal_start;
|
||||||
|
extern ulong _datarelro_start;
|
||||||
|
extern ulong IRQ_STACK_START_IN; /* 8 bytes in IRQ stack */
|
||||||
|
#endif
|
||||||
|
|
||||||
/* cpu/.../cpu.c */
|
/* cpu/.../cpu.c */
|
||||||
int cpu_init(void);
|
int cpu_init(void);
|
||||||
@ -47,6 +56,9 @@ int arch_misc_init(void);
|
|||||||
/* board/.../... */
|
/* board/.../... */
|
||||||
int board_init(void);
|
int board_init(void);
|
||||||
int dram_init (void);
|
int dram_init (void);
|
||||||
|
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
|
void dram_init_banksize (void);
|
||||||
|
#endif
|
||||||
void setup_serial_tag (struct tag **params);
|
void setup_serial_tag (struct tag **params);
|
||||||
void setup_revision_tag (struct tag **params);
|
void setup_revision_tag (struct tag **params);
|
||||||
|
|
||||||
|
@ -39,7 +39,6 @@
|
|||||||
typedef struct bd_info {
|
typedef struct bd_info {
|
||||||
int bi_baudrate; /* serial console baudrate */
|
int bi_baudrate; /* serial console baudrate */
|
||||||
unsigned long bi_ip_addr; /* IP Address */
|
unsigned long bi_ip_addr; /* IP Address */
|
||||||
struct environment_s *bi_env;
|
|
||||||
ulong bi_arch_number; /* unique id for this board */
|
ulong bi_arch_number; /* unique id for this board */
|
||||||
ulong bi_boot_params; /* where this board expects params */
|
ulong bi_boot_params; /* where this board expects params */
|
||||||
struct /* RAM configuration */
|
struct /* RAM configuration */
|
||||||
@ -49,7 +48,4 @@ typedef struct bd_info {
|
|||||||
} bi_dram[CONFIG_NR_DRAM_BANKS];
|
} bi_dram[CONFIG_NR_DRAM_BANKS];
|
||||||
} bd_t;
|
} bd_t;
|
||||||
|
|
||||||
#define bi_env_data bi_env->data
|
|
||||||
#define bi_env_crc bi_env->crc
|
|
||||||
|
|
||||||
#endif /* _U_BOOT_H_ */
|
#endif /* _U_BOOT_H_ */
|
||||||
|
@ -126,7 +126,12 @@ static int init_baudrate (void)
|
|||||||
{
|
{
|
||||||
char tmp[64]; /* long enough for environment variables */
|
char tmp[64]; /* long enough for environment variables */
|
||||||
int i = getenv_f("baudrate", tmp, sizeof (tmp));
|
int i = getenv_f("baudrate", tmp, sizeof (tmp));
|
||||||
|
|
||||||
|
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
|
gd->baudrate = (i > 0)
|
||||||
|
#else
|
||||||
gd->bd->bi_baudrate = gd->baudrate = (i > 0)
|
gd->bd->bi_baudrate = gd->baudrate = (i > 0)
|
||||||
|
#endif
|
||||||
? (int) simple_strtoul (tmp, NULL, 10)
|
? (int) simple_strtoul (tmp, NULL, 10)
|
||||||
: CONFIG_BAUDRATE;
|
: CONFIG_BAUDRATE;
|
||||||
|
|
||||||
@ -137,7 +142,12 @@ static int display_banner (void)
|
|||||||
{
|
{
|
||||||
printf ("\n\n%s\n\n", version_string);
|
printf ("\n\n%s\n\n", version_string);
|
||||||
debug ("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
|
debug ("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
|
||||||
_armboot_start, _bss_start, _bss_end);
|
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
|
_TEXT_BASE,
|
||||||
|
#else
|
||||||
|
_armboot_start,
|
||||||
|
#endif
|
||||||
|
_bss_start, _bss_end);
|
||||||
#ifdef CONFIG_MODEM_SUPPORT
|
#ifdef CONFIG_MODEM_SUPPORT
|
||||||
debug ("Modem Support enabled\n");
|
debug ("Modem Support enabled\n");
|
||||||
#endif
|
#endif
|
||||||
@ -180,6 +190,7 @@ static int display_dram_config (void)
|
|||||||
return (0);
|
return (0);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
#ifndef CONFIG_SYS_NO_FLASH
|
#ifndef CONFIG_SYS_NO_FLASH
|
||||||
static void display_flash_config (ulong size)
|
static void display_flash_config (ulong size)
|
||||||
{
|
{
|
||||||
@ -187,6 +198,7 @@ static void display_flash_config (ulong size)
|
|||||||
print_size (size, "\n");
|
print_size (size, "\n");
|
||||||
}
|
}
|
||||||
#endif /* CONFIG_SYS_NO_FLASH */
|
#endif /* CONFIG_SYS_NO_FLASH */
|
||||||
|
#endif
|
||||||
|
|
||||||
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
|
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
|
||||||
static int init_func_i2c (void)
|
static int init_func_i2c (void)
|
||||||
@ -234,6 +246,7 @@ typedef int (init_fnc_t) (void);
|
|||||||
|
|
||||||
int print_cpuinfo (void);
|
int print_cpuinfo (void);
|
||||||
|
|
||||||
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
init_fnc_t *init_sequence[] = {
|
init_fnc_t *init_sequence[] = {
|
||||||
#if defined(CONFIG_ARCH_CPU_INIT)
|
#if defined(CONFIG_ARCH_CPU_INIT)
|
||||||
arch_cpu_init, /* basic arch cpu dependent setup */
|
arch_cpu_init, /* basic arch cpu dependent setup */
|
||||||
@ -449,6 +462,459 @@ extern void davinci_eth_set_mac_addr (const u_int8_t *addr);
|
|||||||
|
|
||||||
/* NOTREACHED - no way out of command loop except booting */
|
/* NOTREACHED - no way out of command loop except booting */
|
||||||
}
|
}
|
||||||
|
#else
|
||||||
|
void __dram_init_banksize(void)
|
||||||
|
{
|
||||||
|
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
|
||||||
|
gd->bd->bi_dram[0].size = gd->ram_size;
|
||||||
|
}
|
||||||
|
void dram_init_banksize(void)
|
||||||
|
__attribute__((weak, alias("__dram_init_banksize")));
|
||||||
|
|
||||||
|
init_fnc_t *init_sequence[] = {
|
||||||
|
#if defined(CONFIG_ARCH_CPU_INIT)
|
||||||
|
arch_cpu_init, /* basic arch cpu dependent setup */
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_BOARD_EARLY_INIT_F)
|
||||||
|
board_early_init_f,
|
||||||
|
#endif
|
||||||
|
timer_init, /* initialize timer */
|
||||||
|
#ifdef CONFIG_FSL_ESDHC
|
||||||
|
get_clocks,
|
||||||
|
#endif
|
||||||
|
env_init, /* initialize environment */
|
||||||
|
init_baudrate, /* initialze baudrate settings */
|
||||||
|
serial_init, /* serial communications setup */
|
||||||
|
console_init_f, /* stage 1 init of console */
|
||||||
|
display_banner, /* say that we are here */
|
||||||
|
#if defined(CONFIG_DISPLAY_CPUINFO)
|
||||||
|
print_cpuinfo, /* display cpu info (and speed) */
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_DISPLAY_BOARDINFO)
|
||||||
|
checkboard, /* display board info */
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
|
||||||
|
init_func_i2c,
|
||||||
|
#endif
|
||||||
|
dram_init, /* configure available RAM banks */
|
||||||
|
#if defined(CONFIG_CMD_PCI) || defined (CONFIG_PCI)
|
||||||
|
arm_pci_init,
|
||||||
|
#endif
|
||||||
|
NULL,
|
||||||
|
};
|
||||||
|
|
||||||
|
void board_init_f (ulong bootflag)
|
||||||
|
{
|
||||||
|
bd_t *bd;
|
||||||
|
init_fnc_t **init_fnc_ptr;
|
||||||
|
gd_t *id;
|
||||||
|
ulong addr, addr_sp;
|
||||||
|
|
||||||
|
/* Pointer is writable since we allocated a register for it */
|
||||||
|
gd = (gd_t *) (CONFIG_SYS_INIT_SP_ADDR);
|
||||||
|
/* compiler optimization barrier needed for GCC >= 3.4 */
|
||||||
|
__asm__ __volatile__("": : :"memory");
|
||||||
|
|
||||||
|
memset ((void*)gd, 0, sizeof (gd_t));
|
||||||
|
|
||||||
|
gd->mon_len = _bss_end - _TEXT_BASE;
|
||||||
|
|
||||||
|
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
|
||||||
|
if ((*init_fnc_ptr)() != 0) {
|
||||||
|
hang ();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
debug ("monitor len: %08lX\n", gd->mon_len);
|
||||||
|
/*
|
||||||
|
* Ram is setup, size stored in gd !!
|
||||||
|
*/
|
||||||
|
debug ("ramsize: %08lX\n", gd->ram_size);
|
||||||
|
#if defined(CONFIG_SYS_MEM_TOP_HIDE)
|
||||||
|
/*
|
||||||
|
* Subtract specified amount of memory to hide so that it won't
|
||||||
|
* get "touched" at all by U-Boot. By fixing up gd->ram_size
|
||||||
|
* the Linux kernel should now get passed the now "corrected"
|
||||||
|
* memory size and won't touch it either. This should work
|
||||||
|
* for arch/ppc and arch/powerpc. Only Linux board ports in
|
||||||
|
* arch/powerpc with bootwrapper support, that recalculate the
|
||||||
|
* memory size from the SDRAM controller setup will have to
|
||||||
|
* get fixed.
|
||||||
|
*/
|
||||||
|
gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
|
||||||
|
|
||||||
|
#ifdef CONFIG_LOGBUFFER
|
||||||
|
#ifndef CONFIG_ALT_LB_ADDR
|
||||||
|
/* reserve kernel log buffer */
|
||||||
|
addr -= (LOGBUFF_RESERVE);
|
||||||
|
debug ("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, addr);
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_PRAM
|
||||||
|
/*
|
||||||
|
* reserve protected RAM
|
||||||
|
*/
|
||||||
|
i = getenv_r ("pram", (char *)tmp, sizeof (tmp));
|
||||||
|
reg = (i > 0) ? simple_strtoul ((const char *)tmp, NULL, 10) : CONFIG_PRAM;
|
||||||
|
addr -= (reg << 10); /* size is in kB */
|
||||||
|
debug ("Reserving %ldk for protected RAM at %08lx\n", reg, addr);
|
||||||
|
#endif /* CONFIG_PRAM */
|
||||||
|
|
||||||
|
#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE))
|
||||||
|
/* reserve TLB table */
|
||||||
|
addr -= (4096 * 4);
|
||||||
|
|
||||||
|
/* round down to next 64 kB limit */
|
||||||
|
addr &= ~(0x10000 - 1);
|
||||||
|
|
||||||
|
gd->tlb_addr = addr;
|
||||||
|
debug ("TLB table at: %08lx\n", addr);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* round down to next 4 kB limit */
|
||||||
|
addr &= ~(4096 - 1);
|
||||||
|
debug ("Top of RAM usable for U-Boot at: %08lx\n", addr);
|
||||||
|
|
||||||
|
#ifdef CONFIG_VFD
|
||||||
|
# ifndef PAGE_SIZE
|
||||||
|
# define PAGE_SIZE 4096
|
||||||
|
# endif
|
||||||
|
/*
|
||||||
|
* reserve memory for VFD display (always full pages)
|
||||||
|
*/
|
||||||
|
addr -= vfd_setmem (addr);
|
||||||
|
gd->fb_base = addr;
|
||||||
|
#endif /* CONFIG_VFD */
|
||||||
|
|
||||||
|
#ifdef CONFIG_LCD
|
||||||
|
/* reserve memory for LCD display (always full pages) */
|
||||||
|
addr = lcd_setmem (addr);
|
||||||
|
gd->fb_base = addr;
|
||||||
|
#endif /* CONFIG_LCD */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* reserve memory for U-Boot code, data & bss
|
||||||
|
* round down to next 4 kB limit
|
||||||
|
*/
|
||||||
|
addr -= gd->mon_len;
|
||||||
|
addr &= ~(4096 - 1);
|
||||||
|
|
||||||
|
debug ("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, addr);
|
||||||
|
|
||||||
|
#ifndef CONFIG_PRELOADER
|
||||||
|
/*
|
||||||
|
* reserve memory for malloc() arena
|
||||||
|
*/
|
||||||
|
addr_sp = addr - TOTAL_MALLOC_LEN;
|
||||||
|
debug ("Reserving %dk for malloc() at: %08lx\n",
|
||||||
|
TOTAL_MALLOC_LEN >> 10, addr_sp);
|
||||||
|
/*
|
||||||
|
* (permanently) allocate a Board Info struct
|
||||||
|
* and a permanent copy of the "global" data
|
||||||
|
*/
|
||||||
|
addr_sp -= sizeof (bd_t);
|
||||||
|
bd = (bd_t *) addr_sp;
|
||||||
|
gd->bd = bd;
|
||||||
|
debug ("Reserving %zu Bytes for Board Info at: %08lx\n",
|
||||||
|
sizeof (bd_t), addr_sp);
|
||||||
|
addr_sp -= sizeof (gd_t);
|
||||||
|
id = (gd_t *) addr_sp;
|
||||||
|
debug ("Reserving %zu Bytes for Global Data at: %08lx\n",
|
||||||
|
sizeof (gd_t), addr_sp);
|
||||||
|
|
||||||
|
/* setup stackpointer for exeptions */
|
||||||
|
gd->irq_sp = addr_sp;
|
||||||
|
#ifdef CONFIG_USE_IRQ
|
||||||
|
addr_sp -= (CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ);
|
||||||
|
debug ("Reserving %zu Bytes for IRQ stack at: %08lx\n",
|
||||||
|
CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ, addr_sp);
|
||||||
|
#endif
|
||||||
|
/* leave 3 words for abort-stack */
|
||||||
|
addr_sp -= 3;
|
||||||
|
|
||||||
|
/* 8-byte alignment for ABI compliance */
|
||||||
|
addr_sp &= ~0x07;
|
||||||
|
#else
|
||||||
|
addr_sp += 128; /* leave 32 words for abort-stack */
|
||||||
|
gd->irq_sp = addr_sp;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
debug ("New Stack Pointer is: %08lx\n", addr_sp);
|
||||||
|
|
||||||
|
#ifdef CONFIG_POST
|
||||||
|
post_bootmode_init();
|
||||||
|
post_run (NULL, POST_ROM | post_bootmode_get(0));
|
||||||
|
#endif
|
||||||
|
|
||||||
|
gd->bd->bi_baudrate = gd->baudrate;
|
||||||
|
/* Ram ist board specific, so move it to board code ... */
|
||||||
|
dram_init_banksize();
|
||||||
|
display_dram_config(); /* and display it */
|
||||||
|
|
||||||
|
gd->relocaddr = addr;
|
||||||
|
gd->start_addr_sp = addr_sp;
|
||||||
|
gd->reloc_off = addr - _TEXT_BASE;
|
||||||
|
debug ("relocation Offset is: %08lx\n", gd->reloc_off);
|
||||||
|
memcpy (id, (void *)gd, sizeof (gd_t));
|
||||||
|
|
||||||
|
relocate_code (addr_sp, id, addr);
|
||||||
|
|
||||||
|
/* NOTREACHED - relocate_code() does not return */
|
||||||
|
}
|
||||||
|
|
||||||
|
#if !defined(CONFIG_SYS_NO_FLASH)
|
||||||
|
static char *failed = "*** failed ***\n";
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/************************************************************************
|
||||||
|
*
|
||||||
|
* This is the next part if the initialization sequence: we are now
|
||||||
|
* running from RAM and have a "normal" C environment, i. e. global
|
||||||
|
* data can be written, BSS has been cleared, the stack size in not
|
||||||
|
* that critical any more, etc.
|
||||||
|
*
|
||||||
|
************************************************************************
|
||||||
|
*/
|
||||||
|
void board_init_r (gd_t *id, ulong dest_addr)
|
||||||
|
{
|
||||||
|
char *s;
|
||||||
|
bd_t *bd;
|
||||||
|
ulong malloc_start;
|
||||||
|
#if !defined(CONFIG_SYS_NO_FLASH)
|
||||||
|
ulong flash_size;
|
||||||
|
#endif
|
||||||
|
#if !defined(CONFIG_RELOC_FIXUP_WORKS)
|
||||||
|
extern void malloc_bin_reloc (void);
|
||||||
|
#if defined(CONFIG_CMD_BMP)
|
||||||
|
extern void bmp_reloc(void);
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_CMD_I2C)
|
||||||
|
extern void i2c_reloc(void);
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
gd = id;
|
||||||
|
bd = gd->bd;
|
||||||
|
|
||||||
|
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
|
||||||
|
|
||||||
|
monitor_flash_len = _bss_start - _TEXT_BASE;
|
||||||
|
debug ("monitor flash len: %08lX\n", monitor_flash_len);
|
||||||
|
board_init(); /* Setup chipselects */
|
||||||
|
|
||||||
|
#ifdef CONFIG_SERIAL_MULTI
|
||||||
|
serial_initialize();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
|
||||||
|
|
||||||
|
#if !defined(CONFIG_RELOC_FIXUP_WORKS)
|
||||||
|
/*
|
||||||
|
* We have to relocate the command table manually
|
||||||
|
*/
|
||||||
|
fixup_cmdtable(&__u_boot_cmd_start,
|
||||||
|
(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
|
||||||
|
#if defined(CONFIG_CMD_BMP)
|
||||||
|
bmp_reloc();
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_CMD_I2C)
|
||||||
|
i2c_reloc();
|
||||||
|
#endif
|
||||||
|
#endif /* !defined(CONFIG_RELOC_FIXUP_WORKS) */
|
||||||
|
|
||||||
|
#ifdef CONFIG_LOGBUFFER
|
||||||
|
logbuff_init_ptrs ();
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_POST
|
||||||
|
post_output_backlog ();
|
||||||
|
#ifndef CONFIG_RELOC_FIXUP_WORKS
|
||||||
|
post_reloc ();
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* The Malloc area is immediately below the monitor copy in DRAM */
|
||||||
|
malloc_start = dest_addr - TOTAL_MALLOC_LEN;
|
||||||
|
mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN);
|
||||||
|
#if !defined(CONFIG_RELOC_FIXUP_WORKS)
|
||||||
|
malloc_bin_reloc ();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if !defined(CONFIG_SYS_NO_FLASH)
|
||||||
|
puts ("FLASH: ");
|
||||||
|
|
||||||
|
if ((flash_size = flash_init ()) > 0) {
|
||||||
|
# ifdef CONFIG_SYS_FLASH_CHECKSUM
|
||||||
|
print_size (flash_size, "");
|
||||||
|
/*
|
||||||
|
* Compute and print flash CRC if flashchecksum is set to 'y'
|
||||||
|
*
|
||||||
|
* NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
|
||||||
|
*/
|
||||||
|
s = getenv ("flashchecksum");
|
||||||
|
if (s && (*s == 'y')) {
|
||||||
|
printf (" CRC: %08X",
|
||||||
|
crc32 (0, (const unsigned char *) CONFIG_SYS_FLASH_BASE, flash_size)
|
||||||
|
);
|
||||||
|
}
|
||||||
|
putc ('\n');
|
||||||
|
# else /* !CONFIG_SYS_FLASH_CHECKSUM */
|
||||||
|
print_size (flash_size, "\n");
|
||||||
|
# endif /* CONFIG_SYS_FLASH_CHECKSUM */
|
||||||
|
} else {
|
||||||
|
puts (failed);
|
||||||
|
hang ();
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_CMD_NAND)
|
||||||
|
puts ("NAND: ");
|
||||||
|
nand_init(); /* go init the NAND */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_CMD_ONENAND)
|
||||||
|
onenand_init();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_HAS_DATAFLASH
|
||||||
|
AT91F_DataflashInit();
|
||||||
|
dataflash_print_info();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* initialize environment */
|
||||||
|
env_relocate ();
|
||||||
|
|
||||||
|
#ifdef CONFIG_VFD
|
||||||
|
/* must do this after the framebuffer is allocated */
|
||||||
|
drv_vfd_init();
|
||||||
|
#endif /* CONFIG_VFD */
|
||||||
|
|
||||||
|
/* IP Address */
|
||||||
|
gd->bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
|
||||||
|
|
||||||
|
stdio_init (); /* get the devices list going. */
|
||||||
|
|
||||||
|
jumptable_init ();
|
||||||
|
|
||||||
|
#if defined(CONFIG_API)
|
||||||
|
/* Initialize API */
|
||||||
|
api_init ();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
console_init_r (); /* fully init console as a device */
|
||||||
|
|
||||||
|
#if defined(CONFIG_ARCH_MISC_INIT)
|
||||||
|
/* miscellaneous arch dependent initialisations */
|
||||||
|
arch_misc_init ();
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_MISC_INIT_R)
|
||||||
|
/* miscellaneous platform dependent initialisations */
|
||||||
|
misc_init_r ();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* set up exceptions */
|
||||||
|
interrupt_init ();
|
||||||
|
/* enable exceptions */
|
||||||
|
enable_interrupts ();
|
||||||
|
|
||||||
|
/* Perform network card initialisation if necessary */
|
||||||
|
#ifdef CONFIG_DRIVER_TI_EMAC
|
||||||
|
/* XXX: this needs to be moved to board init */
|
||||||
|
extern void davinci_eth_set_mac_addr (const u_int8_t *addr);
|
||||||
|
if (getenv ("ethaddr")) {
|
||||||
|
uchar enetaddr[6];
|
||||||
|
eth_getenv_enetaddr("ethaddr", enetaddr);
|
||||||
|
davinci_eth_set_mac_addr(enetaddr);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96)
|
||||||
|
/* XXX: this needs to be moved to board init */
|
||||||
|
if (getenv ("ethaddr")) {
|
||||||
|
uchar enetaddr[6];
|
||||||
|
eth_getenv_enetaddr("ethaddr", enetaddr);
|
||||||
|
smc_set_mac_addr(enetaddr);
|
||||||
|
}
|
||||||
|
#endif /* CONFIG_DRIVER_SMC91111 || CONFIG_DRIVER_LAN91C96 */
|
||||||
|
|
||||||
|
/* Initialize from environment */
|
||||||
|
if ((s = getenv ("loadaddr")) != NULL) {
|
||||||
|
load_addr = simple_strtoul (s, NULL, 16);
|
||||||
|
}
|
||||||
|
#if defined(CONFIG_CMD_NET)
|
||||||
|
if ((s = getenv ("bootfile")) != NULL) {
|
||||||
|
copy_filename (BootFile, s, sizeof (BootFile));
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef BOARD_LATE_INIT
|
||||||
|
board_late_init ();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_GENERIC_MMC
|
||||||
|
puts ("MMC: ");
|
||||||
|
mmc_initialize (gd->bd);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_BITBANGMII
|
||||||
|
bb_miiphy_init();
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_CMD_NET)
|
||||||
|
#if defined(CONFIG_NET_MULTI)
|
||||||
|
puts ("Net: ");
|
||||||
|
#endif
|
||||||
|
eth_initialize(gd->bd);
|
||||||
|
#if defined(CONFIG_RESET_PHY_R)
|
||||||
|
debug ("Reset Ethernet PHY\n");
|
||||||
|
reset_phy();
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_POST
|
||||||
|
post_run (NULL, POST_RAM | post_bootmode_get(0));
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
|
||||||
|
/*
|
||||||
|
* Export available size of memory for Linux,
|
||||||
|
* taking into account the protected RAM at top of memory
|
||||||
|
*/
|
||||||
|
{
|
||||||
|
ulong pram;
|
||||||
|
uchar memsz[32];
|
||||||
|
#ifdef CONFIG_PRAM
|
||||||
|
char *s;
|
||||||
|
|
||||||
|
if ((s = getenv ("pram")) != NULL) {
|
||||||
|
pram = simple_strtoul (s, NULL, 10);
|
||||||
|
} else {
|
||||||
|
pram = CONFIG_PRAM;
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
pram=0;
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_LOGBUFFER
|
||||||
|
#ifndef CONFIG_ALT_LB_ADDR
|
||||||
|
/* Also take the logbuffer into account (pram is in kB) */
|
||||||
|
pram += (LOGBUFF_LEN+LOGBUFF_OVERHEAD)/1024;
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
sprintf ((char *)memsz, "%ldk", (bd->bi_memsize / 1024) - pram);
|
||||||
|
setenv ("mem", (char *)memsz);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* main_loop() can return to retry autoboot, if so just run it again. */
|
||||||
|
for (;;) {
|
||||||
|
main_loop ();
|
||||||
|
}
|
||||||
|
|
||||||
|
/* NOTREACHED - no way out of command loop except booting */
|
||||||
|
}
|
||||||
|
#endif /* defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
||||||
|
|
||||||
void hang (void)
|
void hang (void)
|
||||||
{
|
{
|
||||||
|
@ -25,6 +25,15 @@
|
|||||||
#include <asm/system.h>
|
#include <asm/system.h>
|
||||||
|
|
||||||
#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE))
|
#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE))
|
||||||
|
|
||||||
|
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
|
||||||
|
#define CACHE_SETUP 0x1a
|
||||||
|
#else
|
||||||
|
#define CACHE_SETUP 0x1e
|
||||||
|
#endif
|
||||||
|
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
static void cp_delay (void)
|
static void cp_delay (void)
|
||||||
{
|
{
|
||||||
volatile int i;
|
volatile int i;
|
||||||
@ -32,6 +41,67 @@ static void cp_delay (void)
|
|||||||
/* copro seems to need some delay between reading and writing */
|
/* copro seems to need some delay between reading and writing */
|
||||||
for (i = 0; i < 100; i++)
|
for (i = 0; i < 100; i++)
|
||||||
nop();
|
nop();
|
||||||
|
asm volatile("" : : : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
|
static inline void dram_bank_mmu_setup(int bank)
|
||||||
|
{
|
||||||
|
u32 *page_table = (u32 *)gd->tlb_addr;
|
||||||
|
bd_t *bd = gd->bd;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
debug("%s: bank: %d\n", __func__, bank);
|
||||||
|
for (i = bd->bi_dram[bank].start >> 20;
|
||||||
|
i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
|
||||||
|
i++) {
|
||||||
|
page_table[i] = i << 20 | (3 << 10) | CACHE_SETUP;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* to activate the MMU we need to set up virtual memory: use 1M areas */
|
||||||
|
static inline void mmu_setup(void)
|
||||||
|
{
|
||||||
|
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
|
u32 *page_table = (u32 *)gd->tlb_addr;
|
||||||
|
#else
|
||||||
|
static u32 __attribute__((aligned(16384))) page_table[4096];
|
||||||
|
bd_t *bd = gd->bd;
|
||||||
|
int j;
|
||||||
|
#endif
|
||||||
|
int i;
|
||||||
|
u32 reg;
|
||||||
|
|
||||||
|
/* Set up an identity-mapping for all 4GB, rw for everyone */
|
||||||
|
for (i = 0; i < 4096; i++)
|
||||||
|
page_table[i] = i << 20 | (3 << 10) | 0x12;
|
||||||
|
|
||||||
|
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
|
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
|
||||||
|
dram_bank_mmu_setup(i);
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
/* Then, enable cacheable and bufferable for RAM only */
|
||||||
|
for (j = 0; j < CONFIG_NR_DRAM_BANKS; j++) {
|
||||||
|
for (i = bd->bi_dram[j].start >> 20;
|
||||||
|
i < (bd->bi_dram[j].start + bd->bi_dram[j].size) >> 20;
|
||||||
|
i++) {
|
||||||
|
page_table[i] = i << 20 | (3 << 10) | CACHE_SETUP;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Copy the page table address to cp15 */
|
||||||
|
asm volatile("mcr p15, 0, %0, c2, c0, 0"
|
||||||
|
: : "r" (page_table) : "memory");
|
||||||
|
/* Set the access control to all-supervisor */
|
||||||
|
asm volatile("mcr p15, 0, %0, c3, c0, 0"
|
||||||
|
: : "r" (~0));
|
||||||
|
/* and enable the mmu */
|
||||||
|
reg = get_cr(); /* get control reg. */
|
||||||
|
cp_delay();
|
||||||
|
set_cr(reg | CR_M);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* cache_bit must be either CR_I or CR_C */
|
/* cache_bit must be either CR_I or CR_C */
|
||||||
@ -39,6 +109,9 @@ static void cache_enable(uint32_t cache_bit)
|
|||||||
{
|
{
|
||||||
uint32_t reg;
|
uint32_t reg;
|
||||||
|
|
||||||
|
/* The data cache is not active unless the mmu is enabled too */
|
||||||
|
if (cache_bit == CR_C)
|
||||||
|
mmu_setup();
|
||||||
reg = get_cr(); /* get control reg. */
|
reg = get_cr(); /* get control reg. */
|
||||||
cp_delay();
|
cp_delay();
|
||||||
set_cr(reg | cache_bit);
|
set_cr(reg | cache_bit);
|
||||||
@ -49,6 +122,15 @@ static void cache_disable(uint32_t cache_bit)
|
|||||||
{
|
{
|
||||||
uint32_t reg;
|
uint32_t reg;
|
||||||
|
|
||||||
|
if (cache_bit == CR_C) {
|
||||||
|
/* if cache isn;t enabled no need to disable */
|
||||||
|
reg = get_cr();
|
||||||
|
if ((reg & CR_C) != CR_C)
|
||||||
|
return;
|
||||||
|
/* if disabling data cache, disable mmu too */
|
||||||
|
cache_bit |= CR_M;
|
||||||
|
flush_cache(0, ~0);
|
||||||
|
}
|
||||||
reg = get_cr();
|
reg = get_cr();
|
||||||
cp_delay();
|
cp_delay();
|
||||||
set_cr(reg & ~cache_bit);
|
set_cr(reg & ~cache_bit);
|
||||||
|
@ -27,10 +27,21 @@
|
|||||||
|
|
||||||
void flush_cache (unsigned long dummy1, unsigned long dummy2)
|
void flush_cache (unsigned long dummy1, unsigned long dummy2)
|
||||||
{
|
{
|
||||||
#ifdef CONFIG_OMAP2420
|
#if defined(CONFIG_OMAP2420) || defined(CONFIG_ARM1136)
|
||||||
void arm1136_cache_flush(void);
|
void arm1136_cache_flush(void);
|
||||||
|
|
||||||
arm1136_cache_flush();
|
arm1136_cache_flush();
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_ARM926EJS
|
||||||
|
/* test and clean, page 2-23 of arm926ejs manual */
|
||||||
|
asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
|
||||||
|
/* disable write buffer as well (page 2-22) */
|
||||||
|
asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_ARMCORTEXA8
|
||||||
|
void v7_flush_cache_all(void);
|
||||||
|
|
||||||
|
v7_flush_cache_all();
|
||||||
#endif
|
#endif
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
@ -38,15 +38,20 @@
|
|||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <asm/proc-armv/ptrace.h>
|
#include <asm/proc-armv/ptrace.h>
|
||||||
|
|
||||||
#ifdef CONFIG_USE_IRQ
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
#ifdef CONFIG_USE_IRQ
|
||||||
int interrupt_init (void)
|
int interrupt_init (void)
|
||||||
{
|
{
|
||||||
/*
|
/*
|
||||||
* setup up stacks if necessary
|
* setup up stacks if necessary
|
||||||
*/
|
*/
|
||||||
|
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
|
IRQ_STACK_START = gd->irq_sp - 4;
|
||||||
|
IRQ_STACK_START_IN = gd->irq_sp + 8;
|
||||||
|
#else
|
||||||
IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
|
IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
|
||||||
|
#endif
|
||||||
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
|
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
|
||||||
|
|
||||||
return arch_interrupt_init();
|
return arch_interrupt_init();
|
||||||
@ -81,6 +86,18 @@ int disable_interrupts (void)
|
|||||||
return (old & 0x80) == 0;
|
return (old & 0x80) == 0;
|
||||||
}
|
}
|
||||||
#else
|
#else
|
||||||
|
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
||||||
|
int interrupt_init (void)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* setup up stacks if necessary
|
||||||
|
*/
|
||||||
|
IRQ_STACK_START_IN = gd->irq_sp + 8;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
void enable_interrupts (void)
|
void enable_interrupts (void)
|
||||||
{
|
{
|
||||||
return;
|
return;
|
||||||
|
@ -46,6 +46,7 @@ typedef struct global_data {
|
|||||||
void *fb_base; /* framebuffer address */
|
void *fb_base; /* framebuffer address */
|
||||||
#endif
|
#endif
|
||||||
void **jt; /* jump table */
|
void **jt; /* jump table */
|
||||||
|
char env_buf[32]; /* buffer for getenv() before reloc. */
|
||||||
} gd_t;
|
} gd_t;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -56,8 +57,9 @@ typedef struct global_data {
|
|||||||
#define GD_FLG_SILENT 0x00004 /* Silent mode */
|
#define GD_FLG_SILENT 0x00004 /* Silent mode */
|
||||||
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
|
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
|
||||||
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
|
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
|
||||||
#define GD_FLG_LOGINIT 0x00020 /* Log Buf has been initialized */
|
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
|
||||||
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
|
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
|
||||||
|
#define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */
|
||||||
|
|
||||||
#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm("r5")
|
#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm("r5")
|
||||||
|
|
||||||
|
@ -26,7 +26,6 @@ typedef struct bd_info {
|
|||||||
unsigned long bi_baudrate;
|
unsigned long bi_baudrate;
|
||||||
unsigned long bi_ip_addr;
|
unsigned long bi_ip_addr;
|
||||||
unsigned char bi_phy_id[4];
|
unsigned char bi_phy_id[4];
|
||||||
struct environment_s *bi_env;
|
|
||||||
unsigned long bi_board_number;
|
unsigned long bi_board_number;
|
||||||
void *bi_boot_params;
|
void *bi_boot_params;
|
||||||
struct {
|
struct {
|
||||||
|
@ -273,30 +273,13 @@ void board_init_r(gd_t *new_gd, ulong dest_addr)
|
|||||||
|
|
||||||
monitor_flash_len = _edata - _text;
|
monitor_flash_len = _edata - _text;
|
||||||
|
|
||||||
|
#if !defined(CONFIG_RELOC_FIXUP_WORKS)
|
||||||
/*
|
/*
|
||||||
* We have to relocate the command table manually
|
* We have to relocate the command table manually
|
||||||
*/
|
*/
|
||||||
for (cmdtp = &__u_boot_cmd_start;
|
fixup_cmdtable(&__u_boot_cmd_start,
|
||||||
cmdtp != &__u_boot_cmd_end; cmdtp++) {
|
(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
|
||||||
unsigned long addr;
|
#endif /* !defined(CONFIG_RELOC_FIXUP_WORKS) */
|
||||||
|
|
||||||
addr = (unsigned long)cmdtp->cmd + gd->reloc_off;
|
|
||||||
cmdtp->cmd = (typeof(cmdtp->cmd))addr;
|
|
||||||
|
|
||||||
addr = (unsigned long)cmdtp->name + gd->reloc_off;
|
|
||||||
cmdtp->name = (typeof(cmdtp->name))addr;
|
|
||||||
|
|
||||||
if (cmdtp->usage) {
|
|
||||||
addr = (unsigned long)cmdtp->usage + gd->reloc_off;
|
|
||||||
cmdtp->usage = (typeof(cmdtp->usage))addr;
|
|
||||||
}
|
|
||||||
#ifdef CONFIG_SYS_LONGHELP
|
|
||||||
if (cmdtp->help) {
|
|
||||||
addr = (unsigned long)cmdtp->help + gd->reloc_off;
|
|
||||||
cmdtp->help = (typeof(cmdtp->help))addr;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
/* there are some other pointer constants we must deal with */
|
/* there are some other pointer constants we must deal with */
|
||||||
#ifndef CONFIG_ENV_IS_NOWHERE
|
#ifndef CONFIG_ENV_IS_NOWHERE
|
||||||
|
@ -3,7 +3,7 @@
|
|||||||
*
|
*
|
||||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||||
*
|
*
|
||||||
* (C) Copyright 2000-2004
|
* (C) Copyright 2000-2010
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
*
|
*
|
||||||
* See file CREDITS for list of people who contributed to this
|
* See file CREDITS for list of people who contributed to this
|
||||||
@ -54,6 +54,7 @@ typedef struct global_data {
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
void **jt; /* jump table */
|
void **jt; /* jump table */
|
||||||
|
char env_buf[32]; /* buffer for getenv() before reloc. */
|
||||||
} gd_t;
|
} gd_t;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -64,8 +65,9 @@ typedef struct global_data {
|
|||||||
#define GD_FLG_SILENT 0x00004 /* Silent mode */
|
#define GD_FLG_SILENT 0x00004 /* Silent mode */
|
||||||
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
|
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
|
||||||
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
|
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
|
||||||
#define GD_FLG_LOGINIT 0x00020 /* Log Buf has been initialized */
|
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
|
||||||
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
|
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
|
||||||
|
#define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */
|
||||||
|
|
||||||
#define DECLARE_GLOBAL_DATA_PTR register gd_t * volatile gd asm ("P3")
|
#define DECLARE_GLOBAL_DATA_PTR register gd_t * volatile gd asm ("P3")
|
||||||
|
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
* (C) Copyright 2002
|
* (C) Copyright 2002-2010
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
*
|
*
|
||||||
* See file CREDITS for list of people who contributed to this
|
* See file CREDITS for list of people who contributed to this
|
||||||
@ -46,6 +46,7 @@ typedef struct {
|
|||||||
phys_size_t ram_size; /* RAM size */
|
phys_size_t ram_size; /* RAM size */
|
||||||
unsigned long reset_status; /* reset status register at boot */
|
unsigned long reset_status; /* reset status register at boot */
|
||||||
void **jt; /* jump table */
|
void **jt; /* jump table */
|
||||||
|
char env_buf[32]; /* buffer for getenv() before reloc. */
|
||||||
} gd_t;
|
} gd_t;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -58,6 +59,7 @@ typedef struct {
|
|||||||
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
|
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
|
||||||
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
|
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
|
||||||
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
|
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
|
||||||
|
#define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */
|
||||||
|
|
||||||
extern gd_t *gd;
|
extern gd_t *gd;
|
||||||
|
|
||||||
|
@ -51,7 +51,6 @@ typedef struct bd_info {
|
|||||||
unsigned long bi_busfreq; /* Bus Freq, in MHz */
|
unsigned long bi_busfreq; /* Bus Freq, in MHz */
|
||||||
unsigned int bi_baudrate; /* Console Baudrate */
|
unsigned int bi_baudrate; /* Console Baudrate */
|
||||||
unsigned long bi_boot_params; /* where this board expects params */
|
unsigned long bi_boot_params; /* where this board expects params */
|
||||||
struct environment_s *bi_env;
|
|
||||||
struct /* RAM configuration */
|
struct /* RAM configuration */
|
||||||
{
|
{
|
||||||
ulong start;
|
ulong start;
|
||||||
@ -59,7 +58,4 @@ typedef struct bd_info {
|
|||||||
}bi_dram[CONFIG_NR_DRAM_BANKS];
|
}bi_dram[CONFIG_NR_DRAM_BANKS];
|
||||||
} bd_t;
|
} bd_t;
|
||||||
|
|
||||||
#define bi_env_data bi_env->data
|
|
||||||
#define bi_env_crc bi_env->crc
|
|
||||||
|
|
||||||
#endif /* _U_BOOT_H_ */
|
#endif /* _U_BOOT_H_ */
|
||||||
|
@ -335,13 +335,6 @@ void board_init_r(gd_t *id, ulong dest_addr)
|
|||||||
enable_interrupts();
|
enable_interrupts();
|
||||||
show_boot_progress(0x28);
|
show_boot_progress(0x28);
|
||||||
|
|
||||||
/* Must happen after interrupts are initialized since
|
|
||||||
* an irq handler gets installed
|
|
||||||
*/
|
|
||||||
#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
|
|
||||||
serial_buffered_init();
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_STATUS_LED
|
#ifdef CONFIG_STATUS_LED
|
||||||
status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING);
|
status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING);
|
||||||
#endif
|
#endif
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
* (C) Copyright 2002 - 2003
|
* (C) Copyright 2002 - 2010
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
*
|
*
|
||||||
* See file CREDITS for list of people who contributed to this
|
* See file CREDITS for list of people who contributed to this
|
||||||
@ -64,6 +64,7 @@ typedef struct global_data {
|
|||||||
unsigned long board_type;
|
unsigned long board_type;
|
||||||
#endif
|
#endif
|
||||||
void **jt; /* Standalone app jump table */
|
void **jt; /* Standalone app jump table */
|
||||||
|
char env_buf[32]; /* buffer for getenv() before reloc. */
|
||||||
} gd_t;
|
} gd_t;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -76,6 +77,7 @@ typedef struct global_data {
|
|||||||
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
|
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
|
||||||
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
|
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
|
||||||
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
|
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
|
||||||
|
#define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */
|
||||||
|
|
||||||
#if 0
|
#if 0
|
||||||
extern gd_t *global_data;
|
extern gd_t *global_data;
|
||||||
|
@ -79,14 +79,6 @@ extern flash_info_t flash_info[];
|
|||||||
|
|
||||||
#include <environment.h>
|
#include <environment.h>
|
||||||
|
|
||||||
#if ( ((CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) < CONFIG_SYS_MONITOR_BASE) || \
|
|
||||||
(CONFIG_ENV_ADDR >= (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)) ) || \
|
|
||||||
defined(CONFIG_ENV_IS_IN_NVRAM)
|
|
||||||
#define TOTAL_MALLOC_LEN (CONFIG_SYS_MALLOC_LEN + CONFIG_ENV_SIZE)
|
|
||||||
#else
|
|
||||||
#define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN
|
|
||||||
#endif
|
|
||||||
|
|
||||||
extern ulong __init_end;
|
extern ulong __init_end;
|
||||||
extern ulong _end;
|
extern ulong _end;
|
||||||
|
|
||||||
@ -433,33 +425,14 @@ void board_init_r (gd_t *id, ulong dest_addr)
|
|||||||
|
|
||||||
monitor_flash_len = (ulong)&__init_end - dest_addr;
|
monitor_flash_len = (ulong)&__init_end - dest_addr;
|
||||||
|
|
||||||
|
#if !defined(CONFIG_RELOC_FIXUP_WORKS)
|
||||||
/*
|
/*
|
||||||
* We have to relocate the command table manually
|
* We have to relocate the command table manually
|
||||||
*/
|
*/
|
||||||
for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) {
|
fixup_cmdtable(&__u_boot_cmd_start,
|
||||||
ulong addr;
|
(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
|
||||||
addr = (ulong) (cmdtp->cmd) + gd->reloc_off;
|
#endif /* !defined(CONFIG_RELOC_FIXUP_WORKS) */
|
||||||
#if 0
|
|
||||||
printf ("Command \"%s\": 0x%08lx => 0x%08lx\n",
|
|
||||||
cmdtp->name, (ulong) (cmdtp->cmd), addr);
|
|
||||||
#endif
|
|
||||||
cmdtp->cmd =
|
|
||||||
(int (*)(struct cmd_tbl_s *, int, int, char *[]))addr;
|
|
||||||
|
|
||||||
addr = (ulong)(cmdtp->name) + gd->reloc_off;
|
|
||||||
cmdtp->name = (char *)addr;
|
|
||||||
|
|
||||||
if (cmdtp->usage) {
|
|
||||||
addr = (ulong)(cmdtp->usage) + gd->reloc_off;
|
|
||||||
cmdtp->usage = (char *)addr;
|
|
||||||
}
|
|
||||||
#ifdef CONFIG_SYS_LONGHELP
|
|
||||||
if (cmdtp->help) {
|
|
||||||
addr = (ulong)(cmdtp->help) + gd->reloc_off;
|
|
||||||
cmdtp->help = (char *)addr;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
/* there are some other pointer constants we must deal with */
|
/* there are some other pointer constants we must deal with */
|
||||||
#ifndef CONFIG_ENV_IS_NOWHERE
|
#ifndef CONFIG_ENV_IS_NOWHERE
|
||||||
env_name_spec += gd->reloc_off;
|
env_name_spec += gd->reloc_off;
|
||||||
@ -596,10 +569,6 @@ void board_init_r (gd_t *id, ulong dest_addr)
|
|||||||
*/
|
*/
|
||||||
timer_init();
|
timer_init();
|
||||||
|
|
||||||
#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
|
|
||||||
serial_buffered_init();
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_STATUS_LED
|
#ifdef CONFIG_STATUS_LED
|
||||||
status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING);
|
status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING);
|
||||||
#endif
|
#endif
|
||||||
|
@ -43,6 +43,7 @@ typedef struct global_data {
|
|||||||
unsigned long env_valid; /* Checksum of Environment valid? */
|
unsigned long env_valid; /* Checksum of Environment valid? */
|
||||||
unsigned long fb_base; /* base address of frame buffer */
|
unsigned long fb_base; /* base address of frame buffer */
|
||||||
void **jt; /* jump table */
|
void **jt; /* jump table */
|
||||||
|
char env_buf[32]; /* buffer for getenv() before reloc. */
|
||||||
} gd_t;
|
} gd_t;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -55,6 +56,7 @@ typedef struct global_data {
|
|||||||
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
|
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
|
||||||
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
|
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
|
||||||
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
|
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
|
||||||
|
#define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */
|
||||||
|
|
||||||
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r31")
|
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r31")
|
||||||
|
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
* (C) Copyright 2002-2003
|
* (C) Copyright 2002-2010
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
*
|
*
|
||||||
* See file CREDITS for list of people who contributed to this
|
* See file CREDITS for list of people who contributed to this
|
||||||
@ -46,6 +46,7 @@ typedef struct global_data {
|
|||||||
unsigned long env_addr; /* Address of Environment struct */
|
unsigned long env_addr; /* Address of Environment struct */
|
||||||
unsigned long env_valid; /* Checksum of Environment valid? */
|
unsigned long env_valid; /* Checksum of Environment valid? */
|
||||||
void **jt; /* jump table */
|
void **jt; /* jump table */
|
||||||
|
char env_buf[32]; /* buffer for getenv() before reloc. */
|
||||||
} gd_t;
|
} gd_t;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -56,8 +57,9 @@ typedef struct global_data {
|
|||||||
#define GD_FLG_SILENT 0x00004 /* Silent mode */
|
#define GD_FLG_SILENT 0x00004 /* Silent mode */
|
||||||
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
|
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
|
||||||
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
|
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
|
||||||
#define GD_FLG_LOGINIT 0x00020 /* Log Buf has been initialized */
|
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
|
||||||
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
|
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
|
||||||
|
#define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */
|
||||||
|
|
||||||
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("k0")
|
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("k0")
|
||||||
|
|
||||||
|
@ -42,7 +42,5 @@ typedef struct bd_info {
|
|||||||
unsigned long bi_flashsize; /* size of FLASH memory */
|
unsigned long bi_flashsize; /* size of FLASH memory */
|
||||||
unsigned long bi_flashoffset; /* reserved area for startup monitor */
|
unsigned long bi_flashoffset; /* reserved area for startup monitor */
|
||||||
} bd_t;
|
} bd_t;
|
||||||
#define bi_env_data bi_env->data
|
|
||||||
#define bi_env_crc bi_env->crc
|
|
||||||
|
|
||||||
#endif /* _U_BOOT_H_ */
|
#endif /* _U_BOOT_H_ */
|
||||||
|
@ -39,14 +39,6 @@
|
|||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
#if ( ((CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) < CONFIG_SYS_MONITOR_BASE) || \
|
|
||||||
(CONFIG_ENV_ADDR >= (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)) ) || \
|
|
||||||
defined(CONFIG_ENV_IS_IN_NVRAM)
|
|
||||||
#define TOTAL_MALLOC_LEN (CONFIG_SYS_MALLOC_LEN + CONFIG_ENV_SIZE)
|
|
||||||
#else
|
|
||||||
#define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#undef DEBUG
|
#undef DEBUG
|
||||||
|
|
||||||
extern int timer_init(void);
|
extern int timer_init(void);
|
||||||
@ -304,34 +296,14 @@ void board_init_r (gd_t *id, ulong dest_addr)
|
|||||||
|
|
||||||
monitor_flash_len = (ulong)&uboot_end_data - dest_addr;
|
monitor_flash_len = (ulong)&uboot_end_data - dest_addr;
|
||||||
|
|
||||||
|
#if !defined(CONFIG_RELOC_FIXUP_WORKS)
|
||||||
/*
|
/*
|
||||||
* We have to relocate the command table manually
|
* We have to relocate the command table manually
|
||||||
*/
|
*/
|
||||||
for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) {
|
fixup_cmdtable(&__u_boot_cmd_start,
|
||||||
ulong addr;
|
(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
|
||||||
|
#endif /* !defined(CONFIG_RELOC_FIXUP_WORKS) */
|
||||||
|
|
||||||
addr = (ulong) (cmdtp->cmd) + gd->reloc_off;
|
|
||||||
#if 0
|
|
||||||
printf ("Command \"%s\": 0x%08lx => 0x%08lx\n",
|
|
||||||
cmdtp->name, (ulong) (cmdtp->cmd), addr);
|
|
||||||
#endif
|
|
||||||
cmdtp->cmd =
|
|
||||||
(int (*)(struct cmd_tbl_s *, int, int, char *[]))addr;
|
|
||||||
|
|
||||||
addr = (ulong)(cmdtp->name) + gd->reloc_off;
|
|
||||||
cmdtp->name = (char *)addr;
|
|
||||||
|
|
||||||
if (cmdtp->usage) {
|
|
||||||
addr = (ulong)(cmdtp->usage) + gd->reloc_off;
|
|
||||||
cmdtp->usage = (char *)addr;
|
|
||||||
}
|
|
||||||
#ifdef CONFIG_SYS_LONGHELP
|
|
||||||
if (cmdtp->help) {
|
|
||||||
addr = (ulong)(cmdtp->help) + gd->reloc_off;
|
|
||||||
cmdtp->help = (char *)addr;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
/* there are some other pointer constants we must deal with */
|
/* there are some other pointer constants we must deal with */
|
||||||
#ifndef CONFIG_ENV_IS_NOWHERE
|
#ifndef CONFIG_ENV_IS_NOWHERE
|
||||||
env_name_spec += gd->reloc_off;
|
env_name_spec += gd->reloc_off;
|
||||||
|
@ -37,6 +37,7 @@ typedef struct global_data {
|
|||||||
unsigned long post_init_f_time; /* When post_init_f started */
|
unsigned long post_init_f_time; /* When post_init_f started */
|
||||||
#endif
|
#endif
|
||||||
void **jt; /* Standalone app jump table */
|
void **jt; /* Standalone app jump table */
|
||||||
|
char env_buf[32]; /* buffer for getenv() before reloc. */
|
||||||
} gd_t;
|
} gd_t;
|
||||||
|
|
||||||
/* flags */
|
/* flags */
|
||||||
@ -47,6 +48,7 @@ typedef struct global_data {
|
|||||||
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
|
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
|
||||||
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
|
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
|
||||||
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
|
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
|
||||||
|
#define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */
|
||||||
|
|
||||||
#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("gp")
|
#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("gp")
|
||||||
|
|
||||||
|
@ -38,7 +38,6 @@ COBJS-y += serial.o
|
|||||||
COBJS-y += speed.o
|
COBJS-y += speed.o
|
||||||
COBJS-$(CONFIG_FSL_DIU_FB) += diu.o
|
COBJS-$(CONFIG_FSL_DIU_FB) += diu.o
|
||||||
COBJS-$(CONFIG_FSL_DIU_FB) += ../../../../board/freescale/common/fsl_diu_fb.o
|
COBJS-$(CONFIG_FSL_DIU_FB) += ../../../../board/freescale/common/fsl_diu_fb.o
|
||||||
COBJS-$(CONFIG_FSL_DIU_FB) += ../../../../board/freescale/common/fsl_logo_bmp.o
|
|
||||||
COBJS-$(CONFIG_CMD_IDE) += ide.o
|
COBJS-$(CONFIG_CMD_IDE) += ide.o
|
||||||
COBJS-$(CONFIG_IIM) += iim.o
|
COBJS-$(CONFIG_IIM) += iim.o
|
||||||
COBJS-$(CONFIG_PCI) += pci.o
|
COBJS-$(CONFIG_PCI) += pci.o
|
||||||
|
@ -36,12 +36,6 @@
|
|||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
#ifdef CONFIG_FSL_DIU_LOGO_BMP
|
|
||||||
extern unsigned int FSL_Logo_BMP[];
|
|
||||||
#else
|
|
||||||
#define FSL_Logo_BMP NULL
|
|
||||||
#endif
|
|
||||||
|
|
||||||
static int xres, yres;
|
static int xres, yres;
|
||||||
|
|
||||||
void diu_set_pixel_clock(unsigned int pixclock)
|
void diu_set_pixel_clock(unsigned int pixclock)
|
||||||
@ -64,28 +58,9 @@ void diu_set_pixel_clock(unsigned int pixclock)
|
|||||||
debug("DIU: Modified value of CLKDVDR = 0x%08x\n", in_be32(clkdvdr));
|
debug("DIU: Modified value of CLKDVDR = 0x%08x\n", in_be32(clkdvdr));
|
||||||
}
|
}
|
||||||
|
|
||||||
char *valid_bmp(char *addr)
|
|
||||||
{
|
|
||||||
unsigned long h_addr;
|
|
||||||
bd_t *bd = gd->bd;
|
|
||||||
|
|
||||||
h_addr = simple_strtoul(addr, NULL, 16);
|
|
||||||
if (h_addr < bd->bi_flashstart ||
|
|
||||||
h_addr >= (bd->bi_flashstart + bd->bi_flashsize - 1)) {
|
|
||||||
printf("bmp addr %lx is not a valid flash address\n", h_addr);
|
|
||||||
return 0;
|
|
||||||
} else if ((*(char *)(h_addr) != 'B') || (*(char *)(h_addr+1) != 'M')) {
|
|
||||||
printf("bmp addr is not a bmp\n");
|
|
||||||
return 0;
|
|
||||||
} else
|
|
||||||
return (char *)h_addr;
|
|
||||||
}
|
|
||||||
|
|
||||||
int mpc5121_diu_init(void)
|
int mpc5121_diu_init(void)
|
||||||
{
|
{
|
||||||
unsigned int pixel_format;
|
unsigned int pixel_format;
|
||||||
char *bmp = NULL;
|
|
||||||
char *bmp_env;
|
|
||||||
|
|
||||||
#if defined(CONFIG_VIDEO_XRES) & defined(CONFIG_VIDEO_YRES)
|
#if defined(CONFIG_VIDEO_XRES) & defined(CONFIG_VIDEO_YRES)
|
||||||
xres = CONFIG_VIDEO_XRES;
|
xres = CONFIG_VIDEO_XRES;
|
||||||
@ -97,46 +72,9 @@ int mpc5121_diu_init(void)
|
|||||||
pixel_format = 0x88883316;
|
pixel_format = 0x88883316;
|
||||||
|
|
||||||
debug("mpc5121_diu_init\n");
|
debug("mpc5121_diu_init\n");
|
||||||
bmp_env = getenv("diu_bmp_addr");
|
|
||||||
if (bmp_env) {
|
return fsl_diu_init(xres, pixel_format, 0);
|
||||||
bmp = valid_bmp(bmp_env);
|
|
||||||
}
|
}
|
||||||
if (!bmp)
|
|
||||||
bmp = (char *)FSL_Logo_BMP;
|
|
||||||
return fsl_diu_init(xres, pixel_format, 0, (unsigned char *)bmp);
|
|
||||||
}
|
|
||||||
|
|
||||||
int mpc5121diu_init_show_bmp(cmd_tbl_t *cmdtp,
|
|
||||||
int flag, int argc, char * const argv[])
|
|
||||||
{
|
|
||||||
unsigned int addr;
|
|
||||||
|
|
||||||
if (argc < 2)
|
|
||||||
return cmd_usage(cmdtp);
|
|
||||||
|
|
||||||
if (!strncmp(argv[1], "init", 4)) {
|
|
||||||
#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
|
|
||||||
fsl_diu_clear_screen();
|
|
||||||
drv_video_init();
|
|
||||||
#else
|
|
||||||
return mpc5121_diu_init();
|
|
||||||
#endif
|
|
||||||
} else {
|
|
||||||
addr = simple_strtoul(argv[1], NULL, 16);
|
|
||||||
fsl_diu_clear_screen();
|
|
||||||
fsl_diu_display_bmp((unsigned char *)addr, 0, 0, 0);
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
U_BOOT_CMD(
|
|
||||||
diufb, CONFIG_SYS_MAXARGS, 1, mpc5121diu_init_show_bmp,
|
|
||||||
"Init or Display BMP file",
|
|
||||||
"init\n - initialize DIU\n"
|
|
||||||
"addr\n - display bmp at address 'addr'"
|
|
||||||
);
|
|
||||||
|
|
||||||
|
|
||||||
#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
|
#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
|
||||||
|
|
||||||
@ -158,7 +96,7 @@ void *video_hw_init(void)
|
|||||||
|
|
||||||
pGD->frameAdrs = (unsigned int)fsl_fb_open(&info);
|
pGD->frameAdrs = (unsigned int)fsl_fb_open(&info);
|
||||||
pGD->winSizeX = xres;
|
pGD->winSizeX = xres;
|
||||||
pGD->winSizeY = yres - info->logo_height;
|
pGD->winSizeY = yres;
|
||||||
pGD->plnSizeX = pGD->winSizeX;
|
pGD->plnSizeX = pGD->winSizeX;
|
||||||
pGD->plnSizeY = pGD->winSizeY;
|
pGD->plnSizeY = pGD->winSizeY;
|
||||||
|
|
||||||
@ -167,7 +105,7 @@ void *video_hw_init(void)
|
|||||||
|
|
||||||
pGD->isaBase = 0;
|
pGD->isaBase = 0;
|
||||||
pGD->pciBase = 0;
|
pGD->pciBase = 0;
|
||||||
pGD->memSize = info->screen_size - info->logo_size;
|
pGD->memSize = info->screen_size;
|
||||||
|
|
||||||
/* Cursor Start Address */
|
/* Cursor Start Address */
|
||||||
pGD->dprBase = 0;
|
pGD->dprBase = 0;
|
||||||
|
@ -126,6 +126,12 @@ void cpu_init_f (volatile immap_t * im)
|
|||||||
#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
|
#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
|
||||||
SCCR_PCICM |
|
SCCR_PCICM |
|
||||||
#endif
|
#endif
|
||||||
|
#ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */
|
||||||
|
SCCR_PCIEXP1CM |
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */
|
||||||
|
SCCR_PCIEXP2CM |
|
||||||
|
#endif
|
||||||
#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
|
#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
|
||||||
SCCR_TSECCM |
|
SCCR_TSECCM |
|
||||||
#endif
|
#endif
|
||||||
@ -158,6 +164,12 @@ void cpu_init_f (volatile immap_t * im)
|
|||||||
#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
|
#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
|
||||||
(CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) |
|
(CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) |
|
||||||
#endif
|
#endif
|
||||||
|
#ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */
|
||||||
|
(CONFIG_SYS_SCCR_PCIEXP1CM << SCCR_PCIEXP1CM_SHIFT) |
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */
|
||||||
|
(CONFIG_SYS_SCCR_PCIEXP2CM << SCCR_PCIEXP2CM_SHIFT) |
|
||||||
|
#endif
|
||||||
#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
|
#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
|
||||||
(CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
|
(CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
|
||||||
#endif
|
#endif
|
||||||
|
@ -133,7 +133,7 @@ static void pci_init_bus(int bus, struct pci_region *reg)
|
|||||||
* If fewer than three regions are requested, then the region
|
* If fewer than three regions are requested, then the region
|
||||||
* list is terminated with a region of size 0.
|
* list is terminated with a region of size 0.
|
||||||
*/
|
*/
|
||||||
void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot)
|
void mpc83xx_pci_init(int num_buses, struct pci_region **reg)
|
||||||
{
|
{
|
||||||
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
|
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
|
||||||
int i;
|
int i;
|
||||||
@ -150,9 +150,9 @@ void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot)
|
|||||||
/*
|
/*
|
||||||
* Release PCI RST Output signal.
|
* Release PCI RST Output signal.
|
||||||
* Power on to RST high must be at least 100 ms as per PCI spec.
|
* Power on to RST high must be at least 100 ms as per PCI spec.
|
||||||
* On warm boots only 1 ms is required.
|
* On warm boots only 1 ms is required, but we play it safe.
|
||||||
*/
|
*/
|
||||||
udelay(warmboot ? 1000 : 100000);
|
udelay(100000);
|
||||||
|
|
||||||
for (i = 0; i < num_buses; i++)
|
for (i = 0; i < num_buses; i++)
|
||||||
immr->pci_ctrl[i].gcr = 1;
|
immr->pci_ctrl[i].gcr = 1;
|
||||||
|
@ -30,6 +30,22 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||||||
|
|
||||||
#define PCIE_MAX_BUSES 2
|
#define PCIE_MAX_BUSES 2
|
||||||
|
|
||||||
|
static struct {
|
||||||
|
u32 base;
|
||||||
|
u32 size;
|
||||||
|
} mpc83xx_pcie_cfg_space[] = {
|
||||||
|
{
|
||||||
|
.base = CONFIG_SYS_PCIE1_CFG_BASE,
|
||||||
|
.size = CONFIG_SYS_PCIE1_CFG_SIZE,
|
||||||
|
},
|
||||||
|
#if defined(CONFIG_SYS_PCIE2_CFG_BASE) && defined(CONFIG_SYS_PCIE2_CFG_SIZE)
|
||||||
|
{
|
||||||
|
.base = CONFIG_SYS_PCIE2_CFG_BASE,
|
||||||
|
.size = CONFIG_SYS_PCIE2_CFG_SIZE,
|
||||||
|
},
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
|
||||||
#ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
|
#ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
|
||||||
|
|
||||||
static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev)
|
static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev)
|
||||||
@ -124,10 +140,7 @@ static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
|
|||||||
hose->first_busno = pci_last_busno() + 1;
|
hose->first_busno = pci_last_busno() + 1;
|
||||||
hose->last_busno = 0xff;
|
hose->last_busno = 0xff;
|
||||||
|
|
||||||
if (bus == 0)
|
hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base;
|
||||||
hose->cfg_addr = (unsigned int *)CONFIG_SYS_PCIE1_CFG_BASE;
|
|
||||||
else
|
|
||||||
hose->cfg_addr = (unsigned int *)CONFIG_SYS_PCIE2_CFG_BASE;
|
|
||||||
|
|
||||||
pci_set_ops(hose,
|
pci_set_ops(hose,
|
||||||
pcie_read_config_byte,
|
pcie_read_config_byte,
|
||||||
@ -182,15 +195,9 @@ static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
|
|||||||
PEX_CSB_OBCTRL_CFGWE);
|
PEX_CSB_OBCTRL_CFGWE);
|
||||||
|
|
||||||
out_win = &pex->bridge.pex_outbound_win[0];
|
out_win = &pex->bridge.pex_outbound_win[0];
|
||||||
if (bus) {
|
|
||||||
out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG |
|
out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG |
|
||||||
CONFIG_SYS_PCIE2_CFG_SIZE);
|
mpc83xx_pcie_cfg_space[bus].size);
|
||||||
out_le32(&out_win->bar, CONFIG_SYS_PCIE2_CFG_BASE);
|
out_le32(&out_win->bar, mpc83xx_pcie_cfg_space[bus].base);
|
||||||
} else {
|
|
||||||
out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG |
|
|
||||||
CONFIG_SYS_PCIE1_CFG_SIZE);
|
|
||||||
out_le32(&out_win->bar, CONFIG_SYS_PCIE1_CFG_BASE);
|
|
||||||
}
|
|
||||||
out_le32(&out_win->tarl, 0);
|
out_le32(&out_win->tarl, 0);
|
||||||
out_le32(&out_win->tarh, 0);
|
out_le32(&out_win->tarh, 0);
|
||||||
|
|
||||||
@ -301,16 +308,21 @@ static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
|
|||||||
* The caller must have already set SCCR, SERDES and the PCIE_LAW BARs
|
* The caller must have already set SCCR, SERDES and the PCIE_LAW BARs
|
||||||
* must have been set to cover all of the requested regions.
|
* must have been set to cover all of the requested regions.
|
||||||
*/
|
*/
|
||||||
void mpc83xx_pcie_init(int num_buses, struct pci_region **reg, int warmboot)
|
void mpc83xx_pcie_init(int num_buses, struct pci_region **reg)
|
||||||
{
|
{
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Release PCI RST Output signal.
|
* Release PCI RST Output signal.
|
||||||
* Power on to RST high must be at least 100 ms as per PCI spec.
|
* Power on to RST high must be at least 100 ms as per PCI spec.
|
||||||
* On warm boots only 1 ms is required.
|
* On warm boots only 1 ms is required, but we play it safe.
|
||||||
*/
|
*/
|
||||||
udelay(warmboot ? 1000 : 100000);
|
udelay(100000);
|
||||||
|
|
||||||
|
if (num_buses > ARRAY_SIZE(mpc83xx_pcie_cfg_space)) {
|
||||||
|
printf("Second PCIE host contoller not configured!\n");
|
||||||
|
num_buses = ARRAY_SIZE(mpc83xx_pcie_cfg_space);
|
||||||
|
}
|
||||||
|
|
||||||
for (i = 0; i < num_buses; i++)
|
for (i = 0; i < num_buses; i++)
|
||||||
mpc83xx_pcie_init_bus(i, reg[i]);
|
mpc83xx_pcie_init_bus(i, reg[i]);
|
||||||
|
@ -45,7 +45,7 @@
|
|||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <asm/processor.h>
|
#include <asm/processor.h>
|
||||||
#include <i2c.h>
|
#include <i2c.h>
|
||||||
#include <ppc4xx.h>
|
#include <asm/ppc4xx.h>
|
||||||
|
|
||||||
#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_440)
|
#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_440)
|
||||||
|
|
||||||
|
@ -50,7 +50,7 @@
|
|||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <asm/processor.h>
|
#include <asm/processor.h>
|
||||||
#include <i2c.h>
|
#include <i2c.h>
|
||||||
#include <ppc4xx.h>
|
#include <asm/ppc4xx.h>
|
||||||
#include <asm/mmu.h>
|
#include <asm/mmu.h>
|
||||||
|
|
||||||
#include "ecc.h"
|
#include "ecc.h"
|
||||||
|
@ -41,7 +41,7 @@
|
|||||||
|
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <command.h>
|
#include <command.h>
|
||||||
#include <ppc4xx.h>
|
#include <asm/ppc4xx.h>
|
||||||
#include <i2c.h>
|
#include <i2c.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <asm/processor.h>
|
#include <asm/processor.h>
|
||||||
@ -469,7 +469,7 @@ phys_size_t initdram(int board_type)
|
|||||||
/*------------------------------------------------------------------
|
/*------------------------------------------------------------------
|
||||||
* Reset the DDR-SDRAM controller.
|
* Reset the DDR-SDRAM controller.
|
||||||
*-----------------------------------------------------------------*/
|
*-----------------------------------------------------------------*/
|
||||||
mtsdr(SDR0_SRST, (0x80000000 >> 10));
|
mtsdr(SDR0_SRST, SDR0_SRST0_DMC);
|
||||||
mtsdr(SDR0_SRST, 0x00000000);
|
mtsdr(SDR0_SRST, 0x00000000);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -38,7 +38,7 @@
|
|||||||
#undef DEBUG
|
#undef DEBUG
|
||||||
|
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <ppc4xx.h>
|
#include <asm/ppc4xx.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <asm/processor.h>
|
#include <asm/processor.h>
|
||||||
|
|
||||||
|
@ -594,35 +594,35 @@ int __pci_pre_init(struct pci_controller *hose)
|
|||||||
* Set priority for all PLB3 devices to 0.
|
* Set priority for all PLB3 devices to 0.
|
||||||
* Set PLB3 arbiter to fair mode.
|
* Set PLB3 arbiter to fair mode.
|
||||||
*/
|
*/
|
||||||
mfsdr(SD0_AMP1, reg);
|
mfsdr(SDR0_AMP1, reg);
|
||||||
mtsdr(SD0_AMP1, (reg & 0x000000FF) | 0x0000FF00);
|
mtsdr(SDR0_AMP1, (reg & 0x000000FF) | 0x0000FF00);
|
||||||
reg = mfdcr(PLB3_ACR);
|
reg = mfdcr(PLB3A0_ACR);
|
||||||
mtdcr(PLB3_ACR, reg | 0x80000000);
|
mtdcr(PLB3A0_ACR, reg | 0x80000000);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Set priority for all PLB4 devices to 0.
|
* Set priority for all PLB4 devices to 0.
|
||||||
*/
|
*/
|
||||||
mfsdr(SD0_AMP0, reg);
|
mfsdr(SDR0_AMP0, reg);
|
||||||
mtsdr(SD0_AMP0, (reg & 0x000000FF) | 0x0000FF00);
|
mtsdr(SDR0_AMP0, (reg & 0x000000FF) | 0x0000FF00);
|
||||||
reg = mfdcr(PLB4_ACR) | 0xa0000000;
|
reg = mfdcr(PLB4A0_ACR) | 0xa0000000;
|
||||||
mtdcr(PLB4_ACR, reg);
|
mtdcr(PLB4A0_ACR, reg);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Set Nebula PLB4 arbiter to fair mode.
|
* Set Nebula PLB4 arbiter to fair mode.
|
||||||
*/
|
*/
|
||||||
/* Segment0 */
|
/* Segment0 */
|
||||||
reg = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
|
reg = (mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR;
|
||||||
reg = (reg & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
|
reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED;
|
||||||
reg = (reg & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
|
reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP;
|
||||||
reg = (reg & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
|
reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP;
|
||||||
mtdcr(PLB0_ACR, reg);
|
mtdcr(PLB4A0_ACR, reg);
|
||||||
|
|
||||||
/* Segment1 */
|
/* Segment1 */
|
||||||
reg = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
|
reg = (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR;
|
||||||
reg = (reg & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
|
reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED;
|
||||||
reg = (reg & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
|
reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP;
|
||||||
reg = (reg & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
|
reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP;
|
||||||
mtdcr(PLB1_ACR, reg);
|
mtdcr(PLB4A1_ACR, reg);
|
||||||
|
|
||||||
#if defined(CONFIG_SYS_PCI_BOARD_FIXUP_IRQ)
|
#if defined(CONFIG_SYS_PCI_BOARD_FIXUP_IRQ)
|
||||||
hose->fixup_irq = board_pci_fixup_irq;
|
hose->fixup_irq = board_pci_fixup_irq;
|
||||||
|
@ -27,7 +27,7 @@
|
|||||||
|
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <pci.h>
|
#include <pci.h>
|
||||||
#include <ppc4xx.h>
|
#include <asm/ppc4xx.h>
|
||||||
#include <asm/processor.h>
|
#include <asm/processor.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <asm/errno.h>
|
#include <asm/errno.h>
|
||||||
|
@ -2,6 +2,9 @@
|
|||||||
* (C) Copyright 2000-2006
|
* (C) Copyright 2000-2006
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
*
|
*
|
||||||
|
* (C) Copyright 2010
|
||||||
|
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||||
|
*
|
||||||
* See file CREDITS for list of people who contributed to this
|
* See file CREDITS for list of people who contributed to this
|
||||||
* project.
|
* project.
|
||||||
*
|
*
|
||||||
@ -49,15 +52,7 @@
|
|||||||
#include <asm/processor.h>
|
#include <asm/processor.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <watchdog.h>
|
#include <watchdog.h>
|
||||||
#include <ppc4xx.h>
|
#include <asm/ppc4xx.h>
|
||||||
|
|
||||||
#ifdef CONFIG_SERIAL_MULTI
|
|
||||||
#include <serial.h>
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
|
|
||||||
#include <malloc.h>
|
|
||||||
#endif
|
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
@ -66,24 +61,6 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||||||
defined(CONFIG_405EX) || defined(CONFIG_440)
|
defined(CONFIG_405EX) || defined(CONFIG_440)
|
||||||
|
|
||||||
#if defined(CONFIG_440)
|
#if defined(CONFIG_440)
|
||||||
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
|
|
||||||
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
|
|
||||||
defined(CONFIG_460EX) || defined(CONFIG_460GT)
|
|
||||||
#define UART0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000300)
|
|
||||||
#define UART1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000400)
|
|
||||||
#else
|
|
||||||
#define UART0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000200)
|
|
||||||
#define UART1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000300)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
|
|
||||||
#define UART2_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000600)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
|
|
||||||
#define UART2_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000500)
|
|
||||||
#define UART3_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000600)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(CONFIG_440GP)
|
#if defined(CONFIG_440GP)
|
||||||
#define CR0_MASK 0x3fff0000
|
#define CR0_MASK 0x3fff0000
|
||||||
@ -116,16 +93,14 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||||||
#define MTREG(a, d) mtsdr(a, d)
|
#define MTREG(a, d) mtsdr(a, d)
|
||||||
#endif /* #if defined(CONFIG_440GP) */
|
#endif /* #if defined(CONFIG_440GP) */
|
||||||
#elif defined(CONFIG_405EP) || defined(CONFIG_405EZ)
|
#elif defined(CONFIG_405EP) || defined(CONFIG_405EZ)
|
||||||
#define UART0_BASE 0xef600300
|
|
||||||
#define UART1_BASE 0xef600400
|
|
||||||
#define UCR0_MASK 0x0000007f
|
#define UCR0_MASK 0x0000007f
|
||||||
#define UCR1_MASK 0x00007f00
|
#define UCR1_MASK 0x00007f00
|
||||||
#define UCR0_UDIV_POS 0
|
#define UCR0_UDIV_POS 0
|
||||||
#define UCR1_UDIV_POS 8
|
#define UCR1_UDIV_POS 8
|
||||||
#define UDIV_MAX 127
|
#define UDIV_MAX 127
|
||||||
#elif defined(CONFIG_405EX)
|
#elif defined(CONFIG_405EX)
|
||||||
#define UART0_BASE 0xef600200
|
#define MFREG(a, d) mfsdr(a, d)
|
||||||
#define UART1_BASE 0xef600300
|
#define MTREG(a, d) mtsdr(a, d)
|
||||||
#define CR0_MASK 0x000000ff
|
#define CR0_MASK 0x000000ff
|
||||||
#define CR0_EXTCLK_ENA 0x00800000
|
#define CR0_EXTCLK_ENA 0x00800000
|
||||||
#define CR0_UDIV_POS 0
|
#define CR0_UDIV_POS 0
|
||||||
@ -133,223 +108,164 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||||||
#define UART0_SDR SDR0_UART0
|
#define UART0_SDR SDR0_UART0
|
||||||
#define UART1_SDR SDR0_UART1
|
#define UART1_SDR SDR0_UART1
|
||||||
#else /* CONFIG_405GP || CONFIG_405CR */
|
#else /* CONFIG_405GP || CONFIG_405CR */
|
||||||
#define UART0_BASE 0xef600300
|
|
||||||
#define UART1_BASE 0xef600400
|
|
||||||
#define CR0_MASK 0x00001fff
|
#define CR0_MASK 0x00001fff
|
||||||
#define CR0_EXTCLK_ENA 0x000000c0
|
#define CR0_EXTCLK_ENA 0x000000c0
|
||||||
#define CR0_UDIV_POS 1
|
#define CR0_UDIV_POS 1
|
||||||
#define UDIV_MAX 32
|
#define UDIV_MAX 32
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* using serial port 0 or 1 as U-Boot console ? */
|
|
||||||
#if defined(CONFIG_UART1_CONSOLE)
|
|
||||||
#define ACTING_UART0_BASE UART1_BASE
|
|
||||||
#define ACTING_UART1_BASE UART0_BASE
|
|
||||||
#else
|
|
||||||
#define ACTING_UART0_BASE UART0_BASE
|
|
||||||
#define ACTING_UART1_BASE UART1_BASE
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(CONFIG_405EP) && defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
|
#if defined(CONFIG_405EP) && defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
|
||||||
#error "External serial clock not supported on AMCC PPC405EP!"
|
#error "External serial clock not supported on AMCC PPC405EP!"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define UART_RBR 0x00
|
#if (defined(CONFIG_405EX) || defined(CONFIG_405EZ) || \
|
||||||
#define UART_THR 0x00
|
defined(CONFIG_440)) && !defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
|
||||||
#define UART_IER 0x01
|
/*
|
||||||
#define UART_IIR 0x02
|
* For some SoC's, the cpu clock is on divider chain A, UART on
|
||||||
#define UART_FCR 0x02
|
* divider chain B ... so cpu clock is irrelevant. Get the
|
||||||
#define UART_LCR 0x03
|
* "optimized" values that are subject to the 1/2 opb clock
|
||||||
#define UART_MCR 0x04
|
* constraint.
|
||||||
#define UART_LSR 0x05
|
|
||||||
#define UART_MSR 0x06
|
|
||||||
#define UART_SCR 0x07
|
|
||||||
#define UART_DLL 0x00
|
|
||||||
#define UART_DLM 0x01
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------------+
|
|
||||||
| Line Status Register.
|
|
||||||
+-----------------------------------------------------------------------------*/
|
|
||||||
#define asyncLSRDataReady1 0x01
|
|
||||||
#define asyncLSROverrunError1 0x02
|
|
||||||
#define asyncLSRParityError1 0x04
|
|
||||||
#define asyncLSRFramingError1 0x08
|
|
||||||
#define asyncLSRBreakInterrupt1 0x10
|
|
||||||
#define asyncLSRTxHoldEmpty1 0x20
|
|
||||||
#define asyncLSRTxShiftEmpty1 0x40
|
|
||||||
#define asyncLSRRxFifoError1 0x80
|
|
||||||
|
|
||||||
#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
|
|
||||||
/*-----------------------------------------------------------------------------+
|
|
||||||
| Fifo
|
|
||||||
+-----------------------------------------------------------------------------*/
|
|
||||||
typedef struct {
|
|
||||||
char *rx_buffer;
|
|
||||||
ulong rx_put;
|
|
||||||
ulong rx_get;
|
|
||||||
} serial_buffer_t;
|
|
||||||
|
|
||||||
volatile static serial_buffer_t buf_info;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
static void serial_init_common(u32 base, u32 udiv, u16 bdiv)
|
|
||||||
{
|
|
||||||
PPC4xx_SYS_INFO sys_info;
|
|
||||||
u8 val;
|
|
||||||
|
|
||||||
get_sys_info(&sys_info);
|
|
||||||
|
|
||||||
/* Correct UART frequency in bd-info struct now that
|
|
||||||
* the UART divisor is available
|
|
||||||
*/
|
*/
|
||||||
#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
|
static u16 serial_bdiv(int baudrate, u32 *udiv)
|
||||||
gd->uart_clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
|
|
||||||
#else
|
|
||||||
gd->uart_clk = sys_info.freqUART / udiv;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
out_8((u8 *)base + UART_LCR, 0x80); /* set DLAB bit */
|
|
||||||
out_8((u8 *)base + UART_DLL, bdiv); /* set baudrate divisor */
|
|
||||||
out_8((u8 *)base + UART_DLM, bdiv >> 8); /* set baudrate divisor */
|
|
||||||
out_8((u8 *)base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
|
|
||||||
out_8((u8 *)base + UART_FCR, 0x00); /* disable FIFO */
|
|
||||||
out_8((u8 *)base + UART_MCR, 0x00); /* no modem control DTR RTS */
|
|
||||||
val = in_8((u8 *)base + UART_LSR); /* clear line status */
|
|
||||||
val = in_8((u8 *)base + UART_RBR); /* read receive buffer */
|
|
||||||
out_8((u8 *)base + UART_SCR, 0x00); /* set scratchpad */
|
|
||||||
out_8((u8 *)base + UART_IER, 0x00); /* set interrupt enable reg */
|
|
||||||
}
|
|
||||||
|
|
||||||
#if (defined(CONFIG_440) || defined(CONFIG_405EX)) && \
|
|
||||||
!defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
|
|
||||||
static void serial_divs (int baudrate, unsigned long *pudiv,
|
|
||||||
unsigned short *pbdiv)
|
|
||||||
{
|
{
|
||||||
sys_info_t sysinfo;
|
sys_info_t sysinfo;
|
||||||
unsigned long div; /* total divisor udiv * bdiv */
|
u32 div; /* total divisor udiv * bdiv */
|
||||||
unsigned long umin; /* minimum udiv */
|
u32 umin; /* minimum udiv */
|
||||||
unsigned short diff; /* smallest diff */
|
u16 diff; /* smallest diff */
|
||||||
unsigned long udiv; /* best udiv */
|
u16 idiff; /* current diff */
|
||||||
unsigned short idiff; /* current diff */
|
u16 ibdiv; /* current bdiv */
|
||||||
unsigned short ibdiv; /* current bdiv */
|
u32 i;
|
||||||
unsigned long i;
|
u32 est; /* current estimate */
|
||||||
unsigned long est; /* current estimate */
|
u32 max;
|
||||||
|
#if defined(CONFIG_405EZ)
|
||||||
|
u32 cpr_pllc;
|
||||||
|
u32 plloutb;
|
||||||
|
u32 reg;
|
||||||
|
#endif
|
||||||
|
|
||||||
get_sys_info(&sysinfo);
|
get_sys_info(&sysinfo);
|
||||||
|
|
||||||
udiv = 32; /* Assume lowest possible serial clk */
|
#if defined(CONFIG_405EZ)
|
||||||
div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */
|
|
||||||
umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */
|
|
||||||
diff = 32; /* highest possible */
|
|
||||||
|
|
||||||
/* i is the test udiv value -- start with the largest
|
|
||||||
* possible (32) to minimize serial clock and constrain
|
|
||||||
* search to umin.
|
|
||||||
*/
|
|
||||||
for (i = 32; i > umin; i--) {
|
|
||||||
ibdiv = div / i;
|
|
||||||
est = i * ibdiv;
|
|
||||||
idiff = (est > div) ? (est-div) : (div-est);
|
|
||||||
if (idiff == 0) {
|
|
||||||
udiv = i;
|
|
||||||
break; /* can't do better */
|
|
||||||
} else if (idiff < diff) {
|
|
||||||
udiv = i; /* best so far */
|
|
||||||
diff = idiff; /* update lowest diff*/
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
*pudiv = udiv;
|
|
||||||
*pbdiv = div / udiv;
|
|
||||||
}
|
|
||||||
|
|
||||||
#elif defined(CONFIG_405EZ)
|
|
||||||
|
|
||||||
static void serial_divs (int baudrate, unsigned long *pudiv,
|
|
||||||
unsigned short *pbdiv)
|
|
||||||
{
|
|
||||||
sys_info_t sysinfo;
|
|
||||||
unsigned long div; /* total divisor udiv * bdiv */
|
|
||||||
unsigned long umin; /* minimum udiv */
|
|
||||||
unsigned short diff; /* smallest diff */
|
|
||||||
unsigned long udiv; /* best udiv */
|
|
||||||
unsigned short idiff; /* current diff */
|
|
||||||
unsigned short ibdiv; /* current bdiv */
|
|
||||||
unsigned long i;
|
|
||||||
unsigned long est; /* current estimate */
|
|
||||||
unsigned long plloutb;
|
|
||||||
unsigned long cpr_pllc;
|
|
||||||
u32 reg;
|
|
||||||
|
|
||||||
/* check the pll feedback source */
|
/* check the pll feedback source */
|
||||||
mfcpr(CPR0_PLLC, cpr_pllc);
|
mfcpr(CPR0_PLLC, cpr_pllc);
|
||||||
|
|
||||||
get_sys_info(&sysinfo);
|
|
||||||
|
|
||||||
plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ?
|
plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ?
|
||||||
sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) *
|
sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) *
|
||||||
sysinfo.pllFbkDiv) / sysinfo.pllFwdDivB);
|
sysinfo.pllFbkDiv) / sysinfo.pllFwdDivB);
|
||||||
udiv = 256; /* Assume lowest possible serial clk */
|
|
||||||
div = plloutb / (16 * baudrate); /* total divisor */
|
div = plloutb / (16 * baudrate); /* total divisor */
|
||||||
umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */
|
umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */
|
||||||
diff = 256; /* highest possible */
|
max = 256; /* highest possible */
|
||||||
|
#else /* 405EZ */
|
||||||
|
div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */
|
||||||
|
umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */
|
||||||
|
max = 32; /* highest possible */
|
||||||
|
#endif /* 405EZ */
|
||||||
|
|
||||||
/* i is the test udiv value -- start with the largest
|
*udiv = diff = max;
|
||||||
* possible (256) to minimize serial clock and constrain
|
|
||||||
|
/*
|
||||||
|
* i is the test udiv value -- start with the largest
|
||||||
|
* possible (max) to minimize serial clock and constrain
|
||||||
* search to umin.
|
* search to umin.
|
||||||
*/
|
*/
|
||||||
for (i = 256; i > umin; i--) {
|
for (i = max; i > umin; i--) {
|
||||||
ibdiv = div / i;
|
ibdiv = div / i;
|
||||||
est = i * ibdiv;
|
est = i * ibdiv;
|
||||||
idiff = (est > div) ? (est - div) : (div - est);
|
idiff = (est > div) ? (est - div) : (div - est);
|
||||||
if (idiff == 0) {
|
if (idiff == 0) {
|
||||||
udiv = i;
|
*udiv = i;
|
||||||
break; /* can't do better */
|
break; /* can't do better */
|
||||||
} else if (idiff < diff) {
|
} else if (idiff < diff) {
|
||||||
udiv = i; /* best so far */
|
*udiv = i; /* best so far */
|
||||||
diff = idiff; /* update lowest diff*/
|
diff = idiff; /* update lowest diff*/
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
*pudiv = udiv;
|
#if defined(CONFIG_405EZ)
|
||||||
mfcpr(CPC0_PERD0, reg);
|
mfcpr(CPR0_PERD0, reg);
|
||||||
reg &= ~0x0000ffff;
|
reg &= ~0x0000ffff;
|
||||||
reg |= ((udiv - 0) << 8) | (udiv - 0);
|
reg |= ((*udiv - 0) << 8) | (*udiv - 0);
|
||||||
mtcpr(CPC0_PERD0, reg);
|
mtcpr(CPR0_PERD0, reg);
|
||||||
*pbdiv = div / udiv;
|
|
||||||
}
|
|
||||||
#endif /* defined(CONFIG_440) && !defined(CONFIG_SYS_EXT_SERIAL_CLK) */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Minimal serial functions needed to use one of the SMC ports
|
|
||||||
* as serial console interface.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#if defined(CONFIG_440)
|
|
||||||
int serial_init_dev(unsigned long base)
|
|
||||||
{
|
|
||||||
unsigned long reg;
|
|
||||||
unsigned long udiv;
|
|
||||||
unsigned short bdiv;
|
|
||||||
#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
|
|
||||||
unsigned long tmp;
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
return div / *udiv;
|
||||||
|
}
|
||||||
|
#endif /* #if (defined(CONFIG_405EP) ... */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This function returns the UART clock used by the common
|
||||||
|
* NS16550 driver. Additionally the SoC internal divisors for
|
||||||
|
* optimal UART baudrate are configured.
|
||||||
|
*/
|
||||||
|
int get_serial_clock(void)
|
||||||
|
{
|
||||||
|
u32 clk;
|
||||||
|
u32 udiv;
|
||||||
|
#if defined(CONFIG_405CR) || defined(CONFIG_405EP) || defined(CONFIG_405GP)
|
||||||
|
u32 tmp;
|
||||||
|
#endif
|
||||||
|
#if !defined(CONFIG_405EZ)
|
||||||
|
u32 reg;
|
||||||
|
#endif
|
||||||
|
#if !defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
|
||||||
|
PPC4xx_SYS_INFO sys_info;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Programming of the internal divisors is SoC specific.
|
||||||
|
* Let's handle this in some #ifdef's for the SoC's.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined(CONFIG_405CR) || defined(CONFIG_405GP)
|
||||||
|
tmp = 0;
|
||||||
|
reg = mfdcr(CPC0_CR0) & ~CR0_MASK;
|
||||||
|
#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
|
||||||
|
clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
|
||||||
|
udiv = 1;
|
||||||
|
reg |= CR0_EXTCLK_ENA;
|
||||||
|
#else /* CONFIG_SYS_EXT_SERIAL_CLOCK */
|
||||||
|
clk = gd->cpu_clk;
|
||||||
|
#ifdef CONFIG_SYS_405_UART_ERRATA_59
|
||||||
|
udiv = 31; /* Errata 59: stuck at 31 */
|
||||||
|
#else /* CONFIG_SYS_405_UART_ERRATA_59 */
|
||||||
|
tmp = CONFIG_SYS_BASE_BAUD * 16;
|
||||||
|
udiv = (clk + tmp / 2) / tmp;
|
||||||
|
if (udiv > UDIV_MAX) /* max. n bits for udiv */
|
||||||
|
udiv = UDIV_MAX;
|
||||||
|
#endif /* CONFIG_SYS_405_UART_ERRATA_59 */
|
||||||
|
#endif /* CONFIG_SYS_EXT_SERIAL_CLOCK */
|
||||||
|
reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
|
||||||
|
mtdcr (CPC0_CR0, reg);
|
||||||
|
#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
|
||||||
|
clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
|
||||||
|
#else
|
||||||
|
clk = CONFIG_SYS_BASE_BAUD * 16;
|
||||||
|
#endif
|
||||||
|
#endif /* CONFIG_405CR */
|
||||||
|
|
||||||
|
#if defined(CONFIG_405EP)
|
||||||
|
reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK);
|
||||||
|
clk = gd->cpu_clk;
|
||||||
|
tmp = CONFIG_SYS_BASE_BAUD * 16;
|
||||||
|
udiv = (clk + tmp / 2) / tmp;
|
||||||
|
if (udiv > UDIV_MAX) /* max. n bits for udiv */
|
||||||
|
udiv = UDIV_MAX;
|
||||||
|
reg |= udiv << UCR0_UDIV_POS; /* set the UART divisor */
|
||||||
|
reg |= udiv << UCR1_UDIV_POS; /* set the UART divisor */
|
||||||
|
mtdcr(CPC0_UCR, reg);
|
||||||
|
clk = CONFIG_SYS_BASE_BAUD * 16;
|
||||||
|
#endif /* CONFIG_405EP */
|
||||||
|
|
||||||
|
#if defined(CONFIG_405EX) || defined(CONFIG_440)
|
||||||
MFREG(UART0_SDR, reg);
|
MFREG(UART0_SDR, reg);
|
||||||
reg &= ~CR0_MASK;
|
reg &= ~CR0_MASK;
|
||||||
|
|
||||||
#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
|
#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
|
||||||
reg |= CR0_EXTCLK_ENA;
|
reg |= CR0_EXTCLK_ENA;
|
||||||
udiv = 1;
|
udiv = 1;
|
||||||
tmp = gd->baudrate * 16;
|
clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
|
||||||
bdiv = (CONFIG_SYS_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
|
#else /* CONFIG_SYS_EXT_SERIAL_CLOCK */
|
||||||
#else
|
clk = gd->baudrate * serial_bdiv(gd->baudrate, &udiv) * 16;
|
||||||
/* For 440, the cpu clock is on divider chain A, UART on divider
|
#endif /* CONFIG_SYS_EXT_SERIAL_CLOCK */
|
||||||
* chain B ... so cpu clock is irrelevant. Get the "optimized"
|
|
||||||
* values that are subject to the 1/2 opb clock constraint
|
|
||||||
*/
|
|
||||||
serial_divs (gd->baudrate, &udiv, &bdiv);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
|
reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
|
||||||
|
|
||||||
@ -367,514 +283,23 @@ int serial_init_dev(unsigned long base)
|
|||||||
#if defined(UART3_SDR)
|
#if defined(UART3_SDR)
|
||||||
MTREG(UART3_SDR, reg);
|
MTREG(UART3_SDR, reg);
|
||||||
#endif
|
#endif
|
||||||
|
#endif /* CONFIG_405EX ... */
|
||||||
|
|
||||||
serial_init_common(base, udiv, bdiv);
|
#if defined(CONFIG_405EZ)
|
||||||
|
clk = gd->baudrate * serial_bdiv(gd->baudrate, &udiv) * 16;
|
||||||
|
#endif /* CONFIG_405EZ */
|
||||||
|
|
||||||
return (0);
|
/*
|
||||||
}
|
* Correct UART frequency in bd-info struct now that
|
||||||
|
* the UART divisor is available
|
||||||
#else /* !defined(CONFIG_440) */
|
*/
|
||||||
|
|
||||||
int serial_init_dev (unsigned long base)
|
|
||||||
{
|
|
||||||
unsigned long reg;
|
|
||||||
unsigned long tmp;
|
|
||||||
unsigned long clk;
|
|
||||||
unsigned long udiv;
|
|
||||||
unsigned short bdiv;
|
|
||||||
|
|
||||||
#ifdef CONFIG_405EX
|
|
||||||
clk = tmp = 0;
|
|
||||||
mfsdr(UART0_SDR, reg);
|
|
||||||
reg &= ~CR0_MASK;
|
|
||||||
#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
|
#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
|
||||||
reg |= CR0_EXTCLK_ENA;
|
gd->uart_clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
|
||||||
udiv = 1;
|
|
||||||
tmp = gd->baudrate * 16;
|
|
||||||
bdiv = (CONFIG_SYS_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
|
|
||||||
#else
|
#else
|
||||||
serial_divs(gd->baudrate, &udiv, &bdiv);
|
get_sys_info(&sys_info);
|
||||||
#endif
|
gd->uart_clk = sys_info.freqUART / udiv;
|
||||||
reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Configure input clock to baudrate generator for all
|
|
||||||
* available serial ports here
|
|
||||||
*/
|
|
||||||
mtsdr(UART0_SDR, reg);
|
|
||||||
|
|
||||||
#if defined(UART1_SDR)
|
|
||||||
mtsdr(UART1_SDR, reg);
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#elif defined(CONFIG_405EZ)
|
return clk;
|
||||||
serial_divs(gd->baudrate, &udiv, &bdiv);
|
|
||||||
clk = tmp = reg = 0;
|
|
||||||
#else
|
|
||||||
#ifdef CONFIG_405EP
|
|
||||||
reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK);
|
|
||||||
clk = gd->cpu_clk;
|
|
||||||
tmp = CONFIG_SYS_BASE_BAUD * 16;
|
|
||||||
udiv = (clk + tmp / 2) / tmp;
|
|
||||||
if (udiv > UDIV_MAX) /* max. n bits for udiv */
|
|
||||||
udiv = UDIV_MAX;
|
|
||||||
reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
|
|
||||||
reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
|
|
||||||
mtdcr (CPC0_UCR, reg);
|
|
||||||
#else /* CONFIG_405EP */
|
|
||||||
reg = mfdcr(CPC0_CR0) & ~CR0_MASK;
|
|
||||||
#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
|
|
||||||
clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
|
|
||||||
udiv = 1;
|
|
||||||
reg |= CR0_EXTCLK_ENA;
|
|
||||||
#else
|
|
||||||
clk = gd->cpu_clk;
|
|
||||||
#ifdef CONFIG_SYS_405_UART_ERRATA_59
|
|
||||||
udiv = 31; /* Errata 59: stuck at 31 */
|
|
||||||
#else
|
|
||||||
tmp = CONFIG_SYS_BASE_BAUD * 16;
|
|
||||||
udiv = (clk + tmp / 2) / tmp;
|
|
||||||
if (udiv > UDIV_MAX) /* max. n bits for udiv */
|
|
||||||
udiv = UDIV_MAX;
|
|
||||||
#endif
|
|
||||||
#endif
|
|
||||||
reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
|
|
||||||
mtdcr (CPC0_CR0, reg);
|
|
||||||
#endif /* CONFIG_405EP */
|
|
||||||
tmp = gd->baudrate * udiv * 16;
|
|
||||||
bdiv = (clk + tmp / 2) / tmp;
|
|
||||||
#endif /* CONFIG_405EX */
|
|
||||||
|
|
||||||
serial_init_common(base, udiv, bdiv);
|
|
||||||
|
|
||||||
return (0);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* if defined(CONFIG_440) */
|
|
||||||
|
|
||||||
void serial_setbrg_dev(unsigned long base)
|
|
||||||
{
|
|
||||||
serial_init_dev(base);
|
|
||||||
}
|
|
||||||
|
|
||||||
void serial_putc_dev(unsigned long base, const char c)
|
|
||||||
{
|
|
||||||
int i;
|
|
||||||
|
|
||||||
if (c == '\n')
|
|
||||||
serial_putc_dev(base, '\r');
|
|
||||||
|
|
||||||
/* check THRE bit, wait for transmiter available */
|
|
||||||
for (i = 1; i < 3500; i++) {
|
|
||||||
if ((in_8((u8 *)base + UART_LSR) & 0x20) == 0x20)
|
|
||||||
break;
|
|
||||||
udelay (100);
|
|
||||||
}
|
|
||||||
|
|
||||||
out_8((u8 *)base + UART_THR, c); /* put character out */
|
|
||||||
}
|
|
||||||
|
|
||||||
void serial_puts_dev (unsigned long base, const char *s)
|
|
||||||
{
|
|
||||||
while (*s)
|
|
||||||
serial_putc_dev (base, *s++);
|
|
||||||
}
|
|
||||||
|
|
||||||
int serial_getc_dev (unsigned long base)
|
|
||||||
{
|
|
||||||
unsigned char status = 0;
|
|
||||||
|
|
||||||
while (1) {
|
|
||||||
#if defined(CONFIG_HW_WATCHDOG)
|
|
||||||
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
|
|
||||||
#endif /* CONFIG_HW_WATCHDOG */
|
|
||||||
|
|
||||||
status = in_8((u8 *)base + UART_LSR);
|
|
||||||
if ((status & asyncLSRDataReady1) != 0x0)
|
|
||||||
break;
|
|
||||||
|
|
||||||
if ((status & ( asyncLSRFramingError1 |
|
|
||||||
asyncLSROverrunError1 |
|
|
||||||
asyncLSRParityError1 |
|
|
||||||
asyncLSRBreakInterrupt1 )) != 0) {
|
|
||||||
out_8((u8 *)base + UART_LSR,
|
|
||||||
asyncLSRFramingError1 |
|
|
||||||
asyncLSROverrunError1 |
|
|
||||||
asyncLSRParityError1 |
|
|
||||||
asyncLSRBreakInterrupt1);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
return (0x000000ff & (int) in_8((u8 *)base));
|
|
||||||
}
|
|
||||||
|
|
||||||
int serial_tstc_dev (unsigned long base)
|
|
||||||
{
|
|
||||||
unsigned char status;
|
|
||||||
|
|
||||||
status = in_8((u8 *)base + UART_LSR);
|
|
||||||
if ((status & asyncLSRDataReady1) != 0x0)
|
|
||||||
return (1);
|
|
||||||
|
|
||||||
if ((status & ( asyncLSRFramingError1 |
|
|
||||||
asyncLSROverrunError1 |
|
|
||||||
asyncLSRParityError1 |
|
|
||||||
asyncLSRBreakInterrupt1 )) != 0) {
|
|
||||||
out_8((u8 *)base + UART_LSR,
|
|
||||||
asyncLSRFramingError1 |
|
|
||||||
asyncLSROverrunError1 |
|
|
||||||
asyncLSRParityError1 |
|
|
||||||
asyncLSRBreakInterrupt1);
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
|
|
||||||
|
|
||||||
void serial_isr (void *arg)
|
|
||||||
{
|
|
||||||
int space;
|
|
||||||
int c;
|
|
||||||
const int rx_get = buf_info.rx_get;
|
|
||||||
int rx_put = buf_info.rx_put;
|
|
||||||
|
|
||||||
if (rx_get <= rx_put)
|
|
||||||
space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
|
|
||||||
else
|
|
||||||
space = rx_get - rx_put;
|
|
||||||
|
|
||||||
while (serial_tstc_dev (ACTING_UART0_BASE)) {
|
|
||||||
c = serial_getc_dev (ACTING_UART0_BASE);
|
|
||||||
if (space) {
|
|
||||||
buf_info.rx_buffer[rx_put++] = c;
|
|
||||||
space--;
|
|
||||||
}
|
|
||||||
if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO)
|
|
||||||
rx_put = 0;
|
|
||||||
if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
|
|
||||||
/* Stop flow by setting RTS inactive */
|
|
||||||
out_8((u8 *)ACTING_UART0_BASE + UART_MCR,
|
|
||||||
in_8((u8 *)ACTING_UART0_BASE + UART_MCR) &
|
|
||||||
(0xFF ^ 0x02));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
buf_info.rx_put = rx_put;
|
|
||||||
}
|
|
||||||
|
|
||||||
void serial_buffered_init (void)
|
|
||||||
{
|
|
||||||
serial_puts ("Switching to interrupt driven serial input mode.\n");
|
|
||||||
buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO);
|
|
||||||
buf_info.rx_put = 0;
|
|
||||||
buf_info.rx_get = 0;
|
|
||||||
|
|
||||||
if (in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10)
|
|
||||||
serial_puts ("Check CTS signal present on serial port: OK.\n");
|
|
||||||
else
|
|
||||||
serial_puts ("WARNING: CTS signal not present on serial port.\n");
|
|
||||||
|
|
||||||
irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ ,
|
|
||||||
serial_isr /*interrupt_handler_t *handler */ ,
|
|
||||||
(void *) &buf_info /*void *arg */ );
|
|
||||||
|
|
||||||
/* Enable "RX Data Available" Interrupt on UART */
|
|
||||||
out_8(ACTING_UART0_BASE + UART_IER, 0x01);
|
|
||||||
/* Set DTR active */
|
|
||||||
out_8(ACTING_UART0_BASE + UART_MCR,
|
|
||||||
in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x01);
|
|
||||||
/* Start flow by setting RTS active */
|
|
||||||
out_8(ACTING_UART0_BASE + UART_MCR,
|
|
||||||
in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x02);
|
|
||||||
/* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */
|
|
||||||
out_8(ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1);
|
|
||||||
}
|
|
||||||
|
|
||||||
void serial_buffered_putc (const char c)
|
|
||||||
{
|
|
||||||
/* Wait for CTS */
|
|
||||||
#if defined(CONFIG_HW_WATCHDOG)
|
|
||||||
while (!(in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10))
|
|
||||||
WATCHDOG_RESET ();
|
|
||||||
#else
|
|
||||||
while (!(in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10));
|
|
||||||
#endif
|
|
||||||
serial_putc (c);
|
|
||||||
}
|
|
||||||
|
|
||||||
void serial_buffered_puts (const char *s)
|
|
||||||
{
|
|
||||||
serial_puts (s);
|
|
||||||
}
|
|
||||||
|
|
||||||
int serial_buffered_getc (void)
|
|
||||||
{
|
|
||||||
int space;
|
|
||||||
int c;
|
|
||||||
int rx_get = buf_info.rx_get;
|
|
||||||
int rx_put;
|
|
||||||
|
|
||||||
#if defined(CONFIG_HW_WATCHDOG)
|
|
||||||
while (rx_get == buf_info.rx_put)
|
|
||||||
WATCHDOG_RESET ();
|
|
||||||
#else
|
|
||||||
while (rx_get == buf_info.rx_put);
|
|
||||||
#endif
|
|
||||||
c = buf_info.rx_buffer[rx_get++];
|
|
||||||
if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO)
|
|
||||||
rx_get = 0;
|
|
||||||
buf_info.rx_get = rx_get;
|
|
||||||
|
|
||||||
rx_put = buf_info.rx_put;
|
|
||||||
if (rx_get <= rx_put)
|
|
||||||
space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
|
|
||||||
else
|
|
||||||
space = rx_get - rx_put;
|
|
||||||
|
|
||||||
if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) {
|
|
||||||
/* Start flow by setting RTS active */
|
|
||||||
out_8(ACTING_UART0_BASE + UART_MCR,
|
|
||||||
in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x02);
|
|
||||||
}
|
|
||||||
|
|
||||||
return c;
|
|
||||||
}
|
|
||||||
|
|
||||||
int serial_buffered_tstc (void)
|
|
||||||
{
|
|
||||||
return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */
|
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_KGDB)
|
|
||||||
/*
|
|
||||||
AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port
|
|
||||||
number 0 or number 1
|
|
||||||
- if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 :
|
|
||||||
configuration has been already done
|
|
||||||
- if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 :
|
|
||||||
configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE
|
|
||||||
*/
|
|
||||||
#if (CONFIG_KGDB_SER_INDEX & 2)
|
|
||||||
void kgdb_serial_init (void)
|
|
||||||
{
|
|
||||||
u8 val;
|
|
||||||
u16 br_reg;
|
|
||||||
|
|
||||||
get_clocks ();
|
|
||||||
br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) +
|
|
||||||
5) / 10;
|
|
||||||
/*
|
|
||||||
* Init onboard 16550 UART
|
|
||||||
*/
|
|
||||||
out_8((u8 *)ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */
|
|
||||||
out_8((u8 *)ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */
|
|
||||||
out_8((u8 *)ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */
|
|
||||||
out_8((u8 *)ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */
|
|
||||||
out_8((u8 *)ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */
|
|
||||||
out_8((u8 *)ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
|
|
||||||
val = in_8((u8 *)ACTING_UART1_BASE + UART_LSR); /* clear line status */
|
|
||||||
val = in_8((u8 *)ACTING_UART1_BASE + UART_RBR); /* read receive buffer */
|
|
||||||
out_8((u8 *)ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */
|
|
||||||
out_8((u8 *)ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */
|
|
||||||
}
|
|
||||||
|
|
||||||
void putDebugChar (const char c)
|
|
||||||
{
|
|
||||||
if (c == '\n')
|
|
||||||
serial_putc ('\r');
|
|
||||||
|
|
||||||
out_8((u8 *)ACTING_UART1_BASE + UART_THR, c); /* put character out */
|
|
||||||
|
|
||||||
/* check THRE bit, wait for transfer done */
|
|
||||||
while ((in_8((u8 *)ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20);
|
|
||||||
}
|
|
||||||
|
|
||||||
void putDebugStr (const char *s)
|
|
||||||
{
|
|
||||||
while (*s)
|
|
||||||
serial_putc (*s++);
|
|
||||||
}
|
|
||||||
|
|
||||||
int getDebugChar (void)
|
|
||||||
{
|
|
||||||
unsigned char status = 0;
|
|
||||||
|
|
||||||
while (1) {
|
|
||||||
status = in_8((u8 *)ACTING_UART1_BASE + UART_LSR);
|
|
||||||
if ((status & asyncLSRDataReady1) != 0x0)
|
|
||||||
break;
|
|
||||||
|
|
||||||
if ((status & (asyncLSRFramingError1 |
|
|
||||||
asyncLSROverrunError1 |
|
|
||||||
asyncLSRParityError1 |
|
|
||||||
asyncLSRBreakInterrupt1 )) != 0) {
|
|
||||||
out_8((u8 *)ACTING_UART1_BASE + UART_LSR,
|
|
||||||
asyncLSRFramingError1 |
|
|
||||||
asyncLSROverrunError1 |
|
|
||||||
asyncLSRParityError1 |
|
|
||||||
asyncLSRBreakInterrupt1);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
return (0x000000ff & (int) in_8((u8 *)ACTING_UART1_BASE));
|
|
||||||
}
|
|
||||||
|
|
||||||
void kgdb_interruptible (int yes)
|
|
||||||
{
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
#else /* ! (CONFIG_KGDB_SER_INDEX & 2) */
|
|
||||||
|
|
||||||
void kgdb_serial_init (void)
|
|
||||||
{
|
|
||||||
serial_printf ("[on serial] ");
|
|
||||||
}
|
|
||||||
|
|
||||||
void putDebugChar (int c)
|
|
||||||
{
|
|
||||||
serial_putc (c);
|
|
||||||
}
|
|
||||||
|
|
||||||
void putDebugStr (const char *str)
|
|
||||||
{
|
|
||||||
serial_puts (str);
|
|
||||||
}
|
|
||||||
|
|
||||||
int getDebugChar (void)
|
|
||||||
{
|
|
||||||
return serial_getc ();
|
|
||||||
}
|
|
||||||
|
|
||||||
void kgdb_interruptible (int yes)
|
|
||||||
{
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
#endif /* (CONFIG_KGDB_SER_INDEX & 2) */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
#if defined(CONFIG_SERIAL_MULTI)
|
|
||||||
int serial0_init(void)
|
|
||||||
{
|
|
||||||
return (serial_init_dev(UART0_BASE));
|
|
||||||
}
|
|
||||||
|
|
||||||
int serial1_init(void)
|
|
||||||
{
|
|
||||||
return (serial_init_dev(UART1_BASE));
|
|
||||||
}
|
|
||||||
|
|
||||||
void serial0_setbrg (void)
|
|
||||||
{
|
|
||||||
serial_setbrg_dev(UART0_BASE);
|
|
||||||
}
|
|
||||||
|
|
||||||
void serial1_setbrg (void)
|
|
||||||
{
|
|
||||||
serial_setbrg_dev(UART1_BASE);
|
|
||||||
}
|
|
||||||
|
|
||||||
void serial0_putc(const char c)
|
|
||||||
{
|
|
||||||
serial_putc_dev(UART0_BASE,c);
|
|
||||||
}
|
|
||||||
|
|
||||||
void serial1_putc(const char c)
|
|
||||||
{
|
|
||||||
serial_putc_dev(UART1_BASE, c);
|
|
||||||
}
|
|
||||||
|
|
||||||
void serial0_puts(const char *s)
|
|
||||||
{
|
|
||||||
serial_puts_dev(UART0_BASE, s);
|
|
||||||
}
|
|
||||||
|
|
||||||
void serial1_puts(const char *s)
|
|
||||||
{
|
|
||||||
serial_puts_dev(UART1_BASE, s);
|
|
||||||
}
|
|
||||||
|
|
||||||
int serial0_getc(void)
|
|
||||||
{
|
|
||||||
return(serial_getc_dev(UART0_BASE));
|
|
||||||
}
|
|
||||||
|
|
||||||
int serial1_getc(void)
|
|
||||||
{
|
|
||||||
return(serial_getc_dev(UART1_BASE));
|
|
||||||
}
|
|
||||||
|
|
||||||
int serial0_tstc(void)
|
|
||||||
{
|
|
||||||
return (serial_tstc_dev(UART0_BASE));
|
|
||||||
}
|
|
||||||
|
|
||||||
int serial1_tstc(void)
|
|
||||||
{
|
|
||||||
return (serial_tstc_dev(UART1_BASE));
|
|
||||||
}
|
|
||||||
|
|
||||||
struct serial_device serial0_device =
|
|
||||||
{
|
|
||||||
"serial0",
|
|
||||||
"UART0",
|
|
||||||
serial0_init,
|
|
||||||
NULL,
|
|
||||||
serial0_setbrg,
|
|
||||||
serial0_getc,
|
|
||||||
serial0_tstc,
|
|
||||||
serial0_putc,
|
|
||||||
serial0_puts,
|
|
||||||
};
|
|
||||||
|
|
||||||
struct serial_device serial1_device =
|
|
||||||
{
|
|
||||||
"serial1",
|
|
||||||
"UART1",
|
|
||||||
serial1_init,
|
|
||||||
NULL,
|
|
||||||
serial1_setbrg,
|
|
||||||
serial1_getc,
|
|
||||||
serial1_tstc,
|
|
||||||
serial1_putc,
|
|
||||||
serial1_puts,
|
|
||||||
};
|
|
||||||
#else
|
|
||||||
/*
|
|
||||||
* Wrapper functions
|
|
||||||
*/
|
|
||||||
int serial_init(void)
|
|
||||||
{
|
|
||||||
return serial_init_dev(ACTING_UART0_BASE);
|
|
||||||
}
|
|
||||||
|
|
||||||
void serial_setbrg(void)
|
|
||||||
{
|
|
||||||
serial_setbrg_dev(ACTING_UART0_BASE);
|
|
||||||
}
|
|
||||||
|
|
||||||
void serial_putc(const char c)
|
|
||||||
{
|
|
||||||
serial_putc_dev(ACTING_UART0_BASE, c);
|
|
||||||
}
|
|
||||||
|
|
||||||
void serial_puts(const char *s)
|
|
||||||
{
|
|
||||||
serial_puts_dev(ACTING_UART0_BASE, s);
|
|
||||||
}
|
|
||||||
|
|
||||||
int serial_getc(void)
|
|
||||||
{
|
|
||||||
return serial_getc_dev(ACTING_UART0_BASE);
|
|
||||||
}
|
|
||||||
|
|
||||||
int serial_tstc(void)
|
|
||||||
{
|
|
||||||
return serial_tstc_dev(ACTING_UART0_BASE);
|
|
||||||
}
|
|
||||||
#endif /* CONFIG_SERIAL_MULTI */
|
|
||||||
|
|
||||||
#endif /* CONFIG_405GP || CONFIG_405CR */
|
#endif /* CONFIG_405GP || CONFIG_405CR */
|
||||||
|
@ -14,7 +14,7 @@
|
|||||||
|
|
||||||
#include <config.h>
|
#include <config.h>
|
||||||
#include <config.h>
|
#include <config.h>
|
||||||
#include <ppc4xx.h>
|
#include <asm/ppc4xx.h>
|
||||||
#include <ppc_asm.tmpl>
|
#include <ppc_asm.tmpl>
|
||||||
#include <ppc_defs.h>
|
#include <ppc_defs.h>
|
||||||
#include <asm/cache.h>
|
#include <asm/cache.h>
|
||||||
|
@ -23,7 +23,7 @@
|
|||||||
*/
|
*/
|
||||||
|
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <ppc4xx.h>
|
#include <asm/ppc4xx.h>
|
||||||
#include <asm/processor.h>
|
#include <asm/processor.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <asm/cache.h>
|
#include <asm/cache.h>
|
||||||
|
@ -35,7 +35,7 @@
|
|||||||
#include <watchdog.h>
|
#include <watchdog.h>
|
||||||
#include <command.h>
|
#include <command.h>
|
||||||
#include <asm/cache.h>
|
#include <asm/cache.h>
|
||||||
#include <ppc4xx.h>
|
#include <asm/ppc4xx.h>
|
||||||
#include <netdev.h>
|
#include <netdev.h>
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
@ -98,8 +98,8 @@ int pci_arbiter_enabled(void)
|
|||||||
#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
|
#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
|
||||||
unsigned long val;
|
unsigned long val;
|
||||||
|
|
||||||
mfsdr(SDR0_XCR, val);
|
mfsdr(SDR0_XCR0, val);
|
||||||
return (val & 0x80000000);
|
return (val & SDR0_XCR0_PAE_MASK);
|
||||||
#endif
|
#endif
|
||||||
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
|
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
|
||||||
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
|
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
|
||||||
@ -107,7 +107,7 @@ int pci_arbiter_enabled(void)
|
|||||||
unsigned long val;
|
unsigned long val;
|
||||||
|
|
||||||
mfsdr(SDR0_PCI0, val);
|
mfsdr(SDR0_PCI0, val);
|
||||||
return (val & 0x80000000);
|
return (val & SDR0_PCI0_PAE_MASK);
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
@ -262,7 +262,7 @@ static int bootstrap_option(void)
|
|||||||
#endif /* SDR0_PINSTP_SHIFT */
|
#endif /* SDR0_PINSTP_SHIFT */
|
||||||
|
|
||||||
|
|
||||||
#if defined(CONFIG_440)
|
#if defined(CONFIG_440GP)
|
||||||
static int do_chip_reset (unsigned long sys0, unsigned long sys1)
|
static int do_chip_reset (unsigned long sys0, unsigned long sys1)
|
||||||
{
|
{
|
||||||
/* Changes to CPC0_SYS0 and CPC0_SYS1 require chip
|
/* Changes to CPC0_SYS0 and CPC0_SYS1 require chip
|
||||||
@ -276,7 +276,7 @@ static int do_chip_reset (unsigned long sys0, unsigned long sys1)
|
|||||||
|
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
#endif
|
#endif /* CONFIG_440GP */
|
||||||
|
|
||||||
|
|
||||||
int checkcpu (void)
|
int checkcpu (void)
|
||||||
@ -303,122 +303,113 @@ int checkcpu (void)
|
|||||||
get_sys_info(&sys_info);
|
get_sys_info(&sys_info);
|
||||||
|
|
||||||
#if defined(CONFIG_XILINX_440)
|
#if defined(CONFIG_XILINX_440)
|
||||||
puts("IBM PowerPC 4");
|
puts("IBM PowerPC ");
|
||||||
#else
|
#else
|
||||||
puts("AMCC PowerPC 4");
|
puts("AMCC PowerPC ");
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
|
|
||||||
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
|
|
||||||
defined(CONFIG_405EX)
|
|
||||||
puts("05");
|
|
||||||
#endif
|
|
||||||
#if defined(CONFIG_440)
|
|
||||||
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
|
|
||||||
puts("60");
|
|
||||||
#else
|
|
||||||
puts("40");
|
|
||||||
#endif
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
switch (pvr) {
|
switch (pvr) {
|
||||||
|
|
||||||
|
#if !defined(CONFIG_440)
|
||||||
case PVR_405GP_RB:
|
case PVR_405GP_RB:
|
||||||
puts("GP Rev. B");
|
puts("405GP Rev. B");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_405GP_RC:
|
case PVR_405GP_RC:
|
||||||
puts("GP Rev. C");
|
puts("405GP Rev. C");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_405GP_RD:
|
case PVR_405GP_RD:
|
||||||
puts("GP Rev. D");
|
puts("405GP Rev. D");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
#ifdef CONFIG_405GP
|
#ifdef CONFIG_405GP
|
||||||
case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
|
case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
|
||||||
puts("GP Rev. E");
|
puts("405GP Rev. E");
|
||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
case PVR_405CR_RA:
|
case PVR_405CR_RA:
|
||||||
puts("CR Rev. A");
|
puts("405CR Rev. A");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_405CR_RB:
|
case PVR_405CR_RB:
|
||||||
puts("CR Rev. B");
|
puts("405CR Rev. B");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
#ifdef CONFIG_405CR
|
#ifdef CONFIG_405CR
|
||||||
case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
|
case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
|
||||||
puts("CR Rev. C");
|
puts("405CR Rev. C");
|
||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
case PVR_405GPR_RB:
|
case PVR_405GPR_RB:
|
||||||
puts("GPr Rev. B");
|
puts("405GPr Rev. B");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_405EP_RB:
|
case PVR_405EP_RB:
|
||||||
puts("EP Rev. B");
|
puts("405EP Rev. B");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_405EZ_RA:
|
case PVR_405EZ_RA:
|
||||||
puts("EZ Rev. A");
|
puts("405EZ Rev. A");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_405EX1_RA:
|
case PVR_405EX1_RA:
|
||||||
puts("EX Rev. A");
|
puts("405EX Rev. A");
|
||||||
strcpy(addstr, "Security support");
|
strcpy(addstr, "Security support");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_405EXR2_RA:
|
case PVR_405EXR2_RA:
|
||||||
puts("EXr Rev. A");
|
puts("405EXr Rev. A");
|
||||||
strcpy(addstr, "No Security support");
|
strcpy(addstr, "No Security support");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_405EX1_RC:
|
case PVR_405EX1_RC:
|
||||||
puts("EX Rev. C");
|
puts("405EX Rev. C");
|
||||||
strcpy(addstr, "Security support");
|
strcpy(addstr, "Security support");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_405EX2_RC:
|
case PVR_405EX2_RC:
|
||||||
puts("EX Rev. C");
|
puts("405EX Rev. C");
|
||||||
strcpy(addstr, "No Security support");
|
strcpy(addstr, "No Security support");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_405EXR1_RC:
|
case PVR_405EXR1_RC:
|
||||||
puts("EXr Rev. C");
|
puts("405EXr Rev. C");
|
||||||
strcpy(addstr, "Security support");
|
strcpy(addstr, "Security support");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_405EXR2_RC:
|
case PVR_405EXR2_RC:
|
||||||
puts("EXr Rev. C");
|
puts("405EXr Rev. C");
|
||||||
strcpy(addstr, "No Security support");
|
strcpy(addstr, "No Security support");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_405EX1_RD:
|
case PVR_405EX1_RD:
|
||||||
puts("EX Rev. D");
|
puts("405EX Rev. D");
|
||||||
strcpy(addstr, "Security support");
|
strcpy(addstr, "Security support");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_405EX2_RD:
|
case PVR_405EX2_RD:
|
||||||
puts("EX Rev. D");
|
puts("405EX Rev. D");
|
||||||
strcpy(addstr, "No Security support");
|
strcpy(addstr, "No Security support");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_405EXR1_RD:
|
case PVR_405EXR1_RD:
|
||||||
puts("EXr Rev. D");
|
puts("405EXr Rev. D");
|
||||||
strcpy(addstr, "Security support");
|
strcpy(addstr, "Security support");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_405EXR2_RD:
|
case PVR_405EXR2_RD:
|
||||||
puts("EXr Rev. D");
|
puts("405EXr Rev. D");
|
||||||
strcpy(addstr, "No Security support");
|
strcpy(addstr, "No Security support");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
#if defined(CONFIG_440)
|
#else /* CONFIG_440 */
|
||||||
|
|
||||||
|
#if defined(CONFIG_440GP)
|
||||||
case PVR_440GP_RB:
|
case PVR_440GP_RB:
|
||||||
puts("GP Rev. B");
|
puts("440GP Rev. B");
|
||||||
/* See errata 1.12: CHIP_4 */
|
/* See errata 1.12: CHIP_4 */
|
||||||
if ((mfdcr(CPC0_SYS0) != mfdcr(CPC0_STRP0)) ||
|
if ((mfdcr(CPC0_SYS0) != mfdcr(CPC0_STRP0)) ||
|
||||||
(mfdcr(CPC0_SYS1) != mfdcr(CPC0_STRP1)) ){
|
(mfdcr(CPC0_SYS1) != mfdcr(CPC0_STRP1)) ){
|
||||||
@ -431,127 +422,127 @@ int checkcpu (void)
|
|||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_440GP_RC:
|
case PVR_440GP_RC:
|
||||||
puts("GP Rev. C");
|
puts("440GP Rev. C");
|
||||||
break;
|
break;
|
||||||
|
#endif /* CONFIG_440GP */
|
||||||
|
|
||||||
case PVR_440GX_RA:
|
case PVR_440GX_RA:
|
||||||
puts("GX Rev. A");
|
puts("440GX Rev. A");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_440GX_RB:
|
case PVR_440GX_RB:
|
||||||
puts("GX Rev. B");
|
puts("440GX Rev. B");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_440GX_RC:
|
case PVR_440GX_RC:
|
||||||
puts("GX Rev. C");
|
puts("440GX Rev. C");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_440GX_RF:
|
case PVR_440GX_RF:
|
||||||
puts("GX Rev. F");
|
puts("440GX Rev. F");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_440EP_RA:
|
case PVR_440EP_RA:
|
||||||
puts("EP Rev. A");
|
puts("440EP Rev. A");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
#ifdef CONFIG_440EP
|
#ifdef CONFIG_440EP
|
||||||
case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
|
case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
|
||||||
puts("EP Rev. B");
|
puts("440EP Rev. B");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
|
case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
|
||||||
puts("EP Rev. C");
|
puts("440EP Rev. C");
|
||||||
break;
|
break;
|
||||||
#endif /* CONFIG_440EP */
|
#endif /* CONFIG_440EP */
|
||||||
|
|
||||||
#ifdef CONFIG_440GR
|
#ifdef CONFIG_440GR
|
||||||
case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
|
case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
|
||||||
puts("GR Rev. A");
|
puts("440GR Rev. A");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
|
case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
|
||||||
puts("GR Rev. B");
|
puts("440GR Rev. B");
|
||||||
break;
|
break;
|
||||||
#endif /* CONFIG_440GR */
|
#endif /* CONFIG_440GR */
|
||||||
#endif /* CONFIG_440 */
|
|
||||||
|
|
||||||
#ifdef CONFIG_440EPX
|
#ifdef CONFIG_440EPX
|
||||||
case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
|
case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
|
||||||
puts("EPx Rev. A");
|
puts("440EPx Rev. A");
|
||||||
strcpy(addstr, "Security/Kasumi support");
|
strcpy(addstr, "Security/Kasumi support");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
|
case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
|
||||||
puts("EPx Rev. A");
|
puts("440EPx Rev. A");
|
||||||
strcpy(addstr, "No Security/Kasumi support");
|
strcpy(addstr, "No Security/Kasumi support");
|
||||||
break;
|
break;
|
||||||
#endif /* CONFIG_440EPX */
|
#endif /* CONFIG_440EPX */
|
||||||
|
|
||||||
#ifdef CONFIG_440GRX
|
#ifdef CONFIG_440GRX
|
||||||
case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
|
case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
|
||||||
puts("GRx Rev. A");
|
puts("440GRx Rev. A");
|
||||||
strcpy(addstr, "Security/Kasumi support");
|
strcpy(addstr, "Security/Kasumi support");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
|
case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
|
||||||
puts("GRx Rev. A");
|
puts("440GRx Rev. A");
|
||||||
strcpy(addstr, "No Security/Kasumi support");
|
strcpy(addstr, "No Security/Kasumi support");
|
||||||
break;
|
break;
|
||||||
#endif /* CONFIG_440GRX */
|
#endif /* CONFIG_440GRX */
|
||||||
|
|
||||||
case PVR_440SP_6_RAB:
|
case PVR_440SP_6_RAB:
|
||||||
puts("SP Rev. A/B");
|
puts("440SP Rev. A/B");
|
||||||
strcpy(addstr, "RAID 6 support");
|
strcpy(addstr, "RAID 6 support");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_440SP_RAB:
|
case PVR_440SP_RAB:
|
||||||
puts("SP Rev. A/B");
|
puts("440SP Rev. A/B");
|
||||||
strcpy(addstr, "No RAID 6 support");
|
strcpy(addstr, "No RAID 6 support");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_440SP_6_RC:
|
case PVR_440SP_6_RC:
|
||||||
puts("SP Rev. C");
|
puts("440SP Rev. C");
|
||||||
strcpy(addstr, "RAID 6 support");
|
strcpy(addstr, "RAID 6 support");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_440SP_RC:
|
case PVR_440SP_RC:
|
||||||
puts("SP Rev. C");
|
puts("440SP Rev. C");
|
||||||
strcpy(addstr, "No RAID 6 support");
|
strcpy(addstr, "No RAID 6 support");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_440SPe_6_RA:
|
case PVR_440SPe_6_RA:
|
||||||
puts("SPe Rev. A");
|
puts("440SPe Rev. A");
|
||||||
strcpy(addstr, "RAID 6 support");
|
strcpy(addstr, "RAID 6 support");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_440SPe_RA:
|
case PVR_440SPe_RA:
|
||||||
puts("SPe Rev. A");
|
puts("440SPe Rev. A");
|
||||||
strcpy(addstr, "No RAID 6 support");
|
strcpy(addstr, "No RAID 6 support");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_440SPe_6_RB:
|
case PVR_440SPe_6_RB:
|
||||||
puts("SPe Rev. B");
|
puts("440SPe Rev. B");
|
||||||
strcpy(addstr, "RAID 6 support");
|
strcpy(addstr, "RAID 6 support");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_440SPe_RB:
|
case PVR_440SPe_RB:
|
||||||
puts("SPe Rev. B");
|
puts("440SPe Rev. B");
|
||||||
strcpy(addstr, "No RAID 6 support");
|
strcpy(addstr, "No RAID 6 support");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
|
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
|
||||||
case PVR_460EX_RA:
|
case PVR_460EX_RA:
|
||||||
puts("EX Rev. A");
|
puts("460EX Rev. A");
|
||||||
strcpy(addstr, "No Security/Kasumi support");
|
strcpy(addstr, "No Security/Kasumi support");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_460EX_SE_RA:
|
case PVR_460EX_SE_RA:
|
||||||
puts("EX Rev. A");
|
puts("460EX Rev. A");
|
||||||
strcpy(addstr, "Security/Kasumi support");
|
strcpy(addstr, "Security/Kasumi support");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_460EX_RB:
|
case PVR_460EX_RB:
|
||||||
puts("EX Rev. B");
|
puts("460EX Rev. B");
|
||||||
mfsdr(SDR0_ECID3, reg);
|
mfsdr(SDR0_ECID3, reg);
|
||||||
if (reg & 0x00100000)
|
if (reg & 0x00100000)
|
||||||
strcpy(addstr, "No Security/Kasumi support");
|
strcpy(addstr, "No Security/Kasumi support");
|
||||||
@ -560,17 +551,17 @@ int checkcpu (void)
|
|||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_460GT_RA:
|
case PVR_460GT_RA:
|
||||||
puts("GT Rev. A");
|
puts("460GT Rev. A");
|
||||||
strcpy(addstr, "No Security/Kasumi support");
|
strcpy(addstr, "No Security/Kasumi support");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_460GT_SE_RA:
|
case PVR_460GT_SE_RA:
|
||||||
puts("GT Rev. A");
|
puts("460GT Rev. A");
|
||||||
strcpy(addstr, "Security/Kasumi support");
|
strcpy(addstr, "Security/Kasumi support");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_460GT_RB:
|
case PVR_460GT_RB:
|
||||||
puts("GT Rev. B");
|
puts("460GT Rev. B");
|
||||||
mfsdr(SDR0_ECID3, reg);
|
mfsdr(SDR0_ECID3, reg);
|
||||||
if (reg & 0x00100000)
|
if (reg & 0x00100000)
|
||||||
strcpy(addstr, "No Security/Kasumi support");
|
strcpy(addstr, "No Security/Kasumi support");
|
||||||
@ -580,28 +571,29 @@ int checkcpu (void)
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
case PVR_460SX_RA:
|
case PVR_460SX_RA:
|
||||||
puts("SX Rev. A");
|
puts("460SX Rev. A");
|
||||||
strcpy(addstr, "Security support");
|
strcpy(addstr, "Security support");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_460SX_RA_V1:
|
case PVR_460SX_RA_V1:
|
||||||
puts("SX Rev. A");
|
puts("460SX Rev. A");
|
||||||
strcpy(addstr, "No Security support");
|
strcpy(addstr, "No Security support");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_460GX_RA:
|
case PVR_460GX_RA:
|
||||||
puts("GX Rev. A");
|
puts("460GX Rev. A");
|
||||||
strcpy(addstr, "Security support");
|
strcpy(addstr, "Security support");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_460GX_RA_V1:
|
case PVR_460GX_RA_V1:
|
||||||
puts("GX Rev. A");
|
puts("460GX Rev. A");
|
||||||
strcpy(addstr, "No Security support");
|
strcpy(addstr, "No Security support");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PVR_VIRTEX5:
|
case PVR_VIRTEX5:
|
||||||
puts("x5 VIRTEX5");
|
puts("440x5 VIRTEX5");
|
||||||
break;
|
break;
|
||||||
|
#endif /* CONFIG_440 */
|
||||||
|
|
||||||
default:
|
default:
|
||||||
printf (" UNKNOWN (PVR=%08x)", pvr);
|
printf (" UNKNOWN (PVR=%08x)", pvr);
|
||||||
|
@ -23,10 +23,10 @@
|
|||||||
|
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <watchdog.h>
|
#include <watchdog.h>
|
||||||
#include <ppc4xx_enet.h>
|
#include <asm/ppc4xx-emac.h>
|
||||||
#include <asm/processor.h>
|
#include <asm/processor.h>
|
||||||
#include <asm/gpio.h>
|
#include <asm/ppc4xx-gpio.h>
|
||||||
#include <ppc4xx.h>
|
#include <asm/ppc4xx.h>
|
||||||
|
|
||||||
#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
|
#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
@ -266,7 +266,7 @@ cpu_init_f (void)
|
|||||||
/*
|
/*
|
||||||
* Set EMAC noise filter bits
|
* Set EMAC noise filter bits
|
||||||
*/
|
*/
|
||||||
mtdcr(CPC0_EPCTL, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE);
|
mtdcr(CPC0_EPCTL, CPC0_EPCTL_E0NFE | CPC0_EPCTL_E1NFE);
|
||||||
#endif /* CONFIG_405EP */
|
#endif /* CONFIG_405EP */
|
||||||
|
|
||||||
#if defined(CONFIG_SYS_4xx_GPIO_TABLE)
|
#if defined(CONFIG_SYS_4xx_GPIO_TABLE)
|
||||||
@ -397,10 +397,10 @@ cpu_init_f (void)
|
|||||||
/*
|
/*
|
||||||
* Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
|
* Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
|
||||||
*/
|
*/
|
||||||
mtdcr(PLB0_ACR, (mfdcr(PLB0_ACR) & ~PLB0_ACR_RDP_MASK) |
|
mtdcr(PLB4A0_ACR, (mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_RDP_MASK) |
|
||||||
PLB0_ACR_RDP_4DEEP);
|
PLB4Ax_ACR_RDP_4DEEP);
|
||||||
mtdcr(PLB1_ACR, (mfdcr(PLB1_ACR) & ~PLB1_ACR_RDP_MASK) |
|
mtdcr(PLB4A1_ACR, (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_RDP_MASK) |
|
||||||
PLB1_ACR_RDP_4DEEP);
|
PLB4Ax_ACR_RDP_4DEEP);
|
||||||
#endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
|
#endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -24,7 +24,7 @@
|
|||||||
|
|
||||||
#if defined(CONFIG_4xx) && defined(CONFIG_CMD_SETGETDCR)
|
#if defined(CONFIG_4xx) && defined(CONFIG_CMD_SETGETDCR)
|
||||||
|
|
||||||
#include <ppc4xx.h>
|
#include <asm/ppc4xx.h>
|
||||||
|
|
||||||
#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
|
#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
|
||||||
|
|
||||||
|
@ -36,7 +36,7 @@
|
|||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <asm/processor.h>
|
#include <asm/processor.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <ppc4xx.h>
|
#include <asm/ppc4xx.h>
|
||||||
|
|
||||||
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
|
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
|
||||||
/*-----------------------------------------------------------------------------+
|
/*-----------------------------------------------------------------------------+
|
||||||
|
@ -40,7 +40,7 @@
|
|||||||
|
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <command.h>
|
#include <command.h>
|
||||||
#include <ppc4xx.h>
|
#include <asm/ppc4xx.h>
|
||||||
#include <i2c.h>
|
#include <i2c.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <asm/processor.h>
|
#include <asm/processor.h>
|
||||||
|
@ -37,7 +37,7 @@
|
|||||||
*/
|
*/
|
||||||
|
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <ppc4xx.h>
|
#include <asm/ppc4xx.h>
|
||||||
#include <ppc_asm.tmpl>
|
#include <ppc_asm.tmpl>
|
||||||
#include <ppc_defs.h>
|
#include <ppc_defs.h>
|
||||||
#include <asm/processor.h>
|
#include <asm/processor.h>
|
||||||
|
@ -25,7 +25,7 @@
|
|||||||
#include <watchdog.h>
|
#include <watchdog.h>
|
||||||
#include <command.h>
|
#include <command.h>
|
||||||
#include <asm/cache.h>
|
#include <asm/cache.h>
|
||||||
#include <ppc4xx.h>
|
#include <asm/ppc4xx.h>
|
||||||
|
|
||||||
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
||||||
#include <libfdt.h>
|
#include <libfdt.h>
|
||||||
|
@ -24,7 +24,10 @@
|
|||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <asm/processor.h>
|
#include <asm/processor.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <asm/gpio.h>
|
#include <asm/ppc4xx-gpio.h>
|
||||||
|
|
||||||
|
/* Only compile this file for boards with GPIO support */
|
||||||
|
#if defined(GPIO0_BASE)
|
||||||
|
|
||||||
#if defined(CONFIG_SYS_4xx_GPIO_TABLE)
|
#if defined(CONFIG_SYS_4xx_GPIO_TABLE)
|
||||||
gpio_param_s const gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CONFIG_SYS_4xx_GPIO_TABLE;
|
gpio_param_s const gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CONFIG_SYS_4xx_GPIO_TABLE;
|
||||||
@ -252,4 +255,6 @@ void gpio_set_chip_configuration(void)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#endif /* GPIO0_BASE */
|
||||||
#endif /* CONFIG_SYS_4xx_GPIO_TABLE */
|
#endif /* CONFIG_SYS_4xx_GPIO_TABLE */
|
||||||
|
@ -36,7 +36,7 @@
|
|||||||
#include <command.h>
|
#include <command.h>
|
||||||
#include <asm/processor.h>
|
#include <asm/processor.h>
|
||||||
#include <asm/interrupt.h>
|
#include <asm/interrupt.h>
|
||||||
#include <ppc4xx.h>
|
#include <asm/ppc4xx.h>
|
||||||
#include <ppc_asm.tmpl>
|
#include <ppc_asm.tmpl>
|
||||||
#include <commproc.h>
|
#include <commproc.h>
|
||||||
|
|
||||||
|
@ -22,7 +22,7 @@
|
|||||||
|
|
||||||
#include <config.h>
|
#include <config.h>
|
||||||
#include <command.h>
|
#include <command.h>
|
||||||
#include <ppc4xx.h>
|
#include <asm/ppc4xx.h>
|
||||||
#include <version.h>
|
#include <version.h>
|
||||||
|
|
||||||
#define CONFIG_405GP 1 /* needed for Linux kernel header files */
|
#define CONFIG_405GP 1 /* needed for Linux kernel header files */
|
||||||
|
@ -41,8 +41,8 @@
|
|||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <ppc_asm.tmpl>
|
#include <ppc_asm.tmpl>
|
||||||
#include <commproc.h>
|
#include <commproc.h>
|
||||||
#include <ppc4xx_enet.h>
|
#include <asm/ppc4xx-emac.h>
|
||||||
#include <405_mal.h>
|
#include <asm/ppc4xx-mal.h>
|
||||||
#include <miiphy.h>
|
#include <miiphy.h>
|
||||||
|
|
||||||
#if !defined(CONFIG_PHY_CLK_FREQ)
|
#if !defined(CONFIG_PHY_CLK_FREQ)
|
||||||
|
@ -28,7 +28,7 @@
|
|||||||
#include <asm/processor.h>
|
#include <asm/processor.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <asm/ppc4xx-uic.h>
|
#include <asm/ppc4xx-uic.h>
|
||||||
#include <ppc4xx_enet.h>
|
#include <asm/ppc4xx-emac.h>
|
||||||
|
|
||||||
enum REGISTER_TYPE {
|
enum REGISTER_TYPE {
|
||||||
IDCR1, /* Indirectly Accessed DCR via SDRAM0_CFGADDR/SDRAM0_CFGDATA */
|
IDCR1, /* Indirectly Accessed DCR via SDRAM0_CFGADDR/SDRAM0_CFGDATA */
|
||||||
@ -108,9 +108,9 @@ const struct cpu_register ppc4xx_reg[] = {
|
|||||||
{"SDR0_SDSTP3", IDCR6, SDR0_SDSTP3},
|
{"SDR0_SDSTP3", IDCR6, SDR0_SDSTP3},
|
||||||
{"SDR0_CUST0", IDCR6, SDR0_CUST0},
|
{"SDR0_CUST0", IDCR6, SDR0_CUST0},
|
||||||
{"SDR0_CUST1", IDCR6, SDR0_CUST1},
|
{"SDR0_CUST1", IDCR6, SDR0_CUST1},
|
||||||
{"SDR0_EBC0", IDCR6, SDR0_EBC0},
|
{"SDR0_EBC", IDCR6, SDR0_EBC},
|
||||||
{"SDR0_AMP0", IDCR6, SD0_AMP0},
|
{"SDR0_AMP0", IDCR6, SDR0_AMP0},
|
||||||
{"SDR0_AMP1", IDCR6, SD0_AMP1},
|
{"SDR0_AMP1", IDCR6, SDR0_AMP1},
|
||||||
{"SDR0_CP440", IDCR6, SDR0_CP440},
|
{"SDR0_CP440", IDCR6, SDR0_CP440},
|
||||||
{"SDR0_CRYP0", IDCR6, SDR0_CRYP0},
|
{"SDR0_CRYP0", IDCR6, SDR0_CRYP0},
|
||||||
{"SDR0_DDRCFG", IDCR6, SDR0_DDRCFG},
|
{"SDR0_DDRCFG", IDCR6, SDR0_DDRCFG},
|
||||||
|
@ -28,7 +28,7 @@
|
|||||||
*/
|
*/
|
||||||
|
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <ppc4xx.h>
|
#include <asm/ppc4xx.h>
|
||||||
#include <asm/processor.h>
|
#include <asm/processor.h>
|
||||||
#include "sdram.h"
|
#include "sdram.h"
|
||||||
#include "ecc.h"
|
#include "ecc.h"
|
||||||
|
@ -23,7 +23,7 @@
|
|||||||
|
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <ppc_asm.tmpl>
|
#include <ppc_asm.tmpl>
|
||||||
#include <ppc4xx.h>
|
#include <asm/ppc4xx.h>
|
||||||
#include <asm/processor.h>
|
#include <asm/processor.h>
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
@ -902,7 +902,7 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
|
|||||||
/*
|
/*
|
||||||
* Read CPR_PRIMAD register
|
* Read CPR_PRIMAD register
|
||||||
*/
|
*/
|
||||||
mfcpr(CPC0_PRIMAD, cpr_primad);
|
mfcpr(CPR0_PRIMAD, cpr_primad);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Determine PLB_DIV.
|
* Determine PLB_DIV.
|
||||||
|
@ -64,7 +64,7 @@
|
|||||||
* address and (s)dram will be positioned at address 0
|
* address and (s)dram will be positioned at address 0
|
||||||
*/
|
*/
|
||||||
#include <config.h>
|
#include <config.h>
|
||||||
#include <ppc4xx.h>
|
#include <asm/ppc4xx.h>
|
||||||
#include <timestamp.h>
|
#include <timestamp.h>
|
||||||
#include <version.h>
|
#include <version.h>
|
||||||
|
|
||||||
@ -340,6 +340,9 @@ _start_440:
|
|||||||
mfspr r1,SPRN_DBCR0
|
mfspr r1,SPRN_DBCR0
|
||||||
andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
|
andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
|
||||||
bne skip_debug_init /* if set, don't clear debug register */
|
bne skip_debug_init /* if set, don't clear debug register */
|
||||||
|
mfspr r1,SPRN_CCR0
|
||||||
|
ori r1,r1,CCR0_DTB@l /* Disable Trace Broadcast */
|
||||||
|
mtspr SPRN_CCR0,r1
|
||||||
mtspr SPRN_DBCR0,r0
|
mtspr SPRN_DBCR0,r0
|
||||||
mtspr SPRN_DBCR1,r0
|
mtspr SPRN_DBCR1,r0
|
||||||
mtspr SPRN_DBCR2,r0
|
mtspr SPRN_DBCR2,r0
|
||||||
|
@ -25,7 +25,7 @@
|
|||||||
|
|
||||||
#if defined(CONFIG_440)
|
#if defined(CONFIG_440)
|
||||||
|
|
||||||
#include <ppc440.h>
|
#include <asm/ppc440.h>
|
||||||
#include <asm/cache.h>
|
#include <asm/cache.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <asm/mmu.h>
|
#include <asm/mmu.h>
|
||||||
|
@ -36,7 +36,7 @@
|
|||||||
#include <command.h>
|
#include <command.h>
|
||||||
#include <asm/processor.h>
|
#include <asm/processor.h>
|
||||||
#include <asm/interrupt.h>
|
#include <asm/interrupt.h>
|
||||||
#include <ppc4xx.h>
|
#include <asm/ppc4xx.h>
|
||||||
#include <ppc_asm.tmpl>
|
#include <ppc_asm.tmpl>
|
||||||
#include <commproc.h>
|
#include <commproc.h>
|
||||||
|
|
||||||
|
@ -21,7 +21,7 @@
|
|||||||
#include <command.h>
|
#include <command.h>
|
||||||
#include <asm/processor.h>
|
#include <asm/processor.h>
|
||||||
#include <asm/interrupt.h>
|
#include <asm/interrupt.h>
|
||||||
#include <ppc4xx.h>
|
#include <asm/ppc4xx.h>
|
||||||
#include <ppc_asm.tmpl>
|
#include <ppc_asm.tmpl>
|
||||||
#include <commproc.h>
|
#include <commproc.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
|
@ -11,7 +11,7 @@
|
|||||||
#ifndef __4XX_PCIE_H
|
#ifndef __4XX_PCIE_H
|
||||||
#define __4XX_PCIE_H
|
#define __4XX_PCIE_H
|
||||||
|
|
||||||
#include <ppc4xx.h>
|
#include <asm/ppc4xx.h>
|
||||||
#include <pci.h>
|
#include <pci.h>
|
||||||
|
|
||||||
#define DCRN_SDR0_CFGADDR 0x00e
|
#define DCRN_SDR0_CFGADDR 0x00e
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
* (C) Copyright 2002
|
* (C) Copyright 2002-2010
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
*
|
*
|
||||||
* See file CREDITS for list of people who contributed to this
|
* See file CREDITS for list of people who contributed to this
|
||||||
@ -176,6 +176,7 @@ typedef struct global_data {
|
|||||||
unsigned long long wdt_last; /* trace watch-dog triggering rate */
|
unsigned long long wdt_last; /* trace watch-dog triggering rate */
|
||||||
#endif
|
#endif
|
||||||
void **jt; /* jump table */
|
void **jt; /* jump table */
|
||||||
|
char env_buf[32]; /* buffer for getenv() before reloc. */
|
||||||
} gd_t;
|
} gd_t;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -188,6 +189,7 @@ typedef struct global_data {
|
|||||||
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
|
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
|
||||||
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
|
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
|
||||||
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
|
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
|
||||||
|
#define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */
|
||||||
|
|
||||||
#if 1
|
#if 1
|
||||||
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2")
|
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2")
|
||||||
|
80
arch/powerpc/include/asm/ppc405.h
Normal file
80
arch/powerpc/include/asm/ppc405.h
Normal file
@ -0,0 +1,80 @@
|
|||||||
|
/*----------------------------------------------------------------------------+
|
||||||
|
| This source code is dual-licensed. You may use it under the terms of the
|
||||||
|
| GNU General Public License version 2, or under the license below.
|
||||||
|
|
|
||||||
|
| This source code has been made available to you by IBM on an AS-IS
|
||||||
|
| basis. Anyone receiving this source is licensed under IBM
|
||||||
|
| copyrights to use it in any way he or she deems fit, including
|
||||||
|
| copying it, modifying it, compiling it, and redistributing it either
|
||||||
|
| with or without modifications. No license under IBM patents or
|
||||||
|
| patent applications is to be implied by the copyright license.
|
||||||
|
|
|
||||||
|
| Any user of this software should understand that IBM cannot provide
|
||||||
|
| technical support for this software and will not be responsible for
|
||||||
|
| any consequences resulting from the use of this software.
|
||||||
|
|
|
||||||
|
| Any person who transfers this source code or any derivative work
|
||||||
|
| must include the IBM copyright notice, this paragraph, and the
|
||||||
|
| preceding two paragraphs in the transferred software.
|
||||||
|
|
|
||||||
|
| COPYRIGHT I B M CORPORATION 1999
|
||||||
|
| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
|
||||||
|
+----------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
#ifndef __PPC405_H__
|
||||||
|
#define __PPC405_H__
|
||||||
|
|
||||||
|
/* Define bits and masks for real-mode storage attribute control registers */
|
||||||
|
#define PPC_128MB_SACR_BIT(addr) ((addr) >> 27)
|
||||||
|
#define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1)
|
||||||
|
|
||||||
|
#ifndef CONFIG_IOP480
|
||||||
|
#define CONFIG_SYS_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */
|
||||||
|
#else
|
||||||
|
#define CONFIG_SYS_DCACHE_SIZE (2 << 10) /* For PLX IOP480(403)*/
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* DCR registers */
|
||||||
|
#define PLB0_ACR 0x0087
|
||||||
|
|
||||||
|
/* SDR registers */
|
||||||
|
#define SDR0_PINSTP 0x0040
|
||||||
|
|
||||||
|
/* CPR registers */
|
||||||
|
#define CPR0_CLKUPD 0x0020
|
||||||
|
#define CPR0_PLLC 0x0040
|
||||||
|
#define CPR0_PLLD 0x0060
|
||||||
|
#define CPR0_CPUD 0x0080
|
||||||
|
#define CPR0_PLBD 0x00a0
|
||||||
|
#define CPR0_OPBD0 0x00c0
|
||||||
|
#define CPR0_PERD 0x00e0
|
||||||
|
|
||||||
|
/*
|
||||||
|
* DMA
|
||||||
|
*/
|
||||||
|
#define DMA_DCR_BASE 0x0100
|
||||||
|
#define DMACR0 (DMA_DCR_BASE + 0x00) /* DMA channel control reg 0 */
|
||||||
|
#define DMACT0 (DMA_DCR_BASE + 0x01) /* DMA count reg 0 */
|
||||||
|
#define DMADA0 (DMA_DCR_BASE + 0x02) /* DMA destination address reg 0 */
|
||||||
|
#define DMASA0 (DMA_DCR_BASE + 0x03) /* DMA source address reg 0 */
|
||||||
|
#define DMASB0 (DMA_DCR_BASE + 0x04) /* DMA sg descriptor addr 0 */
|
||||||
|
#define DMACR1 (DMA_DCR_BASE + 0x08) /* DMA channel control reg 1 */
|
||||||
|
#define DMACT1 (DMA_DCR_BASE + 0x09) /* DMA count reg 1 */
|
||||||
|
#define DMADA1 (DMA_DCR_BASE + 0x0a) /* DMA destination address reg 1 */
|
||||||
|
#define DMASA1 (DMA_DCR_BASE + 0x0b) /* DMA source address reg 1 */
|
||||||
|
#define DMASB1 (DMA_DCR_BASE + 0x0c) /* DMA sg descriptor addr 1 */
|
||||||
|
#define DMACR2 (DMA_DCR_BASE + 0x10) /* DMA channel control reg 2 */
|
||||||
|
#define DMACT2 (DMA_DCR_BASE + 0x11) /* DMA count reg 2 */
|
||||||
|
#define DMADA2 (DMA_DCR_BASE + 0x12) /* DMA destination address reg 2 */
|
||||||
|
#define DMASA2 (DMA_DCR_BASE + 0x13) /* DMA source address reg 2 */
|
||||||
|
#define DMASB2 (DMA_DCR_BASE + 0x14) /* DMA sg descriptor addr 2 */
|
||||||
|
#define DMACR3 (DMA_DCR_BASE + 0x18) /* DMA channel control reg 3 */
|
||||||
|
#define DMACT3 (DMA_DCR_BASE + 0x19) /* DMA count reg 3 */
|
||||||
|
#define DMADA3 (DMA_DCR_BASE + 0x1a) /* DMA destination address reg 3 */
|
||||||
|
#define DMASA3 (DMA_DCR_BASE + 0x1b) /* DMA source address reg 3 */
|
||||||
|
#define DMASB3 (DMA_DCR_BASE + 0x1c) /* DMA sg descriptor addr 3 */
|
||||||
|
#define DMASR (DMA_DCR_BASE + 0x20) /* DMA status reg */
|
||||||
|
#define DMASGC (DMA_DCR_BASE + 0x23) /* DMA scatter/gather command reg*/
|
||||||
|
#define DMAADR (DMA_DCR_BASE + 0x24) /* DMA address decode reg */
|
||||||
|
|
||||||
|
#endif /* __PPC405_H__ */
|
105
arch/powerpc/include/asm/ppc405cr.h
Normal file
105
arch/powerpc/include/asm/ppc405cr.h
Normal file
@ -0,0 +1,105 @@
|
|||||||
|
/*
|
||||||
|
* (C) Copyright 2010
|
||||||
|
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _PPC405CR_H_
|
||||||
|
#define _PPC405CR_H_
|
||||||
|
|
||||||
|
#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */
|
||||||
|
|
||||||
|
/* Memory mapped register */
|
||||||
|
#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */
|
||||||
|
|
||||||
|
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
|
||||||
|
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
|
||||||
|
|
||||||
|
#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
|
||||||
|
|
||||||
|
/* DCR's */
|
||||||
|
#define DCP0_CFGADDR 0x0014 /* Decompression controller addr reg */
|
||||||
|
#define DCP0_CFGDATA 0x0015 /* Decompression controller data reg */
|
||||||
|
#define OCM0_ISCNTL 0x0019 /* OCM I-side control reg */
|
||||||
|
#define OCM0_DSARC 0x001a /* OCM D-side address compare */
|
||||||
|
#define OCM0_DSCNTL 0x001b /* OCM D-side control */
|
||||||
|
#define CPC0_PLLMR 0x00b0 /* PLL mode register */
|
||||||
|
#define CPC0_CR0 0x00b1 /* chip control register 0 */
|
||||||
|
#define CPC0_CR1 0x00b2 /* chip control register 1 */
|
||||||
|
#define CPC0_PSR 0x00b4 /* chip pin strapping reg */
|
||||||
|
#define CPC0_EIRR 0x00b6 /* ext interrupt routing reg */
|
||||||
|
#define CPC0_SR 0x00b8 /* Power management status */
|
||||||
|
#define CPC0_ER 0x00b9 /* Power management enable */
|
||||||
|
#define CPC0_FR 0x00ba /* Power management force */
|
||||||
|
#define CPC0_ECR 0x00aa /* edge conditioner register */
|
||||||
|
|
||||||
|
#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */
|
||||||
|
#define PLLMR_FWD_DIV_BYPASS 0xE0000000
|
||||||
|
#define PLLMR_FWD_DIV_3 0xA0000000
|
||||||
|
#define PLLMR_FWD_DIV_4 0x80000000
|
||||||
|
#define PLLMR_FWD_DIV_6 0x40000000
|
||||||
|
|
||||||
|
#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */
|
||||||
|
#define PLLMR_FB_DIV_1 0x02000000
|
||||||
|
#define PLLMR_FB_DIV_2 0x04000000
|
||||||
|
#define PLLMR_FB_DIV_3 0x06000000
|
||||||
|
#define PLLMR_FB_DIV_4 0x08000000
|
||||||
|
|
||||||
|
#define PLLMR_TUNING_MASK 0x01F80000
|
||||||
|
|
||||||
|
#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */
|
||||||
|
#define PLLMR_CPU_PLB_DIV_1 0x00000000
|
||||||
|
#define PLLMR_CPU_PLB_DIV_2 0x00020000
|
||||||
|
#define PLLMR_CPU_PLB_DIV_3 0x00040000
|
||||||
|
#define PLLMR_CPU_PLB_DIV_4 0x00060000
|
||||||
|
|
||||||
|
#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */
|
||||||
|
#define PLLMR_OPB_PLB_DIV_1 0x00000000
|
||||||
|
#define PLLMR_OPB_PLB_DIV_2 0x00008000
|
||||||
|
#define PLLMR_OPB_PLB_DIV_3 0x00010000
|
||||||
|
#define PLLMR_OPB_PLB_DIV_4 0x00018000
|
||||||
|
|
||||||
|
#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */
|
||||||
|
#define PLLMR_PCI_PLB_DIV_1 0x00000000
|
||||||
|
#define PLLMR_PCI_PLB_DIV_2 0x00002000
|
||||||
|
#define PLLMR_PCI_PLB_DIV_3 0x00004000
|
||||||
|
#define PLLMR_PCI_PLB_DIV_4 0x00006000
|
||||||
|
|
||||||
|
#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */
|
||||||
|
#define PLLMR_EXB_PLB_DIV_2 0x00000000
|
||||||
|
#define PLLMR_EXB_PLB_DIV_3 0x00000800
|
||||||
|
#define PLLMR_EXB_PLB_DIV_4 0x00001000
|
||||||
|
#define PLLMR_EXB_PLB_DIV_5 0x00001800
|
||||||
|
|
||||||
|
/* definitions for PPC405GPr (new mode strapping) */
|
||||||
|
#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */
|
||||||
|
|
||||||
|
#define PSR_PLL_FWD_MASK 0xC0000000
|
||||||
|
#define PSR_PLL_FDBACK_MASK 0x30000000
|
||||||
|
#define PSR_PLL_TUNING_MASK 0x0E000000
|
||||||
|
#define PSR_PLB_CPU_MASK 0x01800000
|
||||||
|
#define PSR_OPB_PLB_MASK 0x00600000
|
||||||
|
#define PSR_PCI_PLB_MASK 0x00180000
|
||||||
|
#define PSR_EB_PLB_MASK 0x00060000
|
||||||
|
#define PSR_ROM_WIDTH_MASK 0x00018000
|
||||||
|
#define PSR_ROM_LOC 0x00004000
|
||||||
|
#define PSR_PCI_ASYNC_EN 0x00001000
|
||||||
|
#define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */
|
||||||
|
#define PSR_PCI_ARBIT_EN 0x00000400
|
||||||
|
#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */
|
||||||
|
|
||||||
|
#endif /* _PPC405CR_H_ */
|
252
arch/powerpc/include/asm/ppc405ep.h
Normal file
252
arch/powerpc/include/asm/ppc405ep.h
Normal file
@ -0,0 +1,252 @@
|
|||||||
|
/*
|
||||||
|
* (C) Copyright 2010
|
||||||
|
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _PPC405EP_H_
|
||||||
|
#define _PPC405EP_H_
|
||||||
|
|
||||||
|
#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */
|
||||||
|
|
||||||
|
/* Memory mapped register */
|
||||||
|
#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */
|
||||||
|
|
||||||
|
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
|
||||||
|
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
|
||||||
|
|
||||||
|
#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
|
||||||
|
|
||||||
|
/* DCR */
|
||||||
|
#define OCM0_ISCNTL 0x0019 /* OCM I-side control reg */
|
||||||
|
#define OCM0_DSARC 0x001a /* OCM D-side address compare */
|
||||||
|
#define OCM0_DSCNTL 0x001b /* OCM D-side control */
|
||||||
|
#define CPC0_PLLMR0 0x00f0 /* PLL mode register 0 */
|
||||||
|
#define CPC0_BOOT 0x00f1 /* Clock status register */
|
||||||
|
#define CPC0_CR1 0x00f2 /* Chip Control 1 register */
|
||||||
|
#define CPC0_EPCTL 0x00f3 /* EMAC to PHY control register */
|
||||||
|
#define CPC0_PLLMR1 0x00f4 /* PLL mode register 1 */
|
||||||
|
#define CPC0_UCR 0x00f5 /* UART control register */
|
||||||
|
#define CPC0_SRR 0x00f6 /* Soft Reset register */
|
||||||
|
#define CPC0_PCI 0x00f9 /* PCI control register */
|
||||||
|
|
||||||
|
/* Defines for CPC0_EPCTL register */
|
||||||
|
#define CPC0_EPCTL_E0NFE 0x80000000
|
||||||
|
#define CPC0_EPCTL_E1NFE 0x40000000
|
||||||
|
|
||||||
|
/* Defines for CPC0_PCI Register */
|
||||||
|
#define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */
|
||||||
|
#define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */
|
||||||
|
#define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled */
|
||||||
|
|
||||||
|
/* Defines for CPC0_BOOR Register */
|
||||||
|
#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */
|
||||||
|
|
||||||
|
/* Bit definitions */
|
||||||
|
#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */
|
||||||
|
#define PLLMR0_CPU_DIV_BYPASS 0x00000000
|
||||||
|
#define PLLMR0_CPU_DIV_2 0x00100000
|
||||||
|
#define PLLMR0_CPU_DIV_3 0x00200000
|
||||||
|
#define PLLMR0_CPU_DIV_4 0x00300000
|
||||||
|
|
||||||
|
#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */
|
||||||
|
#define PLLMR0_CPU_PLB_DIV_1 0x00000000
|
||||||
|
#define PLLMR0_CPU_PLB_DIV_2 0x00010000
|
||||||
|
#define PLLMR0_CPU_PLB_DIV_3 0x00020000
|
||||||
|
#define PLLMR0_CPU_PLB_DIV_4 0x00030000
|
||||||
|
|
||||||
|
#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */
|
||||||
|
#define PLLMR0_OPB_PLB_DIV_1 0x00000000
|
||||||
|
#define PLLMR0_OPB_PLB_DIV_2 0x00001000
|
||||||
|
#define PLLMR0_OPB_PLB_DIV_3 0x00002000
|
||||||
|
#define PLLMR0_OPB_PLB_DIV_4 0x00003000
|
||||||
|
|
||||||
|
#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */
|
||||||
|
#define PLLMR0_EXB_PLB_DIV_2 0x00000000
|
||||||
|
#define PLLMR0_EXB_PLB_DIV_3 0x00000100
|
||||||
|
#define PLLMR0_EXB_PLB_DIV_4 0x00000200
|
||||||
|
#define PLLMR0_EXB_PLB_DIV_5 0x00000300
|
||||||
|
|
||||||
|
#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */
|
||||||
|
#define PLLMR0_MAL_PLB_DIV_1 0x00000000
|
||||||
|
#define PLLMR0_MAL_PLB_DIV_2 0x00000010
|
||||||
|
#define PLLMR0_MAL_PLB_DIV_3 0x00000020
|
||||||
|
#define PLLMR0_MAL_PLB_DIV_4 0x00000030
|
||||||
|
|
||||||
|
#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */
|
||||||
|
#define PLLMR0_PCI_PLB_DIV_1 0x00000000
|
||||||
|
#define PLLMR0_PCI_PLB_DIV_2 0x00000001
|
||||||
|
#define PLLMR0_PCI_PLB_DIV_3 0x00000002
|
||||||
|
#define PLLMR0_PCI_PLB_DIV_4 0x00000003
|
||||||
|
|
||||||
|
#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */
|
||||||
|
#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */
|
||||||
|
#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */
|
||||||
|
|
||||||
|
#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */
|
||||||
|
#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */
|
||||||
|
#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */
|
||||||
|
|
||||||
|
/* Defines for CPC0_PLLMR1 Register fields */
|
||||||
|
#define PLL_ACTIVE 0x80000000
|
||||||
|
#define CPC0_PLLMR1_SSCS 0x80000000
|
||||||
|
#define PLL_RESET 0x40000000
|
||||||
|
#define CPC0_PLLMR1_PLLR 0x40000000
|
||||||
|
/* Feedback multiplier */
|
||||||
|
#define PLL_FBKDIV 0x00F00000
|
||||||
|
#define CPC0_PLLMR1_FBDV 0x00F00000
|
||||||
|
#define PLL_FBKDIV_16 0x00000000
|
||||||
|
#define PLL_FBKDIV_1 0x00100000
|
||||||
|
#define PLL_FBKDIV_2 0x00200000
|
||||||
|
#define PLL_FBKDIV_3 0x00300000
|
||||||
|
#define PLL_FBKDIV_4 0x00400000
|
||||||
|
#define PLL_FBKDIV_5 0x00500000
|
||||||
|
#define PLL_FBKDIV_6 0x00600000
|
||||||
|
#define PLL_FBKDIV_7 0x00700000
|
||||||
|
#define PLL_FBKDIV_8 0x00800000
|
||||||
|
#define PLL_FBKDIV_9 0x00900000
|
||||||
|
#define PLL_FBKDIV_10 0x00A00000
|
||||||
|
#define PLL_FBKDIV_11 0x00B00000
|
||||||
|
#define PLL_FBKDIV_12 0x00C00000
|
||||||
|
#define PLL_FBKDIV_13 0x00D00000
|
||||||
|
#define PLL_FBKDIV_14 0x00E00000
|
||||||
|
#define PLL_FBKDIV_15 0x00F00000
|
||||||
|
/* Forward A divisor */
|
||||||
|
#define PLL_FWDDIVA 0x00070000
|
||||||
|
#define CPC0_PLLMR1_FWDVA 0x00070000
|
||||||
|
#define PLL_FWDDIVA_8 0x00000000
|
||||||
|
#define PLL_FWDDIVA_7 0x00010000
|
||||||
|
#define PLL_FWDDIVA_6 0x00020000
|
||||||
|
#define PLL_FWDDIVA_5 0x00030000
|
||||||
|
#define PLL_FWDDIVA_4 0x00040000
|
||||||
|
#define PLL_FWDDIVA_3 0x00050000
|
||||||
|
#define PLL_FWDDIVA_2 0x00060000
|
||||||
|
#define PLL_FWDDIVA_1 0x00070000
|
||||||
|
/* Forward B divisor */
|
||||||
|
#define PLL_FWDDIVB 0x00007000
|
||||||
|
#define CPC0_PLLMR1_FWDVB 0x00007000
|
||||||
|
#define PLL_FWDDIVB_8 0x00000000
|
||||||
|
#define PLL_FWDDIVB_7 0x00001000
|
||||||
|
#define PLL_FWDDIVB_6 0x00002000
|
||||||
|
#define PLL_FWDDIVB_5 0x00003000
|
||||||
|
#define PLL_FWDDIVB_4 0x00004000
|
||||||
|
#define PLL_FWDDIVB_3 0x00005000
|
||||||
|
#define PLL_FWDDIVB_2 0x00006000
|
||||||
|
#define PLL_FWDDIVB_1 0x00007000
|
||||||
|
/* PLL tune bits */
|
||||||
|
#define PLL_TUNE_MASK 0x000003FF
|
||||||
|
#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
|
||||||
|
#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
|
||||||
|
#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
|
||||||
|
#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
|
||||||
|
#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
|
||||||
|
#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
|
||||||
|
#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
|
||||||
|
|
||||||
|
/* Defines for CPC0_PLLMR0 Register fields */
|
||||||
|
/* CPU divisor */
|
||||||
|
#define PLL_CPUDIV 0x00300000
|
||||||
|
#define CPC0_PLLMR0_CCDV 0x00300000
|
||||||
|
#define PLL_CPUDIV_1 0x00000000
|
||||||
|
#define PLL_CPUDIV_2 0x00100000
|
||||||
|
#define PLL_CPUDIV_3 0x00200000
|
||||||
|
#define PLL_CPUDIV_4 0x00300000
|
||||||
|
/* PLB divisor */
|
||||||
|
#define PLL_PLBDIV 0x00030000
|
||||||
|
#define CPC0_PLLMR0_CBDV 0x00030000
|
||||||
|
#define PLL_PLBDIV_1 0x00000000
|
||||||
|
#define PLL_PLBDIV_2 0x00010000
|
||||||
|
#define PLL_PLBDIV_3 0x00020000
|
||||||
|
#define PLL_PLBDIV_4 0x00030000
|
||||||
|
/* OPB divisor */
|
||||||
|
#define PLL_OPBDIV 0x00003000
|
||||||
|
#define CPC0_PLLMR0_OPDV 0x00003000
|
||||||
|
#define PLL_OPBDIV_1 0x00000000
|
||||||
|
#define PLL_OPBDIV_2 0x00001000
|
||||||
|
#define PLL_OPBDIV_3 0x00002000
|
||||||
|
#define PLL_OPBDIV_4 0x00003000
|
||||||
|
/* EBC divisor */
|
||||||
|
#define PLL_EXTBUSDIV 0x00000300
|
||||||
|
#define CPC0_PLLMR0_EPDV 0x00000300
|
||||||
|
#define PLL_EXTBUSDIV_2 0x00000000
|
||||||
|
#define PLL_EXTBUSDIV_3 0x00000100
|
||||||
|
#define PLL_EXTBUSDIV_4 0x00000200
|
||||||
|
#define PLL_EXTBUSDIV_5 0x00000300
|
||||||
|
/* MAL divisor */
|
||||||
|
#define PLL_MALDIV 0x00000030
|
||||||
|
#define CPC0_PLLMR0_MPDV 0x00000030
|
||||||
|
#define PLL_MALDIV_1 0x00000000
|
||||||
|
#define PLL_MALDIV_2 0x00000010
|
||||||
|
#define PLL_MALDIV_3 0x00000020
|
||||||
|
#define PLL_MALDIV_4 0x00000030
|
||||||
|
/* PCI divisor */
|
||||||
|
#define PLL_PCIDIV 0x00000003
|
||||||
|
#define CPC0_PLLMR0_PPFD 0x00000003
|
||||||
|
#define PLL_PCIDIV_1 0x00000000
|
||||||
|
#define PLL_PCIDIV_2 0x00000001
|
||||||
|
#define PLL_PCIDIV_3 0x00000002
|
||||||
|
#define PLL_PCIDIV_4 0x00000003
|
||||||
|
|
||||||
|
/*
|
||||||
|
* PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
|
||||||
|
* assuming a 33.3MHz input clock to the 405EP.
|
||||||
|
*/
|
||||||
|
#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
|
||||||
|
PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
|
||||||
|
PLL_MALDIV_1 | PLL_PCIDIV_4)
|
||||||
|
#define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \
|
||||||
|
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||||
|
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
||||||
|
|
||||||
|
#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
|
||||||
|
PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
|
||||||
|
PLL_MALDIV_1 | PLL_PCIDIV_4)
|
||||||
|
#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \
|
||||||
|
PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
|
||||||
|
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
||||||
|
#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
|
||||||
|
PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
|
||||||
|
PLL_MALDIV_1 | PLL_PCIDIV_4)
|
||||||
|
#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
|
||||||
|
PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
|
||||||
|
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
||||||
|
#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
|
||||||
|
PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
|
||||||
|
PLL_MALDIV_1 | PLL_PCIDIV_4)
|
||||||
|
#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \
|
||||||
|
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||||
|
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
||||||
|
#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \
|
||||||
|
PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
|
||||||
|
PLL_MALDIV_1 | PLL_PCIDIV_2)
|
||||||
|
#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \
|
||||||
|
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||||
|
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
||||||
|
#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
|
||||||
|
PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
|
||||||
|
PLL_MALDIV_1 | PLL_PCIDIV_3)
|
||||||
|
#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \
|
||||||
|
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||||
|
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
|
||||||
|
#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
|
||||||
|
PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
|
||||||
|
PLL_MALDIV_1 | PLL_PCIDIV_1)
|
||||||
|
#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \
|
||||||
|
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||||
|
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
|
||||||
|
|
||||||
|
#endif /* _PPC405EP_H_ */
|
90
arch/powerpc/include/asm/ppc405ex.h
Normal file
90
arch/powerpc/include/asm/ppc405ex.h
Normal file
@ -0,0 +1,90 @@
|
|||||||
|
/*
|
||||||
|
* (C) Copyright 2010
|
||||||
|
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _PPC405EX_H_
|
||||||
|
#define _PPC405EX_H_
|
||||||
|
|
||||||
|
#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
|
||||||
|
|
||||||
|
#define CONFIG_NAND_NDFC
|
||||||
|
|
||||||
|
/* Memory mapped register */
|
||||||
|
#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */
|
||||||
|
|
||||||
|
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
|
||||||
|
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
|
||||||
|
|
||||||
|
#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0800)
|
||||||
|
|
||||||
|
/* SDR */
|
||||||
|
#define SDR0_SDCS0 0x0060
|
||||||
|
#define SDR0_UART0 0x0120 /* UART0 Config */
|
||||||
|
#define SDR0_UART1 0x0121 /* UART1 Config */
|
||||||
|
#define SDR0_SRST 0x0200
|
||||||
|
#define SDR0_CUST0 0x4000
|
||||||
|
#define SDR0_PFC0 0x4100
|
||||||
|
#define SDR0_PFC1 0x4101
|
||||||
|
#define SDR0_MFR 0x4300 /* SDR0_MFR reg */
|
||||||
|
|
||||||
|
#define SDR0_SDCS_SDD (0x80000000 >> 31)
|
||||||
|
|
||||||
|
#define SDR0_SRST_DMC (0x80000000 >> 10)
|
||||||
|
|
||||||
|
#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
|
||||||
|
#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
|
||||||
|
#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
|
||||||
|
#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
|
||||||
|
|
||||||
|
#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
|
||||||
|
#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
|
||||||
|
#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
|
||||||
|
|
||||||
|
#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
|
||||||
|
#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width= 16 Bit */
|
||||||
|
#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width= 8 Bit */
|
||||||
|
|
||||||
|
#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
|
||||||
|
#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((u32)(n)) & 0xF) << 24)
|
||||||
|
#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((u32)(n)) >> 24) & 0xF)
|
||||||
|
|
||||||
|
#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
|
||||||
|
#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((u32)(n)) & 0x3) << 22)
|
||||||
|
#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((u32)(n)) >> 22) & 0x3)
|
||||||
|
|
||||||
|
#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
|
||||||
|
#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
|
||||||
|
#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
|
||||||
|
|
||||||
|
#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
|
||||||
|
#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
|
||||||
|
#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
|
||||||
|
|
||||||
|
#define SDR0_PFC1_U1ME 0x02000000
|
||||||
|
#define SDR0_PFC1_U0ME 0x00080000
|
||||||
|
#define SDR0_PFC1_U0IM 0x00040000
|
||||||
|
#define SDR0_PFC1_SIS 0x00020000
|
||||||
|
#define SDR0_PFC1_DMAAEN 0x00010000
|
||||||
|
#define SDR0_PFC1_DMADEN 0x00008000
|
||||||
|
#define SDR0_PFC1_USBEN 0x00004000
|
||||||
|
#define SDR0_PFC1_AHBSWAP 0x00000020
|
||||||
|
#define SDR0_PFC1_USBBIGEN 0x00000010
|
||||||
|
#define SDR0_PFC1_GPT_FREQ 0x0000000f
|
||||||
|
|
||||||
|
#endif /* _PPC405EX_H_ */
|
102
arch/powerpc/include/asm/ppc405ez.h
Normal file
102
arch/powerpc/include/asm/ppc405ez.h
Normal file
@ -0,0 +1,102 @@
|
|||||||
|
/*
|
||||||
|
* (C) Copyright 2010
|
||||||
|
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _PPC405EZ_H_
|
||||||
|
#define _PPC405EZ_H_
|
||||||
|
|
||||||
|
#define CONFIG_NAND_NDFC
|
||||||
|
|
||||||
|
/* Memory mapped register */
|
||||||
|
#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */
|
||||||
|
|
||||||
|
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
|
||||||
|
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
|
||||||
|
|
||||||
|
#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
|
||||||
|
#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0800)
|
||||||
|
|
||||||
|
/* DCR register */
|
||||||
|
#define OCM0_PLBCR1 0x0020 /* OCM PLB3 Bank 1 Config */
|
||||||
|
#define OCM0_PLBCR2 0x0021 /* OCM PLB3 Bank 2 Config */
|
||||||
|
#define OCM0_PLBBEAR 0x0022 /* OCM PLB3 Bus Error Add */
|
||||||
|
#define OCM0_DSRC1 0x0028 /* OCM D-side Bank 1 Config */
|
||||||
|
#define OCM0_DSRC2 0x0029 /* OCM D-side Bank 2 Config */
|
||||||
|
#define OCM0_ISRC1 0x002A /* OCM I-side Bank 1Config */
|
||||||
|
#define OCM0_ISRC2 0x002B /* OCM I-side Bank 2 Config */
|
||||||
|
#define OCM0_DISDPC 0x002C /* OCM D-/I-side Data Par Chk */
|
||||||
|
|
||||||
|
/* SDR register */
|
||||||
|
#define SDR0_NAND0 0x4000
|
||||||
|
#define SDR0_ULTRA0 0x4040
|
||||||
|
#define SDR0_ULTRA1 0x4050
|
||||||
|
#define SDR0_ICINTSTAT 0x4510
|
||||||
|
|
||||||
|
/* CPR register */
|
||||||
|
#define CPR0_PRIMAD 0x0080
|
||||||
|
#define CPR0_PERD0 0x00e0
|
||||||
|
#define CPR0_PERD1 0x00e1
|
||||||
|
#define CPR0_PERC0 0x0180
|
||||||
|
|
||||||
|
#define MAL_DCR_BASE 0x380
|
||||||
|
|
||||||
|
#define SDR_NAND0_NDEN 0x80000000
|
||||||
|
#define SDR_NAND0_NDBTEN 0x40000000
|
||||||
|
#define SDR_NAND0_NDBADR_MASK 0x30000000
|
||||||
|
#define SDR_NAND0_NDBPG_MASK 0x0f000000
|
||||||
|
#define SDR_NAND0_NDAREN 0x00800000
|
||||||
|
#define SDR_NAND0_NDRBEN 0x00400000
|
||||||
|
|
||||||
|
#define SDR_ULTRA0_NDGPIOBP 0x80000000
|
||||||
|
#define SDR_ULTRA0_CSN_MASK 0x78000000
|
||||||
|
#define SDR_ULTRA0_CSNSEL0 0x40000000
|
||||||
|
#define SDR_ULTRA0_CSNSEL1 0x20000000
|
||||||
|
#define SDR_ULTRA0_CSNSEL2 0x10000000
|
||||||
|
#define SDR_ULTRA0_CSNSEL3 0x08000000
|
||||||
|
#define SDR_ULTRA0_EBCRDYEN 0x04000000
|
||||||
|
#define SDR_ULTRA0_SPISSINEN 0x02000000
|
||||||
|
#define SDR_ULTRA0_NFSRSTEN 0x01000000
|
||||||
|
|
||||||
|
#define SDR_ULTRA1_LEDNENABLE 0x40000000
|
||||||
|
|
||||||
|
#define SDR_ICRX_STAT 0x80000000
|
||||||
|
#define SDR_ICTX0_STAT 0x40000000
|
||||||
|
#define SDR_ICTX1_STAT 0x20000000
|
||||||
|
|
||||||
|
#define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */
|
||||||
|
#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */
|
||||||
|
#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
|
||||||
|
|
||||||
|
#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
|
||||||
|
|
||||||
|
#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
|
||||||
|
#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */
|
||||||
|
#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */
|
||||||
|
|
||||||
|
#define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */
|
||||||
|
#define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */
|
||||||
|
#define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */
|
||||||
|
#define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */
|
||||||
|
|
||||||
|
#define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */
|
||||||
|
#define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */
|
||||||
|
#define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */
|
||||||
|
#define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */
|
||||||
|
|
||||||
|
#endif /* _PPC405EZ_H_ */
|
108
arch/powerpc/include/asm/ppc405gp.h
Normal file
108
arch/powerpc/include/asm/ppc405gp.h
Normal file
@ -0,0 +1,108 @@
|
|||||||
|
/*
|
||||||
|
* (C) Copyright 2010
|
||||||
|
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _PPC405GP_H_
|
||||||
|
#define _PPC405GP_H_
|
||||||
|
|
||||||
|
#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */
|
||||||
|
|
||||||
|
/* Memory mapped register */
|
||||||
|
#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */
|
||||||
|
|
||||||
|
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
|
||||||
|
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
|
||||||
|
|
||||||
|
#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
|
||||||
|
|
||||||
|
/* DCR's */
|
||||||
|
#define DCP0_CFGADDR 0x0014 /* Decompression controller addr reg */
|
||||||
|
#define DCP0_CFGDATA 0x0015 /* Decompression controller data reg */
|
||||||
|
#define OCM0_ISCNTL 0x0019 /* OCM I-side control reg */
|
||||||
|
#define OCM0_DSARC 0x001a /* OCM D-side address compare */
|
||||||
|
#define OCM0_DSCNTL 0x001b /* OCM D-side control */
|
||||||
|
#define CPC0_PLLMR 0x00b0 /* PLL mode register */
|
||||||
|
#define CPC0_CR0 0x00b1 /* chip control register 0 */
|
||||||
|
#define CPC0_CR1 0x00b2 /* chip control register 1 */
|
||||||
|
#define CPC0_PSR 0x00b4 /* chip pin strapping reg */
|
||||||
|
#define CPC0_EIRR 0x00b6 /* ext interrupt routing reg */
|
||||||
|
#define CPC0_SR 0x00b8 /* Power management status */
|
||||||
|
#define CPC0_ER 0x00b9 /* Power management enable */
|
||||||
|
#define CPC0_FR 0x00ba /* Power management force */
|
||||||
|
#define CPC0_ECR 0x00aa /* edge conditioner register */
|
||||||
|
|
||||||
|
/* values for kiar register - indirect addressing of these regs */
|
||||||
|
#define KCONF 0x40 /* decompression core config register */
|
||||||
|
|
||||||
|
#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */
|
||||||
|
#define PLLMR_FWD_DIV_BYPASS 0xE0000000
|
||||||
|
#define PLLMR_FWD_DIV_3 0xA0000000
|
||||||
|
#define PLLMR_FWD_DIV_4 0x80000000
|
||||||
|
#define PLLMR_FWD_DIV_6 0x40000000
|
||||||
|
|
||||||
|
#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */
|
||||||
|
#define PLLMR_FB_DIV_1 0x02000000
|
||||||
|
#define PLLMR_FB_DIV_2 0x04000000
|
||||||
|
#define PLLMR_FB_DIV_3 0x06000000
|
||||||
|
#define PLLMR_FB_DIV_4 0x08000000
|
||||||
|
|
||||||
|
#define PLLMR_TUNING_MASK 0x01F80000
|
||||||
|
|
||||||
|
#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */
|
||||||
|
#define PLLMR_CPU_PLB_DIV_1 0x00000000
|
||||||
|
#define PLLMR_CPU_PLB_DIV_2 0x00020000
|
||||||
|
#define PLLMR_CPU_PLB_DIV_3 0x00040000
|
||||||
|
#define PLLMR_CPU_PLB_DIV_4 0x00060000
|
||||||
|
|
||||||
|
#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */
|
||||||
|
#define PLLMR_OPB_PLB_DIV_1 0x00000000
|
||||||
|
#define PLLMR_OPB_PLB_DIV_2 0x00008000
|
||||||
|
#define PLLMR_OPB_PLB_DIV_3 0x00010000
|
||||||
|
#define PLLMR_OPB_PLB_DIV_4 0x00018000
|
||||||
|
|
||||||
|
#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */
|
||||||
|
#define PLLMR_PCI_PLB_DIV_1 0x00000000
|
||||||
|
#define PLLMR_PCI_PLB_DIV_2 0x00002000
|
||||||
|
#define PLLMR_PCI_PLB_DIV_3 0x00004000
|
||||||
|
#define PLLMR_PCI_PLB_DIV_4 0x00006000
|
||||||
|
|
||||||
|
#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */
|
||||||
|
#define PLLMR_EXB_PLB_DIV_2 0x00000000
|
||||||
|
#define PLLMR_EXB_PLB_DIV_3 0x00000800
|
||||||
|
#define PLLMR_EXB_PLB_DIV_4 0x00001000
|
||||||
|
#define PLLMR_EXB_PLB_DIV_5 0x00001800
|
||||||
|
|
||||||
|
/* definitions for PPC405GPr (new mode strapping) */
|
||||||
|
#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */
|
||||||
|
|
||||||
|
#define PSR_PLL_FWD_MASK 0xC0000000
|
||||||
|
#define PSR_PLL_FDBACK_MASK 0x30000000
|
||||||
|
#define PSR_PLL_TUNING_MASK 0x0E000000
|
||||||
|
#define PSR_PLB_CPU_MASK 0x01800000
|
||||||
|
#define PSR_OPB_PLB_MASK 0x00600000
|
||||||
|
#define PSR_PCI_PLB_MASK 0x00180000
|
||||||
|
#define PSR_EB_PLB_MASK 0x00060000
|
||||||
|
#define PSR_ROM_WIDTH_MASK 0x00018000
|
||||||
|
#define PSR_ROM_LOC 0x00004000
|
||||||
|
#define PSR_PCI_ASYNC_EN 0x00001000
|
||||||
|
#define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */
|
||||||
|
#define PSR_PCI_ARBIT_EN 0x00000400
|
||||||
|
#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */
|
||||||
|
|
||||||
|
#endif /* _PPC405GP_H_ */
|
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue
Block a user