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zynq: Enable axi ethernet and emaclite driver initialization

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Zynq can have axi ethernet and emaclite IPs in programmable
logic.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
This commit is contained in:
Michal Simek 2013-07-25 15:47:16 +02:00
parent 39523bef29
commit 2d83d33a51
1 changed files with 17 additions and 0 deletions
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17
board/xilinx/zynq/board.c
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@ -61,6 +61,23 @@ int board_eth_init(bd_t *bis)
{
u32 ret = 0;
#ifdef CONFIG_XILINX_AXIEMAC
ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
XILINX_AXIDMA_BASEADDR);
#endif
#ifdef CONFIG_XILINX_EMACLITE
u32 txpp = 0;
u32 rxpp = 0;
# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
txpp = 1;
# endif
# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
rxpp = 1;
# endif
ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
txpp, rxpp);
#endif
#if defined(CONFIG_ZYNQ_GEM)
# if defined(CONFIG_ZYNQ_GEM0)
ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,