mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-29 16:10:24 +09:00
Merge branch '2019-12-26-ti-imports'
- Update maintainer on omapl138_lcdk - Match TRM sequence & settings in the TI pipe3 PHY
This commit is contained in:
commit
2ce1dbbeec
@ -8,7 +8,7 @@ F: configs/da850evm_nand_defconfig
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|||||||
F: configs/da850evm_direct_nor_defconfig
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F: configs/da850evm_direct_nor_defconfig
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OMAPL138_LCDK BOARD
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OMAPL138_LCDK BOARD
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||||||
M: Peter Howard <phoward@gme.net.au>
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M: Lokesh Vutla <lokeshvutla@ti.com>
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S: Maintained
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S: Maintained
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||||||
F: include/configs/omap1l38_lcdk.h
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F: include/configs/omap1l38_lcdk.h
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F: configs/omapl138_lcdk_defconfig
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F: configs/omapl138_lcdk_defconfig
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@ -41,27 +41,110 @@
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#define SATA_PLL_SOFT_RESET (1<<18)
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#define SATA_PLL_SOFT_RESET (1<<18)
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/* PHY POWER CONTROL Register */
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/* PHY POWER CONTROL Register */
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#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000
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#define PIPE3_PHY_PWRCTL_CLK_CMD_MASK GENMASK(21, 14)
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#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE
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#define PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 14
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#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000
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#define PIPE3_PHY_PWRCTL_CLK_FREQ_MASK GENMASK(31, 22)
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#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16
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#define PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 22
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#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3
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#define PIPE3_PHY_RX_POWERON (0x1 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT)
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#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0
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#define PIPE3_PHY_TX_POWERON (0x2 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT)
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/* PHY RX Registers */
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#define PIPE3_PHY_RX_ANA_PROGRAMMABILITY 0x0000000C
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#define INTERFACE_MASK GENMASK(31, 27)
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#define INTERFACE_SHIFT 27
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#define INTERFACE_MODE_USBSS BIT(4)
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#define INTERFACE_MODE_SATA_1P5 BIT(3)
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#define INTERFACE_MODE_SATA_3P0 BIT(2)
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#define INTERFACE_MODE_PCIE BIT(0)
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#define LOSD_MASK GENMASK(17, 14)
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#define LOSD_SHIFT 14
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#define MEM_PLLDIV GENMASK(6, 5)
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#define PIPE3_PHY_RX_TRIM 0x0000001C
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#define MEM_DLL_TRIM_SEL_MASK GENMASK(31, 30)
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#define MEM_DLL_TRIM_SHIFT 30
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#define PIPE3_PHY_RX_DLL 0x00000024
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#define MEM_DLL_PHINT_RATE_MASK GENMASK(31, 30)
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#define MEM_DLL_PHINT_RATE_SHIFT 30
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#define PIPE3_PHY_RX_DIGITAL_MODES 0x00000028
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#define MEM_HS_RATE_MASK GENMASK(28, 27)
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#define MEM_HS_RATE_SHIFT 27
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#define MEM_OVRD_HS_RATE BIT(26)
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#define MEM_OVRD_HS_RATE_SHIFT 26
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#define MEM_CDR_FASTLOCK BIT(23)
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#define MEM_CDR_FASTLOCK_SHIFT 23
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#define MEM_CDR_LBW_MASK GENMASK(22, 21)
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#define MEM_CDR_LBW_SHIFT 21
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#define MEM_CDR_STEPCNT_MASK GENMASK(20, 19)
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#define MEM_CDR_STEPCNT_SHIFT 19
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#define MEM_CDR_STL_MASK GENMASK(18, 16)
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#define MEM_CDR_STL_SHIFT 16
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#define MEM_CDR_THR_MASK GENMASK(15, 13)
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#define MEM_CDR_THR_SHIFT 13
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#define MEM_CDR_THR_MODE BIT(12)
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#define MEM_CDR_THR_MODE_SHIFT 12
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#define MEM_CDR_2NDO_SDM_MODE BIT(11)
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#define MEM_CDR_2NDO_SDM_MODE_SHIFT 11
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#define PIPE3_PHY_RX_EQUALIZER 0x00000038
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#define MEM_EQLEV_MASK GENMASK(31, 16)
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#define MEM_EQLEV_SHIFT 16
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#define MEM_EQFTC_MASK GENMASK(15, 11)
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#define MEM_EQFTC_SHIFT 11
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#define MEM_EQCTL_MASK GENMASK(10, 7)
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#define MEM_EQCTL_SHIFT 7
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#define MEM_OVRD_EQLEV BIT(2)
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#define MEM_OVRD_EQLEV_SHIFT 2
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#define MEM_OVRD_EQFTC BIT(1)
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#define MEM_OVRD_EQFTC_SHIFT 1
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#define SATA_PHY_RX_IO_AND_A2D_OVERRIDES 0x44
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#define MEM_CDR_LOS_SOURCE_MASK GENMASK(10, 9)
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#define MEM_CDR_LOS_SOURCE_SHIFT 9
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#define PLL_IDLE_TIME 100 /* in milliseconds */
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#define PLL_IDLE_TIME 100 /* in milliseconds */
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#define PLL_LOCK_TIME 100 /* in milliseconds */
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#define PLL_LOCK_TIME 100 /* in milliseconds */
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enum pipe3_mode { PIPE3_MODE_PCIE = 1,
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PIPE3_MODE_SATA,
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PIPE3_MODE_USBSS };
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struct pipe3_settings {
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u8 ana_interface;
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u8 ana_losd;
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u8 dig_fastlock;
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u8 dig_lbw;
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u8 dig_stepcnt;
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u8 dig_stl;
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u8 dig_thr;
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u8 dig_thr_mode;
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u8 dig_2ndo_sdm_mode;
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u8 dig_hs_rate;
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u8 dig_ovrd_hs_rate;
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u8 dll_trim_sel;
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u8 dll_phint_rate;
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u8 eq_lev;
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u8 eq_ftc;
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u8 eq_ctl;
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u8 eq_ovrd_lev;
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u8 eq_ovrd_ftc;
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};
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struct omap_pipe3 {
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struct omap_pipe3 {
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void __iomem *pll_ctrl_base;
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void __iomem *pll_ctrl_base;
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void __iomem *phy_rx;
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void __iomem *power_reg;
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void __iomem *power_reg;
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void __iomem *pll_reset_reg;
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void __iomem *pll_reset_reg;
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struct pipe3_dpll_map *dpll_map;
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struct pipe3_dpll_map *dpll_map;
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enum pipe3_mode mode;
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struct pipe3_settings settings;
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};
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};
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struct pipe3_dpll_params {
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struct pipe3_dpll_params {
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u16 m;
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u16 m;
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u8 n;
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u8 n;
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@ -75,6 +158,12 @@ struct pipe3_dpll_map {
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struct pipe3_dpll_params params;
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struct pipe3_dpll_params params;
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};
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};
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struct pipe3_data {
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enum pipe3_mode mode;
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struct pipe3_dpll_map *dpll_map;
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struct pipe3_settings settings;
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};
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static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset)
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static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset)
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{
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{
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return readl(addr + offset);
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return readl(addr + offset);
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@ -175,19 +264,75 @@ static void omap_control_pipe3_power(struct omap_pipe3 *pipe3, int on)
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rate = rate/1000000;
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rate = rate/1000000;
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if (on) {
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if (on) {
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val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
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val &= ~(PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
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OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
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PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
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val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<
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val |= rate << PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
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OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
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writel(val, pipe3->power_reg);
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val |= rate <<
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OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
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} else {
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val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
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val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<
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OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
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}
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writel(val, pipe3->power_reg);
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/* Power up TX before RX for SATA & USB */
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val |= PIPE3_PHY_TX_POWERON;
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writel(val, pipe3->power_reg);
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val |= PIPE3_PHY_RX_POWERON;
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writel(val, pipe3->power_reg);
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} else {
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val &= ~PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
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writel(val, pipe3->power_reg);
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}
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}
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static void ti_pipe3_calibrate(struct omap_pipe3 *phy)
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{
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u32 val;
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struct pipe3_settings *s = &phy->settings;
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val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY);
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val &= ~(INTERFACE_MASK | LOSD_MASK | MEM_PLLDIV);
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val = (s->ana_interface << INTERFACE_SHIFT | s->ana_losd << LOSD_SHIFT);
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omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY, val);
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val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES);
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val &= ~(MEM_HS_RATE_MASK | MEM_OVRD_HS_RATE | MEM_CDR_FASTLOCK |
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MEM_CDR_LBW_MASK | MEM_CDR_STEPCNT_MASK | MEM_CDR_STL_MASK |
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MEM_CDR_THR_MASK | MEM_CDR_THR_MODE | MEM_CDR_2NDO_SDM_MODE);
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val |= s->dig_hs_rate << MEM_HS_RATE_SHIFT |
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s->dig_ovrd_hs_rate << MEM_OVRD_HS_RATE_SHIFT |
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s->dig_fastlock << MEM_CDR_FASTLOCK_SHIFT |
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s->dig_lbw << MEM_CDR_LBW_SHIFT |
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s->dig_stepcnt << MEM_CDR_STEPCNT_SHIFT |
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s->dig_stl << MEM_CDR_STL_SHIFT |
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s->dig_thr << MEM_CDR_THR_SHIFT |
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s->dig_thr_mode << MEM_CDR_THR_MODE_SHIFT |
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s->dig_2ndo_sdm_mode << MEM_CDR_2NDO_SDM_MODE_SHIFT;
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omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES, val);
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val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_TRIM);
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val &= ~MEM_DLL_TRIM_SEL_MASK;
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val |= s->dll_trim_sel << MEM_DLL_TRIM_SHIFT;
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omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_TRIM, val);
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val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DLL);
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val &= ~MEM_DLL_PHINT_RATE_MASK;
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val |= s->dll_phint_rate << MEM_DLL_PHINT_RATE_SHIFT;
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omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DLL, val);
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val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER);
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val &= ~(MEM_EQLEV_MASK | MEM_EQFTC_MASK | MEM_EQCTL_MASK |
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MEM_OVRD_EQLEV | MEM_OVRD_EQFTC);
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val |= s->eq_lev << MEM_EQLEV_SHIFT |
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s->eq_ftc << MEM_EQFTC_SHIFT |
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s->eq_ctl << MEM_EQCTL_SHIFT |
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s->eq_ovrd_lev << MEM_OVRD_EQLEV_SHIFT |
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s->eq_ovrd_ftc << MEM_OVRD_EQFTC_SHIFT;
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omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER, val);
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if (phy->mode == PIPE3_MODE_SATA) {
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val = omap_pipe3_readl(phy->phy_rx,
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SATA_PHY_RX_IO_AND_A2D_OVERRIDES);
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val &= ~MEM_CDR_LOS_SOURCE_MASK;
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omap_pipe3_writel(phy->phy_rx, SATA_PHY_RX_IO_AND_A2D_OVERRIDES,
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val);
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}
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}
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}
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static int pipe3_init(struct phy *phy)
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static int pipe3_init(struct phy *phy)
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@ -202,6 +347,8 @@ static int pipe3_init(struct phy *phy)
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ret = omap_pipe3_dpll_program(pipe3);
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ret = omap_pipe3_dpll_program(pipe3);
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if (ret)
|
if (ret)
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return ret;
|
return ret;
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ti_pipe3_calibrate(pipe3);
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} else {
|
} else {
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/* else just bring it out of IDLE mode */
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/* else just bring it out of IDLE mode */
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val = omap_pipe3_readl(pipe3->pll_ctrl_base,
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val = omap_pipe3_readl(pipe3->pll_ctrl_base,
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@ -317,7 +464,22 @@ static int pipe3_phy_probe(struct udevice *dev)
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fdt_addr_t addr;
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fdt_addr_t addr;
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fdt_size_t sz;
|
fdt_size_t sz;
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struct omap_pipe3 *pipe3 = dev_get_priv(dev);
|
struct omap_pipe3 *pipe3 = dev_get_priv(dev);
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struct pipe3_data *data;
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/* PHY_RX */
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addr = devfdt_get_addr_size_index(dev, 0, &sz);
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|
if (addr == FDT_ADDR_T_NONE) {
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pr_err("missing phy_rx address\n");
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return -EINVAL;
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|
}
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|
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pipe3->phy_rx = map_physmem(addr, sz, MAP_NOCACHE);
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|
if (!pipe3->phy_rx) {
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|
pr_err("unable to remap phy_rx\n");
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|
return -EINVAL;
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|
}
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|
/* PLLCTRL */
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addr = devfdt_get_addr_size_index(dev, 2, &sz);
|
addr = devfdt_get_addr_size_index(dev, 2, &sz);
|
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if (addr == FDT_ADDR_T_NONE) {
|
if (addr == FDT_ADDR_T_NONE) {
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pr_err("missing pll ctrl address\n");
|
pr_err("missing pll ctrl address\n");
|
||||||
@ -334,25 +496,28 @@ static int pipe3_phy_probe(struct udevice *dev)
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|||||||
if (!pipe3->power_reg)
|
if (!pipe3->power_reg)
|
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return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
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if (device_is_compatible(dev, "ti,phy-pipe3-sata")) {
|
data = (struct pipe3_data *)dev_get_driver_data(dev);
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|
pipe3->mode = data->mode;
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|
pipe3->dpll_map = data->dpll_map;
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|
pipe3->settings = data->settings;
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|
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||||||
|
if (pipe3->mode == PIPE3_MODE_SATA) {
|
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pipe3->pll_reset_reg = get_reg(dev, "syscon-pllreset");
|
pipe3->pll_reset_reg = get_reg(dev, "syscon-pllreset");
|
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if (!pipe3->pll_reset_reg)
|
if (!pipe3->pll_reset_reg)
|
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return -EINVAL;
|
return -EINVAL;
|
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}
|
}
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||||||
|
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||||||
pipe3->dpll_map = (struct pipe3_dpll_map *)dev_get_driver_data(dev);
|
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct pipe3_dpll_map dpll_map_sata[] = {
|
static struct pipe3_dpll_map dpll_map_sata[] = {
|
||||||
{12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */
|
{12000000, {625, 4, 4, 6, 0} }, /* 12 MHz */
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{16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
|
{16800000, {625, 6, 4, 7, 0} }, /* 16.8 MHz */
|
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{19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
|
{19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
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{20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */
|
{20000000, {750, 9, 4, 6, 0} }, /* 20 MHz */
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{26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */
|
{26000000, {750, 12, 4, 6, 0} }, /* 26 MHz */
|
||||||
{38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
|
{38400000, {625, 15, 4, 6, 0} }, /* 38.4 MHz */
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||||||
{ }, /* Terminator */
|
{ }, /* Terminator */
|
||||||
};
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};
|
||||||
|
|
||||||
static struct pipe3_dpll_map dpll_map_usb[] = {
|
static struct pipe3_dpll_map dpll_map_usb[] = {
|
||||||
@ -365,9 +530,61 @@ static struct pipe3_dpll_map dpll_map_usb[] = {
|
|||||||
{ }, /* Terminator */
|
{ }, /* Terminator */
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static struct pipe3_data data_usb = {
|
||||||
|
.mode = PIPE3_MODE_USBSS,
|
||||||
|
.dpll_map = dpll_map_usb,
|
||||||
|
.settings = {
|
||||||
|
/* DRA75x TRM Table 26-17. Preferred USB3_PHY_RX SCP Register Settings */
|
||||||
|
.ana_interface = INTERFACE_MODE_USBSS,
|
||||||
|
.ana_losd = 0xa,
|
||||||
|
.dig_fastlock = 1,
|
||||||
|
.dig_lbw = 3,
|
||||||
|
.dig_stepcnt = 0,
|
||||||
|
.dig_stl = 0x3,
|
||||||
|
.dig_thr = 1,
|
||||||
|
.dig_thr_mode = 1,
|
||||||
|
.dig_2ndo_sdm_mode = 0,
|
||||||
|
.dig_hs_rate = 0,
|
||||||
|
.dig_ovrd_hs_rate = 1,
|
||||||
|
.dll_trim_sel = 0x2,
|
||||||
|
.dll_phint_rate = 0x3,
|
||||||
|
.eq_lev = 0,
|
||||||
|
.eq_ftc = 0,
|
||||||
|
.eq_ctl = 0x9,
|
||||||
|
.eq_ovrd_lev = 0,
|
||||||
|
.eq_ovrd_ftc = 0,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct pipe3_data data_sata = {
|
||||||
|
.mode = PIPE3_MODE_SATA,
|
||||||
|
.dpll_map = dpll_map_sata,
|
||||||
|
.settings = {
|
||||||
|
/* DRA75x TRM Table 26-9. Preferred SATA_PHY_RX SCP Register Settings */
|
||||||
|
.ana_interface = INTERFACE_MODE_SATA_3P0,
|
||||||
|
.ana_losd = 0x5,
|
||||||
|
.dig_fastlock = 1,
|
||||||
|
.dig_lbw = 3,
|
||||||
|
.dig_stepcnt = 0,
|
||||||
|
.dig_stl = 0x3,
|
||||||
|
.dig_thr = 1,
|
||||||
|
.dig_thr_mode = 1,
|
||||||
|
.dig_2ndo_sdm_mode = 0,
|
||||||
|
.dig_hs_rate = 0, /* Not in TRM preferred settings */
|
||||||
|
.dig_ovrd_hs_rate = 0, /* Not in TRM preferred settings */
|
||||||
|
.dll_trim_sel = 0x1,
|
||||||
|
.dll_phint_rate = 0x2, /* for 1.5 GHz DPLL clock */
|
||||||
|
.eq_lev = 0,
|
||||||
|
.eq_ftc = 0x1f,
|
||||||
|
.eq_ctl = 0,
|
||||||
|
.eq_ovrd_lev = 1,
|
||||||
|
.eq_ovrd_ftc = 1,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
static const struct udevice_id pipe3_phy_ids[] = {
|
static const struct udevice_id pipe3_phy_ids[] = {
|
||||||
{ .compatible = "ti,phy-pipe3-sata", .data = (ulong)&dpll_map_sata },
|
{ .compatible = "ti,phy-pipe3-sata", .data = (ulong)&data_sata },
|
||||||
{ .compatible = "ti,omap-usb3", .data = (ulong)&dpll_map_usb},
|
{ .compatible = "ti,omap-usb3", .data = (ulong)&data_usb},
|
||||||
{ }
|
{ }
|
||||||
};
|
};
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user