mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
imx: mx6slevk: introduce device tree support
Introduce device tree support. dts from kernel commit c4f3f22edd Merge tag 'linux-kselftest-4.11-rc1' Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
parent
6b2781f679
commit
2cc416a836
|
@ -311,6 +311,7 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
|
|||
dtb-$(CONFIG_MX53) += imx53-cx9020.dtb
|
||||
|
||||
dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
|
||||
imx6sl-evk.dtb \
|
||||
imx6sll-evk.dtb \
|
||||
imx6dl-icore.dtb \
|
||||
imx6dl-icore-rqs.dtb \
|
||||
|
|
641
arch/arm/dts/imx6sl-evk.dts
Normal file
641
arch/arm/dts/imx6sl-evk.dts
Normal file
|
@ -0,0 +1,641 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include "imx6sl.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX6 SoloLite EVK Board";
|
||||
compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
|
||||
|
||||
memory {
|
||||
reg = <0x80000000 0x40000000>;
|
||||
};
|
||||
|
||||
backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm1 0 5000000>;
|
||||
brightness-levels = <0 4 8 16 32 64 128 255>;
|
||||
default-brightness-level = <6>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_led>;
|
||||
|
||||
user {
|
||||
label = "debug";
|
||||
gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg_usb_otg1_vbus: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "usb_otg1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio4 0 0>;
|
||||
enable-active-high;
|
||||
vin-supply = <&swbst_reg>;
|
||||
};
|
||||
|
||||
reg_usb_otg2_vbus: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
regulator-name = "usb_otg2_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio4 2 0>;
|
||||
enable-active-high;
|
||||
vin-supply = <&swbst_reg>;
|
||||
};
|
||||
|
||||
reg_aud3v: regulator@2 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <2>;
|
||||
regulator-name = "wm8962-supply-3v15";
|
||||
regulator-min-microvolt = <3150000>;
|
||||
regulator-max-microvolt = <3150000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
reg_aud4v: regulator@3 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <3>;
|
||||
regulator-name = "wm8962-supply-4v2";
|
||||
regulator-min-microvolt = <4325000>;
|
||||
regulator-max-microvolt = <4325000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
reg_lcd_3v3: regulator@4 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <4>;
|
||||
regulator-name = "lcd-3v3";
|
||||
gpio = <&gpio4 3 0>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962";
|
||||
model = "wm8962-audio";
|
||||
ssi-controller = <&ssi2>;
|
||||
audio-codec = <&codec>;
|
||||
audio-routing =
|
||||
"Headphone Jack", "HPOUTL",
|
||||
"Headphone Jack", "HPOUTR",
|
||||
"Ext Spk", "SPKOUTL",
|
||||
"Ext Spk", "SPKOUTR",
|
||||
"AMIC", "MICBIAS",
|
||||
"IN3R", "AMIC";
|
||||
mux-int-port = <2>;
|
||||
mux-ext-port = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
&audmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_audmux3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ecspi1 {
|
||||
cs-gpios = <&gpio4 11 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1>;
|
||||
status = "okay";
|
||||
|
||||
flash: m25p80@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,m25p32", "jedec,spi-nor";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&pinctrl_fec>;
|
||||
pinctrl-1 = <&pinctrl_fec_sleep>;
|
||||
phy-mode = "rmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
|
||||
pmic: pfuze100@08 {
|
||||
compatible = "fsl,pfuze100";
|
||||
reg = <0x08>;
|
||||
|
||||
regulators {
|
||||
sw1a_reg: sw1ab {
|
||||
regulator-min-microvolt = <300000>;
|
||||
regulator-max-microvolt = <1875000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <6250>;
|
||||
};
|
||||
|
||||
sw1c_reg: sw1c {
|
||||
regulator-min-microvolt = <300000>;
|
||||
regulator-max-microvolt = <1875000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <6250>;
|
||||
};
|
||||
|
||||
sw2_reg: sw2 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw3a_reg: sw3a {
|
||||
regulator-min-microvolt = <400000>;
|
||||
regulator-max-microvolt = <1975000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw3b_reg: sw3b {
|
||||
regulator-min-microvolt = <400000>;
|
||||
regulator-max-microvolt = <1975000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw4_reg: sw4 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
swbst_reg: swbst {
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5150000>;
|
||||
};
|
||||
|
||||
snvs_reg: vsnvs {
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vref_reg: vrefddr {
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen1_reg: vgen1 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1550000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen2_reg: vgen2 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1550000>;
|
||||
};
|
||||
|
||||
vgen3_reg: vgen3 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vgen4_reg: vgen4 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen5_reg: vgen5 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen6_reg: vgen6 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
|
||||
codec: wm8962@1a {
|
||||
compatible = "wlf,wm8962";
|
||||
reg = <0x1a>;
|
||||
clocks = <&clks IMX6SL_CLK_EXTERN_AUDIO>;
|
||||
DCVDD-supply = <&vgen3_reg>;
|
||||
DBVDD-supply = <®_aud3v>;
|
||||
AVDD-supply = <&vgen3_reg>;
|
||||
CPVDD-supply = <&vgen3_reg>;
|
||||
MICVDD-supply = <®_aud3v>;
|
||||
PLLVDD-supply = <&vgen3_reg>;
|
||||
SPKVDD1-supply = <®_aud4v>;
|
||||
SPKVDD2-supply = <®_aud4v>;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
imx6sl-evk {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x17059
|
||||
MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x17059
|
||||
MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x17059
|
||||
MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x17059
|
||||
MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
|
||||
MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000
|
||||
MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000
|
||||
MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_audmux3: audmux3grp {
|
||||
fsl,pins = <
|
||||
MX6SL_PAD_AUD_RXD__AUD3_RXD 0x4130b0
|
||||
MX6SL_PAD_AUD_TXC__AUD3_TXC 0x4130b0
|
||||
MX6SL_PAD_AUD_TXD__AUD3_TXD 0x4110b0
|
||||
MX6SL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
|
||||
MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
|
||||
MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
|
||||
MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0
|
||||
MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0
|
||||
MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0
|
||||
MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0
|
||||
MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0
|
||||
MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0
|
||||
MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0
|
||||
MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0
|
||||
MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_fec_sleep: fecgrp-sleep {
|
||||
fsl,pins = <
|
||||
MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x3080
|
||||
MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x3080
|
||||
MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x3080
|
||||
MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x3080
|
||||
MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x3080
|
||||
MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x3080
|
||||
MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x3080
|
||||
MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x3080
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1
|
||||
MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001b8b1
|
||||
MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_kpp: kppgrp {
|
||||
fsl,pins = <
|
||||
MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010
|
||||
MX6SL_PAD_KEY_ROW1__KEY_ROW1 0x1b010
|
||||
MX6SL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b0
|
||||
MX6SL_PAD_KEY_COL0__KEY_COL0 0x110b0
|
||||
MX6SL_PAD_KEY_COL1__KEY_COL1 0x110b0
|
||||
MX6SL_PAD_KEY_COL2__KEY_COL2 0x110b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lcd: lcdgrp {
|
||||
fsl,pins = <
|
||||
MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0
|
||||
MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0
|
||||
MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1b0b0
|
||||
MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1b0b0
|
||||
MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1b0b0
|
||||
MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1b0b0
|
||||
MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x1b0b0
|
||||
MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x1b0b0
|
||||
MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x1b0b0
|
||||
MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x1b0b0
|
||||
MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b0b0
|
||||
MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1b0b0
|
||||
MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1b0b0
|
||||
MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1b0b0
|
||||
MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1b0b0
|
||||
MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1b0b0
|
||||
MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1b0b0
|
||||
MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1b0b0
|
||||
MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1b0b0
|
||||
MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1b0b0
|
||||
MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1b0b0
|
||||
MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0
|
||||
MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0
|
||||
MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0
|
||||
MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0
|
||||
MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0
|
||||
MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0
|
||||
MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_led: ledgrp {
|
||||
fsl,pins = <
|
||||
MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm1: pwmgrp {
|
||||
fsl,pins = <
|
||||
MX6SL_PAD_PWM1__PWM1_OUT 0x110b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
|
||||
MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg1: usbotg1grp {
|
||||
fsl,pins = <
|
||||
MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059
|
||||
MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059
|
||||
MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
|
||||
MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
|
||||
MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
|
||||
MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
|
||||
MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
|
||||
MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
|
||||
MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
|
||||
MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
|
||||
fsl,pins = <
|
||||
MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9
|
||||
MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9
|
||||
MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9
|
||||
MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9
|
||||
MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9
|
||||
MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9
|
||||
MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9
|
||||
MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9
|
||||
MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9
|
||||
MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
|
||||
fsl,pins = <
|
||||
MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9
|
||||
MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9
|
||||
MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
|
||||
MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
|
||||
MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
|
||||
MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
|
||||
MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9
|
||||
MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9
|
||||
MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9
|
||||
MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
|
||||
MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059
|
||||
MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
|
||||
MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
|
||||
MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
|
||||
MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
|
||||
fsl,pins = <
|
||||
MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9
|
||||
MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9
|
||||
MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
|
||||
MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
|
||||
MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
|
||||
MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
|
||||
fsl,pins = <
|
||||
MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9
|
||||
MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9
|
||||
MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
|
||||
MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
|
||||
MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
|
||||
MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059
|
||||
MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059
|
||||
MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
||||
MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
||||
MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
||||
MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
|
||||
fsl,pins = <
|
||||
MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
|
||||
MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9
|
||||
MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
|
||||
MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
|
||||
MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
|
||||
MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
|
||||
fsl,pins = <
|
||||
MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
|
||||
MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9
|
||||
MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
|
||||
MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
|
||||
MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
|
||||
MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&kpp {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_kpp>;
|
||||
linux,keymap = <
|
||||
MATRIX_KEY(0x0, 0x0, KEY_UP) /* ROW0, COL0 */
|
||||
MATRIX_KEY(0x0, 0x1, KEY_DOWN) /* ROW0, COL1 */
|
||||
MATRIX_KEY(0x0, 0x2, KEY_ENTER) /* ROW0, COL2 */
|
||||
MATRIX_KEY(0x1, 0x0, KEY_HOME) /* ROW1, COL0 */
|
||||
MATRIX_KEY(0x1, 0x1, KEY_RIGHT) /* ROW1, COL1 */
|
||||
MATRIX_KEY(0x1, 0x2, KEY_LEFT) /* ROW1, COL2 */
|
||||
MATRIX_KEY(0x2, 0x0, KEY_VOLUMEDOWN) /* ROW2, COL0 */
|
||||
MATRIX_KEY(0x2, 0x1, KEY_VOLUMEUP) /* ROW2, COL1 */
|
||||
>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lcdif {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lcd>;
|
||||
lcd-supply = <®_lcd_3v3>;
|
||||
display = <&display0>;
|
||||
status = "okay";
|
||||
|
||||
display0: display0 {
|
||||
bits-per-pixel = <32>;
|
||||
bus-width = <24>;
|
||||
|
||||
display-timings {
|
||||
native-mode = <&timing0>;
|
||||
timing0: timing0 {
|
||||
clock-frequency = <33500000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hback-porch = <89>;
|
||||
hfront-porch = <164>;
|
||||
vback-porch = <23>;
|
||||
vfront-porch = <10>;
|
||||
hsync-len = <10>;
|
||||
vsync-len = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&snvs_poweroff {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssi2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg1 {
|
||||
vbus-supply = <®_usb_otg1_vbus>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg1>;
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg2 {
|
||||
vbus-supply = <®_usb_otg2_vbus>;
|
||||
dr_mode = "host";
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
|
||||
bus-width = <8>;
|
||||
cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
|
||||
cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
||||
cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
1077
arch/arm/dts/imx6sl-pinfunc.h
Normal file
1077
arch/arm/dts/imx6sl-pinfunc.h
Normal file
File diff suppressed because it is too large
Load Diff
927
arch/arm/dts/imx6sl.dtsi
Normal file
927
arch/arm/dts/imx6sl.dtsi
Normal file
|
@ -0,0 +1,927 @@
|
|||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include "imx6sl-pinfunc.h"
|
||||
#include <dt-bindings/clock/imx6sl-clock.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/*
|
||||
* The decompressor and also some bootloaders rely on a
|
||||
* pre-existing /chosen node to be available to insert the
|
||||
* command line and merge other ATAGS info.
|
||||
* Also for U-Boot there must be a pre-existing /memory node.
|
||||
*/
|
||||
chosen {};
|
||||
memory { device_type = "memory"; reg = <0 0>; };
|
||||
|
||||
aliases {
|
||||
ethernet0 = &fec;
|
||||
gpio0 = &gpio1;
|
||||
gpio1 = &gpio2;
|
||||
gpio2 = &gpio3;
|
||||
gpio3 = &gpio4;
|
||||
gpio4 = &gpio5;
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
serial3 = &uart4;
|
||||
serial4 = &uart5;
|
||||
spi0 = &ecspi1;
|
||||
spi1 = &ecspi2;
|
||||
spi2 = &ecspi3;
|
||||
spi3 = &ecspi4;
|
||||
usbphy0 = &usbphy1;
|
||||
usbphy1 = &usbphy2;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a9";
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
operating-points = <
|
||||
/* kHz uV */
|
||||
996000 1275000
|
||||
792000 1175000
|
||||
396000 975000
|
||||
>;
|
||||
fsl,soc-operating-points = <
|
||||
/* ARM kHz SOC-PU uV */
|
||||
996000 1225000
|
||||
792000 1175000
|
||||
396000 1175000
|
||||
>;
|
||||
clock-latency = <61036>; /* two CLK32 periods */
|
||||
clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
|
||||
<&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
|
||||
<&clks IMX6SL_CLK_PLL1_SYS>;
|
||||
clock-names = "arm", "pll2_pfd2_396m", "step",
|
||||
"pll1_sw", "pll1_sys";
|
||||
arm-supply = <®_arm>;
|
||||
pu-supply = <®_pu>;
|
||||
soc-supply = <®_soc>;
|
||||
};
|
||||
};
|
||||
|
||||
intc: interrupt-controller@00a01000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x00a01000 0x1000>,
|
||||
<0x00a00100 0x100>;
|
||||
interrupt-parent = <&intc>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ckil {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
osc {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&gpc>;
|
||||
ranges;
|
||||
|
||||
ocram: sram@00900000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00900000 0x20000>;
|
||||
clocks = <&clks IMX6SL_CLK_OCRAM>;
|
||||
};
|
||||
|
||||
L2: l2-cache@00a02000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x00a02000 0x1000>;
|
||||
interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
arm,tag-latency = <4 2 3>;
|
||||
arm,data-latency = <4 2 3>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a9-pmu";
|
||||
interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
aips1: aips-bus@02000000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x02000000 0x100000>;
|
||||
ranges;
|
||||
|
||||
spba: spba-bus@02000000 {
|
||||
compatible = "fsl,spba-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x02000000 0x40000>;
|
||||
ranges;
|
||||
|
||||
spdif: spdif@02004000 {
|
||||
compatible = "fsl,imx6sl-spdif",
|
||||
"fsl,imx35-spdif";
|
||||
reg = <0x02004000 0x4000>;
|
||||
interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&sdma 14 18 0>,
|
||||
<&sdma 15 18 0>;
|
||||
dma-names = "rx", "tx";
|
||||
clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
|
||||
<&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
|
||||
<&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
|
||||
<&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
|
||||
<&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
|
||||
clock-names = "core", "rxtx0",
|
||||
"rxtx1", "rxtx2",
|
||||
"rxtx3", "rxtx4",
|
||||
"rxtx5", "rxtx6",
|
||||
"rxtx7", "spba";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi1: ecspi@02008000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x02008000 0x4000>;
|
||||
interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_ECSPI1>,
|
||||
<&clks IMX6SL_CLK_ECSPI1>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi2: ecspi@0200c000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x0200c000 0x4000>;
|
||||
interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_ECSPI2>,
|
||||
<&clks IMX6SL_CLK_ECSPI2>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi3: ecspi@02010000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x02010000 0x4000>;
|
||||
interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_ECSPI3>,
|
||||
<&clks IMX6SL_CLK_ECSPI3>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi4: ecspi@02014000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x02014000 0x4000>;
|
||||
interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_ECSPI4>,
|
||||
<&clks IMX6SL_CLK_ECSPI4>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: serial@02018000 {
|
||||
compatible = "fsl,imx6sl-uart",
|
||||
"fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x02018000 0x4000>;
|
||||
interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_UART>,
|
||||
<&clks IMX6SL_CLK_UART_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@02020000 {
|
||||
compatible = "fsl,imx6sl-uart",
|
||||
"fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x02020000 0x4000>;
|
||||
interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_UART>,
|
||||
<&clks IMX6SL_CLK_UART_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@02024000 {
|
||||
compatible = "fsl,imx6sl-uart",
|
||||
"fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x02024000 0x4000>;
|
||||
interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_UART>,
|
||||
<&clks IMX6SL_CLK_UART_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssi1: ssi@02028000 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "fsl,imx6sl-ssi",
|
||||
"fsl,imx51-ssi";
|
||||
reg = <0x02028000 0x4000>;
|
||||
interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
|
||||
<&clks IMX6SL_CLK_SSI1>;
|
||||
clock-names = "ipg", "baud";
|
||||
dmas = <&sdma 37 1 0>,
|
||||
<&sdma 38 1 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssi2: ssi@0202c000 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "fsl,imx6sl-ssi",
|
||||
"fsl,imx51-ssi";
|
||||
reg = <0x0202c000 0x4000>;
|
||||
interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
|
||||
<&clks IMX6SL_CLK_SSI2>;
|
||||
clock-names = "ipg", "baud";
|
||||
dmas = <&sdma 41 1 0>,
|
||||
<&sdma 42 1 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssi3: ssi@02030000 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "fsl,imx6sl-ssi",
|
||||
"fsl,imx51-ssi";
|
||||
reg = <0x02030000 0x4000>;
|
||||
interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
|
||||
<&clks IMX6SL_CLK_SSI3>;
|
||||
clock-names = "ipg", "baud";
|
||||
dmas = <&sdma 45 1 0>,
|
||||
<&sdma 46 1 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@02034000 {
|
||||
compatible = "fsl,imx6sl-uart",
|
||||
"fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x02034000 0x4000>;
|
||||
interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_UART>,
|
||||
<&clks IMX6SL_CLK_UART_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@02038000 {
|
||||
compatible = "fsl,imx6sl-uart",
|
||||
"fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x02038000 0x4000>;
|
||||
interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_UART>,
|
||||
<&clks IMX6SL_CLK_UART_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
pwm1: pwm@02080000 {
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x02080000 0x4000>;
|
||||
interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_PWM1>,
|
||||
<&clks IMX6SL_CLK_PWM1>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
pwm2: pwm@02084000 {
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x02084000 0x4000>;
|
||||
interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_PWM2>,
|
||||
<&clks IMX6SL_CLK_PWM2>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
pwm3: pwm@02088000 {
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x02088000 0x4000>;
|
||||
interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_PWM3>,
|
||||
<&clks IMX6SL_CLK_PWM3>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
pwm4: pwm@0208c000 {
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x0208c000 0x4000>;
|
||||
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_PWM4>,
|
||||
<&clks IMX6SL_CLK_PWM4>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
gpt: gpt@02098000 {
|
||||
compatible = "fsl,imx6sl-gpt";
|
||||
reg = <0x02098000 0x4000>;
|
||||
interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_GPT>,
|
||||
<&clks IMX6SL_CLK_GPT_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
gpio1: gpio@0209c000 {
|
||||
compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x0209c000 0x4000>;
|
||||
interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 22 1>, <&iomuxc 1 20 2>,
|
||||
<&iomuxc 3 23 1>, <&iomuxc 4 25 1>,
|
||||
<&iomuxc 5 24 1>, <&iomuxc 6 19 1>,
|
||||
<&iomuxc 7 36 2>, <&iomuxc 9 44 8>,
|
||||
<&iomuxc 17 38 6>, <&iomuxc 23 68 4>,
|
||||
<&iomuxc 27 64 4>, <&iomuxc 31 52 1>;
|
||||
};
|
||||
|
||||
gpio2: gpio@020a0000 {
|
||||
compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x020a0000 0x4000>;
|
||||
interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 53 3>, <&iomuxc 3 72 2>,
|
||||
<&iomuxc 5 34 2>, <&iomuxc 7 57 4>,
|
||||
<&iomuxc 11 56 1>, <&iomuxc 12 61 3>,
|
||||
<&iomuxc 15 107 1>, <&iomuxc 16 132 2>,
|
||||
<&iomuxc 18 135 1>, <&iomuxc 19 134 1>,
|
||||
<&iomuxc 20 108 2>, <&iomuxc 22 120 1>,
|
||||
<&iomuxc 23 125 7>, <&iomuxc 30 110 2>;
|
||||
};
|
||||
|
||||
gpio3: gpio@020a4000 {
|
||||
compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x020a4000 0x4000>;
|
||||
interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 112 8>, <&iomuxc 8 121 4>,
|
||||
<&iomuxc 12 97 4>, <&iomuxc 16 166 3>,
|
||||
<&iomuxc 19 85 2>, <&iomuxc 21 137 2>,
|
||||
<&iomuxc 23 136 1>, <&iomuxc 24 91 1>,
|
||||
<&iomuxc 25 99 1>, <&iomuxc 26 92 1>,
|
||||
<&iomuxc 27 100 1>, <&iomuxc 28 93 1>,
|
||||
<&iomuxc 29 101 1>, <&iomuxc 30 94 1>,
|
||||
<&iomuxc 31 102 1>;
|
||||
};
|
||||
|
||||
gpio4: gpio@020a8000 {
|
||||
compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x020a8000 0x4000>;
|
||||
interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 95 1>, <&iomuxc 1 103 1>,
|
||||
<&iomuxc 2 96 1>, <&iomuxc 3 104 1>,
|
||||
<&iomuxc 4 97 1>, <&iomuxc 5 105 1>,
|
||||
<&iomuxc 6 98 1>, <&iomuxc 7 106 1>,
|
||||
<&iomuxc 8 28 1>, <&iomuxc 9 27 1>,
|
||||
<&iomuxc 10 26 1>, <&iomuxc 11 29 1>,
|
||||
<&iomuxc 12 32 1>, <&iomuxc 13 31 1>,
|
||||
<&iomuxc 14 30 1>, <&iomuxc 15 33 1>,
|
||||
<&iomuxc 16 84 1>, <&iomuxc 17 79 2>,
|
||||
<&iomuxc 19 78 1>, <&iomuxc 20 76 1>,
|
||||
<&iomuxc 21 81 2>, <&iomuxc 23 75 1>,
|
||||
<&iomuxc 24 83 1>, <&iomuxc 25 74 1>,
|
||||
<&iomuxc 26 77 1>, <&iomuxc 27 159 1>,
|
||||
<&iomuxc 28 154 1>, <&iomuxc 29 157 1>,
|
||||
<&iomuxc 30 152 1>, <&iomuxc 31 156 1>;
|
||||
};
|
||||
|
||||
gpio5: gpio@020ac000 {
|
||||
compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x020ac000 0x4000>;
|
||||
interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 75 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 158 1>, <&iomuxc 1 151 1>,
|
||||
<&iomuxc 2 155 1>, <&iomuxc 3 153 1>,
|
||||
<&iomuxc 4 150 1>, <&iomuxc 5 149 1>,
|
||||
<&iomuxc 6 144 1>, <&iomuxc 7 147 1>,
|
||||
<&iomuxc 8 142 1>, <&iomuxc 9 146 1>,
|
||||
<&iomuxc 10 148 1>, <&iomuxc 11 141 1>,
|
||||
<&iomuxc 12 145 1>, <&iomuxc 13 143 1>,
|
||||
<&iomuxc 14 140 1>, <&iomuxc 15 139 1>,
|
||||
<&iomuxc 16 164 2>, <&iomuxc 18 160 1>,
|
||||
<&iomuxc 19 162 1>, <&iomuxc 20 163 1>,
|
||||
<&iomuxc 21 161 1>;
|
||||
};
|
||||
|
||||
kpp: kpp@020b8000 {
|
||||
compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
|
||||
reg = <0x020b8000 0x4000>;
|
||||
interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_DUMMY>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog1: wdog@020bc000 {
|
||||
compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x020bc000 0x4000>;
|
||||
interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_DUMMY>;
|
||||
};
|
||||
|
||||
wdog2: wdog@020c0000 {
|
||||
compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x020c0000 0x4000>;
|
||||
interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_DUMMY>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clks: ccm@020c4000 {
|
||||
compatible = "fsl,imx6sl-ccm";
|
||||
reg = <0x020c4000 0x4000>;
|
||||
interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 88 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
anatop: anatop@020c8000 {
|
||||
compatible = "fsl,imx6sl-anatop",
|
||||
"fsl,imx6q-anatop",
|
||||
"syscon", "simple-bus";
|
||||
reg = <0x020c8000 0x1000>;
|
||||
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 54 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
regulator-1p1 {
|
||||
compatible = "fsl,anatop-regulator";
|
||||
regulator-name = "vdd1p1";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1375000>;
|
||||
regulator-always-on;
|
||||
anatop-reg-offset = <0x110>;
|
||||
anatop-vol-bit-shift = <8>;
|
||||
anatop-vol-bit-width = <5>;
|
||||
anatop-min-bit-val = <4>;
|
||||
anatop-min-voltage = <800000>;
|
||||
anatop-max-voltage = <1375000>;
|
||||
};
|
||||
|
||||
regulator-3p0 {
|
||||
compatible = "fsl,anatop-regulator";
|
||||
regulator-name = "vdd3p0";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <3150000>;
|
||||
regulator-always-on;
|
||||
anatop-reg-offset = <0x120>;
|
||||
anatop-vol-bit-shift = <8>;
|
||||
anatop-vol-bit-width = <5>;
|
||||
anatop-min-bit-val = <0>;
|
||||
anatop-min-voltage = <2625000>;
|
||||
anatop-max-voltage = <3400000>;
|
||||
};
|
||||
|
||||
regulator-2p5 {
|
||||
compatible = "fsl,anatop-regulator";
|
||||
regulator-name = "vdd2p5";
|
||||
regulator-min-microvolt = <2100000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
regulator-always-on;
|
||||
anatop-reg-offset = <0x130>;
|
||||
anatop-vol-bit-shift = <8>;
|
||||
anatop-vol-bit-width = <5>;
|
||||
anatop-min-bit-val = <0>;
|
||||
anatop-min-voltage = <2100000>;
|
||||
anatop-max-voltage = <2850000>;
|
||||
};
|
||||
|
||||
reg_arm: regulator-vddcore {
|
||||
compatible = "fsl,anatop-regulator";
|
||||
regulator-name = "vddarm";
|
||||
regulator-min-microvolt = <725000>;
|
||||
regulator-max-microvolt = <1450000>;
|
||||
regulator-always-on;
|
||||
anatop-reg-offset = <0x140>;
|
||||
anatop-vol-bit-shift = <0>;
|
||||
anatop-vol-bit-width = <5>;
|
||||
anatop-delay-reg-offset = <0x170>;
|
||||
anatop-delay-bit-shift = <24>;
|
||||
anatop-delay-bit-width = <2>;
|
||||
anatop-min-bit-val = <1>;
|
||||
anatop-min-voltage = <725000>;
|
||||
anatop-max-voltage = <1450000>;
|
||||
};
|
||||
|
||||
reg_pu: regulator-vddpu {
|
||||
compatible = "fsl,anatop-regulator";
|
||||
regulator-name = "vddpu";
|
||||
regulator-min-microvolt = <725000>;
|
||||
regulator-max-microvolt = <1450000>;
|
||||
regulator-always-on;
|
||||
anatop-reg-offset = <0x140>;
|
||||
anatop-vol-bit-shift = <9>;
|
||||
anatop-vol-bit-width = <5>;
|
||||
anatop-delay-reg-offset = <0x170>;
|
||||
anatop-delay-bit-shift = <26>;
|
||||
anatop-delay-bit-width = <2>;
|
||||
anatop-min-bit-val = <1>;
|
||||
anatop-min-voltage = <725000>;
|
||||
anatop-max-voltage = <1450000>;
|
||||
};
|
||||
|
||||
reg_soc: regulator-vddsoc {
|
||||
compatible = "fsl,anatop-regulator";
|
||||
regulator-name = "vddsoc";
|
||||
regulator-min-microvolt = <725000>;
|
||||
regulator-max-microvolt = <1450000>;
|
||||
regulator-always-on;
|
||||
anatop-reg-offset = <0x140>;
|
||||
anatop-vol-bit-shift = <18>;
|
||||
anatop-vol-bit-width = <5>;
|
||||
anatop-delay-reg-offset = <0x170>;
|
||||
anatop-delay-bit-shift = <28>;
|
||||
anatop-delay-bit-width = <2>;
|
||||
anatop-min-bit-val = <1>;
|
||||
anatop-min-voltage = <725000>;
|
||||
anatop-max-voltage = <1450000>;
|
||||
};
|
||||
};
|
||||
|
||||
tempmon: tempmon {
|
||||
compatible = "fsl,imx6q-tempmon";
|
||||
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
fsl,tempmon = <&anatop>;
|
||||
fsl,tempmon-data = <&ocotp>;
|
||||
clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
|
||||
};
|
||||
|
||||
usbphy1: usbphy@020c9000 {
|
||||
compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
|
||||
reg = <0x020c9000 0x1000>;
|
||||
interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_USBPHY1>;
|
||||
fsl,anatop = <&anatop>;
|
||||
};
|
||||
|
||||
usbphy2: usbphy@020ca000 {
|
||||
compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
|
||||
reg = <0x020ca000 0x1000>;
|
||||
interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_USBPHY2>;
|
||||
fsl,anatop = <&anatop>;
|
||||
};
|
||||
|
||||
snvs: snvs@020cc000 {
|
||||
compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
|
||||
reg = <0x020cc000 0x4000>;
|
||||
|
||||
snvs_rtc: snvs-rtc-lp {
|
||||
compatible = "fsl,sec-v4.0-mon-rtc-lp";
|
||||
regmap = <&snvs>;
|
||||
offset = <0x34>;
|
||||
interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
snvs_poweroff: snvs-poweroff {
|
||||
compatible = "syscon-poweroff";
|
||||
regmap = <&snvs>;
|
||||
offset = <0x38>;
|
||||
mask = <0x60>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
epit1: epit@020d0000 {
|
||||
reg = <0x020d0000 0x4000>;
|
||||
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
epit2: epit@020d4000 {
|
||||
reg = <0x020d4000 0x4000>;
|
||||
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
src: src@020d8000 {
|
||||
compatible = "fsl,imx6sl-src", "fsl,imx51-src";
|
||||
reg = <0x020d8000 0x4000>;
|
||||
interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 96 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
gpc: gpc@020dc000 {
|
||||
compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
|
||||
reg = <0x020dc000 0x4000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&intc>;
|
||||
pu-supply = <®_pu>;
|
||||
clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
|
||||
<&clks IMX6SL_CLK_GPU2D_PODF>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
gpr: iomuxc-gpr@020e0000 {
|
||||
compatible = "fsl,imx6sl-iomuxc-gpr",
|
||||
"fsl,imx6q-iomuxc-gpr", "syscon";
|
||||
reg = <0x020e0000 0x38>;
|
||||
};
|
||||
|
||||
iomuxc: iomuxc@020e0000 {
|
||||
compatible = "fsl,imx6sl-iomuxc";
|
||||
reg = <0x020e0000 0x4000>;
|
||||
};
|
||||
|
||||
csi: csi@020e4000 {
|
||||
reg = <0x020e4000 0x4000>;
|
||||
interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
spdc: spdc@020e8000 {
|
||||
reg = <0x020e8000 0x4000>;
|
||||
interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sdma: sdma@020ec000 {
|
||||
compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
|
||||
reg = <0x020ec000 0x4000>;
|
||||
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_SDMA>,
|
||||
<&clks IMX6SL_CLK_SDMA>;
|
||||
clock-names = "ipg", "ahb";
|
||||
#dma-cells = <3>;
|
||||
/* imx6sl reuses imx6q sdma firmware */
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
|
||||
};
|
||||
|
||||
pxp: pxp@020f0000 {
|
||||
reg = <0x020f0000 0x4000>;
|
||||
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
epdc: epdc@020f4000 {
|
||||
reg = <0x020f4000 0x4000>;
|
||||
interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
lcdif: lcdif@020f8000 {
|
||||
compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
|
||||
reg = <0x020f8000 0x4000>;
|
||||
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
|
||||
<&clks IMX6SL_CLK_LCDIF_AXI>,
|
||||
<&clks IMX6SL_CLK_DUMMY>;
|
||||
clock-names = "pix", "axi", "disp_axi";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dcp: dcp@020fc000 {
|
||||
compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
|
||||
reg = <0x020fc000 0x4000>;
|
||||
interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 100 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 101 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
aips2: aips-bus@02100000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x02100000 0x100000>;
|
||||
ranges;
|
||||
|
||||
usbotg1: usb@02184000 {
|
||||
compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
|
||||
reg = <0x02184000 0x200>;
|
||||
interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_USBOH3>;
|
||||
fsl,usbphy = <&usbphy1>;
|
||||
fsl,usbmisc = <&usbmisc 0>;
|
||||
ahb-burst-config = <0x0>;
|
||||
tx-burst-size-dword = <0x10>;
|
||||
rx-burst-size-dword = <0x10>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbotg2: usb@02184200 {
|
||||
compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
|
||||
reg = <0x02184200 0x200>;
|
||||
interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_USBOH3>;
|
||||
fsl,usbphy = <&usbphy2>;
|
||||
fsl,usbmisc = <&usbmisc 1>;
|
||||
ahb-burst-config = <0x0>;
|
||||
tx-burst-size-dword = <0x10>;
|
||||
rx-burst-size-dword = <0x10>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbh: usb@02184400 {
|
||||
compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
|
||||
reg = <0x02184400 0x200>;
|
||||
interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_USBOH3>;
|
||||
fsl,usbmisc = <&usbmisc 2>;
|
||||
dr_mode = "host";
|
||||
ahb-burst-config = <0x0>;
|
||||
tx-burst-size-dword = <0x10>;
|
||||
rx-burst-size-dword = <0x10>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbmisc: usbmisc@02184800 {
|
||||
#index-cells = <1>;
|
||||
compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
|
||||
reg = <0x02184800 0x200>;
|
||||
clocks = <&clks IMX6SL_CLK_USBOH3>;
|
||||
};
|
||||
|
||||
fec: ethernet@02188000 {
|
||||
compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
|
||||
reg = <0x02188000 0x4000>;
|
||||
interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_ENET>,
|
||||
<&clks IMX6SL_CLK_ENET_REF>;
|
||||
clock-names = "ipg", "ahb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc1: usdhc@02190000 {
|
||||
compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
|
||||
reg = <0x02190000 0x4000>;
|
||||
interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_USDHC1>,
|
||||
<&clks IMX6SL_CLK_USDHC1>,
|
||||
<&clks IMX6SL_CLK_USDHC1>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc2: usdhc@02194000 {
|
||||
compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
|
||||
reg = <0x02194000 0x4000>;
|
||||
interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_USDHC2>,
|
||||
<&clks IMX6SL_CLK_USDHC2>,
|
||||
<&clks IMX6SL_CLK_USDHC2>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc3: usdhc@02198000 {
|
||||
compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
|
||||
reg = <0x02198000 0x4000>;
|
||||
interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_USDHC3>,
|
||||
<&clks IMX6SL_CLK_USDHC3>,
|
||||
<&clks IMX6SL_CLK_USDHC3>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc4: usdhc@0219c000 {
|
||||
compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
|
||||
reg = <0x0219c000 0x4000>;
|
||||
interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_USDHC4>,
|
||||
<&clks IMX6SL_CLK_USDHC4>,
|
||||
<&clks IMX6SL_CLK_USDHC4>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@021a0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x021a0000 0x4000>;
|
||||
interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_I2C1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@021a4000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x021a4000 0x4000>;
|
||||
interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_I2C2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@021a8000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x021a8000 0x4000>;
|
||||
interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_I2C3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmdc: mmdc@021b0000 {
|
||||
compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
|
||||
reg = <0x021b0000 0x4000>;
|
||||
};
|
||||
|
||||
rngb: rngb@021b4000 {
|
||||
reg = <0x021b4000 0x4000>;
|
||||
interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
weim: weim@021b8000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x021b8000 0x4000>;
|
||||
interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
fsl,weim-cs-gpr = <&gpr>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ocotp: ocotp@021bc000 {
|
||||
compatible = "fsl,imx6sl-ocotp", "syscon";
|
||||
reg = <0x021bc000 0x4000>;
|
||||
clocks = <&clks IMX6SL_CLK_OCOTP>;
|
||||
};
|
||||
|
||||
audmux: audmux@021d8000 {
|
||||
compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
|
||||
reg = <0x021d8000 0x4000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
|
@ -1,6 +1,7 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_TARGET_MX6SLEVK=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL"
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
|
@ -23,10 +24,10 @@ CONFIG_CMD_EXT4=y
|
|||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
|
|
|
@ -1,6 +1,7 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_TARGET_MX6SLEVK=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL"
|
||||
CONFIG_SPI_BOOT=y
|
||||
CONFIG_BOOTDELAY=3
|
||||
|
@ -24,10 +25,10 @@ CONFIG_CMD_EXT4=y
|
|||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
|
|
180
include/dt-bindings/clock/imx6sl-clock.h
Normal file
180
include/dt-bindings/clock/imx6sl-clock.h
Normal file
|
@ -0,0 +1,180 @@
|
|||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_IMX6SL_H
|
||||
#define __DT_BINDINGS_CLOCK_IMX6SL_H
|
||||
|
||||
#define IMX6SL_CLK_DUMMY 0
|
||||
#define IMX6SL_CLK_CKIL 1
|
||||
#define IMX6SL_CLK_OSC 2
|
||||
#define IMX6SL_CLK_PLL1_SYS 3
|
||||
#define IMX6SL_CLK_PLL2_BUS 4
|
||||
#define IMX6SL_CLK_PLL3_USB_OTG 5
|
||||
#define IMX6SL_CLK_PLL4_AUDIO 6
|
||||
#define IMX6SL_CLK_PLL5_VIDEO 7
|
||||
#define IMX6SL_CLK_PLL6_ENET 8
|
||||
#define IMX6SL_CLK_PLL7_USB_HOST 9
|
||||
#define IMX6SL_CLK_USBPHY1 10
|
||||
#define IMX6SL_CLK_USBPHY2 11
|
||||
#define IMX6SL_CLK_USBPHY1_GATE 12
|
||||
#define IMX6SL_CLK_USBPHY2_GATE 13
|
||||
#define IMX6SL_CLK_PLL4_POST_DIV 14
|
||||
#define IMX6SL_CLK_PLL5_POST_DIV 15
|
||||
#define IMX6SL_CLK_PLL5_VIDEO_DIV 16
|
||||
#define IMX6SL_CLK_ENET_REF 17
|
||||
#define IMX6SL_CLK_PLL2_PFD0 18
|
||||
#define IMX6SL_CLK_PLL2_PFD1 19
|
||||
#define IMX6SL_CLK_PLL2_PFD2 20
|
||||
#define IMX6SL_CLK_PLL3_PFD0 21
|
||||
#define IMX6SL_CLK_PLL3_PFD1 22
|
||||
#define IMX6SL_CLK_PLL3_PFD2 23
|
||||
#define IMX6SL_CLK_PLL3_PFD3 24
|
||||
#define IMX6SL_CLK_PLL2_198M 25
|
||||
#define IMX6SL_CLK_PLL3_120M 26
|
||||
#define IMX6SL_CLK_PLL3_80M 27
|
||||
#define IMX6SL_CLK_PLL3_60M 28
|
||||
#define IMX6SL_CLK_STEP 29
|
||||
#define IMX6SL_CLK_PLL1_SW 30
|
||||
#define IMX6SL_CLK_OCRAM_ALT_SEL 31
|
||||
#define IMX6SL_CLK_OCRAM_SEL 32
|
||||
#define IMX6SL_CLK_PRE_PERIPH2_SEL 33
|
||||
#define IMX6SL_CLK_PRE_PERIPH_SEL 34
|
||||
#define IMX6SL_CLK_PERIPH2_CLK2_SEL 35
|
||||
#define IMX6SL_CLK_PERIPH_CLK2_SEL 36
|
||||
#define IMX6SL_CLK_CSI_SEL 37
|
||||
#define IMX6SL_CLK_LCDIF_AXI_SEL 38
|
||||
#define IMX6SL_CLK_USDHC1_SEL 39
|
||||
#define IMX6SL_CLK_USDHC2_SEL 40
|
||||
#define IMX6SL_CLK_USDHC3_SEL 41
|
||||
#define IMX6SL_CLK_USDHC4_SEL 42
|
||||
#define IMX6SL_CLK_SSI1_SEL 43
|
||||
#define IMX6SL_CLK_SSI2_SEL 44
|
||||
#define IMX6SL_CLK_SSI3_SEL 45
|
||||
#define IMX6SL_CLK_PERCLK_SEL 46
|
||||
#define IMX6SL_CLK_PXP_AXI_SEL 47
|
||||
#define IMX6SL_CLK_EPDC_AXI_SEL 48
|
||||
#define IMX6SL_CLK_GPU2D_OVG_SEL 49
|
||||
#define IMX6SL_CLK_GPU2D_SEL 50
|
||||
#define IMX6SL_CLK_LCDIF_PIX_SEL 51
|
||||
#define IMX6SL_CLK_EPDC_PIX_SEL 52
|
||||
#define IMX6SL_CLK_SPDIF0_SEL 53
|
||||
#define IMX6SL_CLK_SPDIF1_SEL 54
|
||||
#define IMX6SL_CLK_EXTERN_AUDIO_SEL 55
|
||||
#define IMX6SL_CLK_ECSPI_SEL 56
|
||||
#define IMX6SL_CLK_UART_SEL 57
|
||||
#define IMX6SL_CLK_PERIPH 58
|
||||
#define IMX6SL_CLK_PERIPH2 59
|
||||
#define IMX6SL_CLK_OCRAM_PODF 60
|
||||
#define IMX6SL_CLK_PERIPH_CLK2_PODF 61
|
||||
#define IMX6SL_CLK_PERIPH2_CLK2_PODF 62
|
||||
#define IMX6SL_CLK_IPG 63
|
||||
#define IMX6SL_CLK_CSI_PODF 64
|
||||
#define IMX6SL_CLK_LCDIF_AXI_PODF 65
|
||||
#define IMX6SL_CLK_USDHC1_PODF 66
|
||||
#define IMX6SL_CLK_USDHC2_PODF 67
|
||||
#define IMX6SL_CLK_USDHC3_PODF 68
|
||||
#define IMX6SL_CLK_USDHC4_PODF 69
|
||||
#define IMX6SL_CLK_SSI1_PRED 70
|
||||
#define IMX6SL_CLK_SSI1_PODF 71
|
||||
#define IMX6SL_CLK_SSI2_PRED 72
|
||||
#define IMX6SL_CLK_SSI2_PODF 73
|
||||
#define IMX6SL_CLK_SSI3_PRED 74
|
||||
#define IMX6SL_CLK_SSI3_PODF 75
|
||||
#define IMX6SL_CLK_PERCLK 76
|
||||
#define IMX6SL_CLK_PXP_AXI_PODF 77
|
||||
#define IMX6SL_CLK_EPDC_AXI_PODF 78
|
||||
#define IMX6SL_CLK_GPU2D_OVG_PODF 79
|
||||
#define IMX6SL_CLK_GPU2D_PODF 80
|
||||
#define IMX6SL_CLK_LCDIF_PIX_PRED 81
|
||||
#define IMX6SL_CLK_EPDC_PIX_PRED 82
|
||||
#define IMX6SL_CLK_LCDIF_PIX_PODF 83
|
||||
#define IMX6SL_CLK_EPDC_PIX_PODF 84
|
||||
#define IMX6SL_CLK_SPDIF0_PRED 85
|
||||
#define IMX6SL_CLK_SPDIF0_PODF 86
|
||||
#define IMX6SL_CLK_SPDIF1_PRED 87
|
||||
#define IMX6SL_CLK_SPDIF1_PODF 88
|
||||
#define IMX6SL_CLK_EXTERN_AUDIO_PRED 89
|
||||
#define IMX6SL_CLK_EXTERN_AUDIO_PODF 90
|
||||
#define IMX6SL_CLK_ECSPI_ROOT 91
|
||||
#define IMX6SL_CLK_UART_ROOT 92
|
||||
#define IMX6SL_CLK_AHB 93
|
||||
#define IMX6SL_CLK_MMDC_ROOT 94
|
||||
#define IMX6SL_CLK_ARM 95
|
||||
#define IMX6SL_CLK_ECSPI1 96
|
||||
#define IMX6SL_CLK_ECSPI2 97
|
||||
#define IMX6SL_CLK_ECSPI3 98
|
||||
#define IMX6SL_CLK_ECSPI4 99
|
||||
#define IMX6SL_CLK_EPIT1 100
|
||||
#define IMX6SL_CLK_EPIT2 101
|
||||
#define IMX6SL_CLK_EXTERN_AUDIO 102
|
||||
#define IMX6SL_CLK_GPT 103
|
||||
#define IMX6SL_CLK_GPT_SERIAL 104
|
||||
#define IMX6SL_CLK_GPU2D_OVG 105
|
||||
#define IMX6SL_CLK_I2C1 106
|
||||
#define IMX6SL_CLK_I2C2 107
|
||||
#define IMX6SL_CLK_I2C3 108
|
||||
#define IMX6SL_CLK_OCOTP 109
|
||||
#define IMX6SL_CLK_CSI 110
|
||||
#define IMX6SL_CLK_PXP_AXI 111
|
||||
#define IMX6SL_CLK_EPDC_AXI 112
|
||||
#define IMX6SL_CLK_LCDIF_AXI 113
|
||||
#define IMX6SL_CLK_LCDIF_PIX 114
|
||||
#define IMX6SL_CLK_EPDC_PIX 115
|
||||
#define IMX6SL_CLK_OCRAM 116
|
||||
#define IMX6SL_CLK_PWM1 117
|
||||
#define IMX6SL_CLK_PWM2 118
|
||||
#define IMX6SL_CLK_PWM3 119
|
||||
#define IMX6SL_CLK_PWM4 120
|
||||
#define IMX6SL_CLK_SDMA 121
|
||||
#define IMX6SL_CLK_SPDIF 122
|
||||
#define IMX6SL_CLK_SSI1 123
|
||||
#define IMX6SL_CLK_SSI2 124
|
||||
#define IMX6SL_CLK_SSI3 125
|
||||
#define IMX6SL_CLK_UART 126
|
||||
#define IMX6SL_CLK_UART_SERIAL 127
|
||||
#define IMX6SL_CLK_USBOH3 128
|
||||
#define IMX6SL_CLK_USDHC1 129
|
||||
#define IMX6SL_CLK_USDHC2 130
|
||||
#define IMX6SL_CLK_USDHC3 131
|
||||
#define IMX6SL_CLK_USDHC4 132
|
||||
#define IMX6SL_CLK_PLL4_AUDIO_DIV 133
|
||||
#define IMX6SL_CLK_SPBA 134
|
||||
#define IMX6SL_CLK_ENET 135
|
||||
#define IMX6SL_CLK_LVDS1_SEL 136
|
||||
#define IMX6SL_CLK_LVDS1_OUT 137
|
||||
#define IMX6SL_CLK_LVDS1_IN 138
|
||||
#define IMX6SL_CLK_ANACLK1 139
|
||||
#define IMX6SL_PLL1_BYPASS_SRC 140
|
||||
#define IMX6SL_PLL2_BYPASS_SRC 141
|
||||
#define IMX6SL_PLL3_BYPASS_SRC 142
|
||||
#define IMX6SL_PLL4_BYPASS_SRC 143
|
||||
#define IMX6SL_PLL5_BYPASS_SRC 144
|
||||
#define IMX6SL_PLL6_BYPASS_SRC 145
|
||||
#define IMX6SL_PLL7_BYPASS_SRC 146
|
||||
#define IMX6SL_CLK_PLL1 147
|
||||
#define IMX6SL_CLK_PLL2 148
|
||||
#define IMX6SL_CLK_PLL3 149
|
||||
#define IMX6SL_CLK_PLL4 150
|
||||
#define IMX6SL_CLK_PLL5 151
|
||||
#define IMX6SL_CLK_PLL6 152
|
||||
#define IMX6SL_CLK_PLL7 153
|
||||
#define IMX6SL_PLL1_BYPASS 154
|
||||
#define IMX6SL_PLL2_BYPASS 155
|
||||
#define IMX6SL_PLL3_BYPASS 156
|
||||
#define IMX6SL_PLL4_BYPASS 157
|
||||
#define IMX6SL_PLL5_BYPASS 158
|
||||
#define IMX6SL_PLL6_BYPASS 159
|
||||
#define IMX6SL_PLL7_BYPASS 160
|
||||
#define IMX6SL_CLK_SSI1_IPG 161
|
||||
#define IMX6SL_CLK_SSI2_IPG 162
|
||||
#define IMX6SL_CLK_SSI3_IPG 163
|
||||
#define IMX6SL_CLK_SPDIF_GCLK 164
|
||||
#define IMX6SL_CLK_END 165
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
|
Loading…
Reference in New Issue
Block a user