brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-07-06 19:26:16 +09:00
Code Issues Projects Releases Wiki Activity

sunxi_nand_spl: Add proper cache flusing

Browse Source 
We are using dma, so we should flush the cache before starting the dma,
and invalidate it once the dma is done.

Things are working without this by mostly luck, but lets not rely on that.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This commit is contained in:
Hans de Goede 2015-08-15 12:32:24 +02:00
parent 5d65c67bf1
commit 2a43973f64
1 changed files with 8 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/mtd/nand/sunxi_nand_spl.c
View File

@ -266,6 +266,10 @@ static void nand_read_page(unsigned int real_addr, dma_addr_t dst,
writel(oob_offset, SUNXI_NFC_BASE + NFC_SPARE_AREA);
}
flush_dcache_range(dst,
ALIGN(dst + CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE,
ARCH_DMA_MINALIGN));
/* SUNXI_DMA */
writel(0x0, SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0); /* clr dma cmd */
/* read from REG_IO_DATA */
@ -311,6 +315,10 @@ static void nand_read_page(unsigned int real_addr, dma_addr_t dst,
return;
}
invalidate_dcache_range(dst,
ALIGN(dst + CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE,
ARCH_DMA_MINALIGN));
if (readl(SUNXI_NFC_BASE + NFC_ECC_ST))
(*ecc_errors)++;
}