drivers/net/phy: Add CORTINA_NO_FW_UPLOAD to Kconfig

Move CORTINA_NO_FW_UPLOAD to Kconfig file so that it can
be controlled via defconfig files.

Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Meenakshi Aggarwal 2020-10-29 19:16:15 +05:30 committed by Priyanka Jain
parent 1255f8bc36
commit 2a29a9a1b4
9 changed files with 18 additions and 6 deletions

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@ -56,6 +56,7 @@ CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y

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@ -63,6 +63,7 @@ CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y

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@ -52,6 +52,7 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y

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@ -61,6 +61,7 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y

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@ -61,6 +61,7 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y

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@ -100,6 +100,15 @@ config PHY_BROADCOM
config PHY_CORTINA
bool "Cortina Ethernet PHYs support"
config SYS_CORTINA_NO_FW_UPLOAD
bool "Cortina firmware loading support"
default n
depends on PHY_CORTINA
help
Cortina phy has provision to store phy firmware in attached dedicated
EEPROM. And boards designed with such EEPROM does not require firmware
upload.
choice
prompt "Location of the Cortina firmware"
default SYS_CORTINA_FW_IN_NOR

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@ -3,7 +3,7 @@
* Cortina CS4315/CS4340 10G PHY drivers
*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2018 NXP
* Copyright 2018, 2020 NXP
*
*/
@ -29,7 +29,7 @@
#error The Cortina PHY needs 10G support
#endif
#ifndef CORTINA_NO_FW_UPLOAD
#ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD
struct cortina_reg_config cortina_reg_cfg[] = {
/* CS4315_enable_sr_mode */
{VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
@ -227,7 +227,7 @@ void cs4340_upload_firmware(struct phy_device *phydev)
int cs4340_phy_init(struct phy_device *phydev)
{
#ifndef CORTINA_NO_FW_UPLOAD
#ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD
int timeout = 100; /* 100ms */
#endif
int reg_value;
@ -238,7 +238,7 @@ int cs4340_phy_init(struct phy_device *phydev)
* Boards designed with EEPROM attached to Cortina
* does not require FW upload.
*/
#ifndef CORTINA_NO_FW_UPLOAD
#ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD
/* step1: BIST test */
phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL, 0x0004);
phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000);

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@ -93,7 +93,6 @@ u8 qixis_esdhc_detect_quirk(void);
#define AQ_PHY_ADDR3 0x02
#define AQ_PHY_ADDR4 0x03
#define CORTINA_NO_FW_UPLOAD
#define CORTINA_PHY_ADDR1 0x0
#define INPHI_PHY_ADDR1 0x0

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@ -64,7 +64,6 @@
#define AQR107_PHY_ADDR2 0x05
#define AQR107_IRQ_MASK 0x0C
#define CORTINA_NO_FW_UPLOAD
#define CORTINA_PHY_ADDR1 0x0
#define INPHI_PHY_ADDR1 0x0