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ppc4xx: Add CONFIG_4xx_DCACHE compile switch to Denali-core SPD code

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Signed-off-by: Larry Johnson <lrj@acm.org>
This commit is contained in:
Larry Johnson 2008-01-22 08:51:59 -05:00 committed by Stefan Roese
parent ff02f13980
commit 29e3500cbc
1 changed files with 3 additions and 3 deletions
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6
cpu/ppc4xx/denali_spd_ddr2.c
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@ -3,7 +3,7 @@
* This SPD SDRAM detection code supports AMCC PPC44x CPUs with a Denali-core * This SPD SDRAM detection code supports AMCC PPC44x CPUs with a Denali-core
* DDR2 controller, specifically the 440EPx/GRx. * DDR2 controller, specifically the 440EPx/GRx.
* *
* (C) Copyright 2007 * (C) Copyright 2007-2008
* Larry Johnson, lrj@acm.org. * Larry Johnson, lrj@acm.org.
* *
* Based primarily on cpu/ppc4xx/4xx_spd_ddr2.c, which is... * Based primarily on cpu/ppc4xx/4xx_spd_ddr2.c, which is...
@ -77,10 +77,10 @@
* memory. * memory.
* *
* If at some time this restriction doesn't apply anymore, just define * If at some time this restriction doesn't apply anymore, just define
* CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup * CONFIG_4xx_DCACHE in the board config file and this code should setup
* everything correctly. * everything correctly.
*/ */
#if defined(CFG_ENABLE_SDRAM_CACHE) #if defined(CONFIG_4xx_DCACHE)
#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
#else #else
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */