mirror of
https://github.com/brain-hackers/u-boot-brain
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- Add lx2162 soc, lx2162qds support. - Bug-fixes related ls102x-usb, ifc, bootcmd, secure-boot header, - rgmii, vid, fdt, env variable, pci for Layerscape products
This commit is contained in:
commit
298a62960f
@ -1326,6 +1326,18 @@ config TARGET_LX2160AQDS
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is a high-performance development platform that supports the
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is a high-performance development platform that supports the
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QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
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QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
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config TARGET_LX2162AQDS
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bool "Support lx2162aqds"
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select ARCH_LX2162A
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select ARCH_MISC_INIT
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select ARM64
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select ARMV8_MULTIENTRY
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select ARCH_SUPPORT_TFABOOT
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select BOARD_LATE_INIT
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help
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Support for NXP LX2162AQDS platform.
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The lx2162aqds support is based on LX2160A Layerscape Architecture processor.
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config TARGET_HIKEY
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config TARGET_HIKEY
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bool "Support HiKey 96boards Consumer Edition Platform"
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bool "Support HiKey 96boards Consumer Edition Platform"
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select ARM64
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select ARM64
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@ -5,11 +5,11 @@ config ARCH_LS1021A
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select SYS_FSL_ERRATUM_A008378
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select SYS_FSL_ERRATUM_A008378
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select SYS_FSL_ERRATUM_A008407
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select SYS_FSL_ERRATUM_A008407
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select SYS_FSL_ERRATUM_A008850
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select SYS_FSL_ERRATUM_A008850
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select SYS_FSL_ERRATUM_A008997
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select SYS_FSL_ERRATUM_A008997 if USB
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select SYS_FSL_ERRATUM_A009007
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select SYS_FSL_ERRATUM_A009007 if USB
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select SYS_FSL_ERRATUM_A009008
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select SYS_FSL_ERRATUM_A009008 if USB
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select SYS_FSL_ERRATUM_A009663
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select SYS_FSL_ERRATUM_A009663
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select SYS_FSL_ERRATUM_A009798
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select SYS_FSL_ERRATUM_A009798 if USB
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select SYS_FSL_ERRATUM_A009942
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select SYS_FSL_ERRATUM_A009942
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select SYS_FSL_ERRATUM_A010315
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select SYS_FSL_ERRATUM_A010315
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select SYS_FSL_HAS_CCI400
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select SYS_FSL_HAS_CCI400
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@ -115,7 +115,7 @@ config PSCI_RESET
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!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
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!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
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!TARGET_LS1046AFRWY && \
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!TARGET_LS1046AFRWY && \
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!TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
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!TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
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!TARGET_LX2160AQDS && \
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!TARGET_LX2160AQDS && !TARGET_LX2162AQDS && \
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!ARCH_UNIPHIER && !TARGET_S32V234EVB
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!ARCH_UNIPHIER && !TARGET_S32V234EVB
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help
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help
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Most armv8 systems have PSCI support enabled in EL3, either through
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Most armv8 systems have PSCI support enabled in EL3, either through
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@ -208,6 +208,35 @@ config ARCH_LS2080A
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imply DISTRO_DEFAULTS
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imply DISTRO_DEFAULTS
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imply PANIC_HANG
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imply PANIC_HANG
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config ARCH_LX2162A
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bool
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select ARMV8_SET_SMPEN
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select FSL_LSCH3
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select NXP_LSCH3_2
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select SYS_HAS_SERDES
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select SYS_FSL_SRDS_1
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select SYS_FSL_SRDS_2
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select SYS_FSL_DDR
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select SYS_FSL_DDR_LE
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select SYS_FSL_DDR_VER_50
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select SYS_FSL_EC1
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select SYS_FSL_EC2
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select SYS_FSL_ERRATUM_A050106
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select SYS_FSL_HAS_RGMII
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select SYS_FSL_HAS_SEC
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select SYS_FSL_HAS_CCN508
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select SYS_FSL_HAS_DDR4
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select SYS_FSL_SEC_COMPAT_5
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select SYS_FSL_SEC_LE
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select ARCH_EARLY_INIT_R
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select BOARD_EARLY_INIT_F
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select SYS_I2C_MXC
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select RESV_RAM if GIC_V3_ITS
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imply DISTRO_DEFAULTS
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imply PANIC_HANG
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imply SCSI
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imply SCSI_AHCI
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config ARCH_LX2160A
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config ARCH_LX2160A
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bool
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bool
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select ARMV8_SET_SMPEN
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select ARMV8_SET_SMPEN
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@ -345,7 +374,7 @@ config SYS_FSL_ERRATUM_A050106
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help
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help
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USB3.0 Receiver needs to enable fixed equalization
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USB3.0 Receiver needs to enable fixed equalization
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for each of PHY instances in an SOC. This is similar
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for each of PHY instances in an SOC. This is similar
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to erratum A-009007, but this one is for LX2160A,
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to erratum A-009007, but this one is for LX2160A and LX2162A,
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and the register value is different.
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and the register value is different.
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config SYS_FSL_ERRATUM_A010315
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config SYS_FSL_ERRATUM_A010315
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@ -362,6 +391,7 @@ config MAX_CPUS
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default 16 if ARCH_LS2080A
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default 16 if ARCH_LS2080A
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default 8 if ARCH_LS1088A
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default 8 if ARCH_LS1088A
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default 16 if ARCH_LX2160A
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default 16 if ARCH_LX2160A
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default 16 if ARCH_LX2162A
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default 1
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default 1
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help
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help
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Set this number to the maximum number of possible CPUs in the SoC.
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Set this number to the maximum number of possible CPUs in the SoC.
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@ -491,6 +521,7 @@ config SYS_FSL_DUART_CLK_DIV
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int "DUART clock divider"
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int "DUART clock divider"
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default 1 if ARCH_LS1043A
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default 1 if ARCH_LS1043A
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default 4 if ARCH_LX2160A
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default 4 if ARCH_LX2160A
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default 4 if ARCH_LX2162A
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default 2
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default 2
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help
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help
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This is the divider that is used to derive DUART clock from Platform
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This is the divider that is used to derive DUART clock from Platform
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@ -502,6 +533,7 @@ config SYS_FSL_I2C_CLK_DIV
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default 4 if ARCH_LS1012A
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default 4 if ARCH_LS1012A
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default 4 if ARCH_LS1028A
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default 4 if ARCH_LS1028A
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default 8 if ARCH_LX2160A
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default 8 if ARCH_LX2160A
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default 8 if ARCH_LX2162A
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default 8 if ARCH_LS1088A
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default 8 if ARCH_LS1088A
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default 2
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default 2
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help
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help
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@ -514,6 +546,7 @@ config SYS_FSL_IFC_CLK_DIV
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default 4 if ARCH_LS1012A
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default 4 if ARCH_LS1012A
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default 4 if ARCH_LS1028A
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default 4 if ARCH_LS1028A
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default 8 if ARCH_LX2160A
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default 8 if ARCH_LX2160A
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default 8 if ARCH_LX2162A
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default 8 if ARCH_LS1088A
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default 8 if ARCH_LS1088A
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default 2
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default 2
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help
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help
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@ -560,14 +593,14 @@ config SYS_FSL_EC1
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bool
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bool
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help
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help
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Ethernet controller 1, this is connected to
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Ethernet controller 1, this is connected to
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MAC17 for LX2160A or to MAC3 for other SoCs
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MAC17 for LX2160A and LX2162A or to MAC3 for other SoCs
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Provides DPAA2 capabilities
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Provides DPAA2 capabilities
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config SYS_FSL_EC2
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config SYS_FSL_EC2
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bool
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bool
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help
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help
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Ethernet controller 2, this is connected to
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Ethernet controller 2, this is connected to
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MAC18 for LX2160A or to MAC4 for other SoCs
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MAC18 for LX2160A and LX2162A or to MAC4 for other SoCs
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Provides DPAA2 capabilities
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Provides DPAA2 capabilities
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config SYS_FSL_ERRATUM_A008336
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config SYS_FSL_ERRATUM_A008336
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@ -27,6 +27,11 @@ obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o
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obj-y += icid.o lx2160_ids.o
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obj-y += icid.o lx2160_ids.o
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endif
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endif
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ifneq ($(CONFIG_ARCH_LX2162A),)
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obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o
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obj-y += icid.o lx2160_ids.o
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endif
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ifneq ($(CONFIG_ARCH_LS2080A),)
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ifneq ($(CONFIG_ARCH_LS2080A),)
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obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
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obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
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obj-y += icid.o ls2088_ids.o
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obj-y += icid.o ls2088_ids.o
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@ -79,6 +79,9 @@ static struct cpu_type cpu_type_list[] = {
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CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
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CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
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CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
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CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
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CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
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CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
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CPU_TYPE_ENTRY(LX2162A, LX2162A, 16),
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CPU_TYPE_ENTRY(LX2122A, LX2122A, 12),
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CPU_TYPE_ENTRY(LX2082A, LX2082A, 8),
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};
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};
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#define EARLY_PGTABLE_SIZE 0x5000
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#define EARLY_PGTABLE_SIZE 0x5000
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@ -403,7 +406,7 @@ void cpu_name(char *name)
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for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
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for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
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if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
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if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
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strcpy(name, cpu_type_list[i].name);
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strcpy(name, cpu_type_list[i].name);
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#ifdef CONFIG_ARCH_LX2160A
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#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
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if (IS_C_PROCESSOR(svr))
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if (IS_C_PROCESSOR(svr))
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strcat(name, "C");
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strcat(name, "C");
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#endif
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#endif
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@ -1229,7 +1232,7 @@ __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
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void __efi_runtime reset_cpu(ulong addr)
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void __efi_runtime reset_cpu(ulong addr)
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{
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{
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#ifdef CONFIG_ARCH_LX2160A
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#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
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/* clear the RST_REQ_MSK and SW_RST_REQ */
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/* clear the RST_REQ_MSK and SW_RST_REQ */
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out_le32(rstcr, 0x0);
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out_le32(rstcr, 0x0);
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@ -9,6 +9,7 @@ SoC overview
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7. LS2081A
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7. LS2081A
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8. LX2160A
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8. LX2160A
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9. LS1028A
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9. LS1028A
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10. LX2162A
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LS1043A
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LS1043A
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---------
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---------
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@ -379,3 +380,58 @@ The LS1028A SoC includes the following function and features:
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- Layerscape Trust Architecture
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- Layerscape Trust Architecture
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- Service Processor (SP) provides pre-boot initialization and secure-boot
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- Service Processor (SP) provides pre-boot initialization and secure-boot
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capabilities
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capabilities
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LX2162A
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--------
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The QorIQ LX2162A processor is built on the Layerscape architecture
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combining sixteen ARM A72 processor cores with advanced, high-performance
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datapath acceleration and network, peripheral interfaces required for
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networking, wireless infrastructure, storage, and general-purpose embedded
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applications.
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LX2162A is compliant with the Layerscape Chassis Generation 3.2.
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The LX2162A SoC includes the following function and features:
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Sixteen 32-bit / 64-bit ARM v8 A72 CPUs
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Cache Coherent Interconnect Fabric (CCN508)
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One 64-bit 2.9GT/s DDR4 SDRAM memory controllers with ECC.
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Data path acceleration architecture (DPAA2)
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12 Serdes lanes at up to 25 GHz
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Ethernet interfaces
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Support for 10G-SXGMII (aka USXGMII).
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Support for SGMII (and 1000Base-KX)
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Support for XFI (and 10GBase-KR)
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Support for CAUI2 (50G) and 25G-AUI(25G).
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Support for XLAUI (and 40GBase-KR4) for 40G.
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Support for two RGMII parallel interfaces.
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Energy efficient Ethernet support (802.3az)
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IEEE 1588 support.
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High-speed peripheral interfaces
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One PCIe Gen 3.0 8-lane controllers supporting SR-IOV,
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Two PCIe Gen 3.0 4-lane controllers.
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Four serial ATA (SATA 3.0) controllers.
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One USB 3.0 controllers with integrated PHY
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Two Enhanced secure digital host controllers
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Two Controller Area Network (CAN) modules
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Flexible Serial peripheral interface (FlexSPI) controller.
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Three Serial peripheral interface (SPI) controllers.
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Eight I2C Controllers.
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Four PL011 UARTs supporting two 4-pin UART ports or four 2-pin UART ports.
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General Purpose IO (GPIO)
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Support for hardware virtualization and partitioning (ARM MMU-500)
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Support for GIC (ARM GIC-500)
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QorIQ platform Trust Architecture 3.0
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One Secure WatchDog timer and one Non-Secure Watchdog timer.
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ARM Generic Timer
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Two Flextimers
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Debug supporting run control, data acquisition, high-speed trace,
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performance/event monitoring
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Thermal Monitor Unit (TMU) with +/- 2C accuracy
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Support for Voltage ID (VID) for yield improvement
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LX2162A SoC has 2 more similar SoC personalities
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1)LX2122A, few difference w.r.t. LX2162A:
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a) Twelve 64-bit ARM v8 Cortex-A72 CPUs
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2)LX2082A, few difference w.r.t. LX2162A:
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a) Eight 64-bit ARM v8 Cortex-A72 CPUs
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@ -400,11 +400,13 @@ void fdt_fixup_remove_jr(void *blob)
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while (jr_node != -FDT_ERR_NOTFOUND) {
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while (jr_node != -FDT_ERR_NOTFOUND) {
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reg = (fdt32_t *)fdt_getprop(blob, jr_node, "reg", &len);
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reg = (fdt32_t *)fdt_getprop(blob, jr_node, "reg", &len);
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if (reg) {
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jr_offset = fdt_read_number(reg, addr_cells);
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jr_offset = fdt_read_number(reg, addr_cells);
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if (jr_offset == used_jr) {
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if (jr_offset == used_jr) {
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fdt_del_node(blob, jr_node);
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fdt_del_node(blob, jr_node);
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break;
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break;
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}
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}
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||||||
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}
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jr_node = fdt_node_offset_by_compatible(blob, jr_node,
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jr_node = fdt_node_offset_by_compatible(blob, jr_node,
|
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"fsl,sec-v4.0-job-ring");
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"fsl,sec-v4.0-job-ring");
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}
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}
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0+
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// SPDX-License-Identifier: GPL-2.0+
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/*
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/*
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||||||
* Copyright 2016-2018 NXP
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* Copyright 2016-2018, 2020 NXP
|
||||||
* Copyright 2014-2015 Freescale Semiconductor, Inc.
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* Copyright 2014-2015 Freescale Semiconductor, Inc.
|
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*/
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*/
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|
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@ -26,7 +26,7 @@ static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
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#endif
|
#endif
|
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|
|
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#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
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#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
|
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#ifdef CONFIG_ARCH_LX2160A
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#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
|
||||||
int xfi_dpmac[XFI14 + 1];
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int xfi_dpmac[XFI14 + 1];
|
||||||
int sgmii_dpmac[SGMII18 + 1];
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int sgmii_dpmac[SGMII18 + 1];
|
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int a25gaui_dpmac[_25GE10 + 1];
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int a25gaui_dpmac[_25GE10 + 1];
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@ -159,7 +159,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
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|||||||
else {
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else {
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||||||
serdes_prtcl_map[lane_prtcl] = 1;
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serdes_prtcl_map[lane_prtcl] = 1;
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#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
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#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
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||||||
#ifdef CONFIG_ARCH_LX2160A
|
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
|
||||||
if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14)
|
if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14)
|
||||||
wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl],
|
wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl],
|
||||||
(int)lane_prtcl);
|
(int)lane_prtcl);
|
||||||
@ -552,7 +552,7 @@ void fsl_serdes_init(void)
|
|||||||
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
|
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
|
||||||
int i , j;
|
int i , j;
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_LX2160A
|
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
|
||||||
for (i = XFI1, j = 1; i <= XFI14; i++, j++)
|
for (i = XFI1, j = 1; i <= XFI14; i++, j++)
|
||||||
xfi_dpmac[i] = j;
|
xfi_dpmac[i] = j;
|
||||||
|
|
||||||
|
@ -1,7 +1,7 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0+
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
/*
|
/*
|
||||||
* Copyright 2014-2015, Freescale Semiconductor, Inc.
|
* Copyright 2014-2015, Freescale Semiconductor, Inc.
|
||||||
* Copyright 2019 NXP Semiconductors
|
* Copyright 2019-2020 NXP
|
||||||
*
|
*
|
||||||
* Derived from arch/power/cpu/mpc85xx/speed.c
|
* Derived from arch/power/cpu/mpc85xx/speed.c
|
||||||
*/
|
*/
|
||||||
@ -180,7 +180,7 @@ int get_clocks(void)
|
|||||||
#ifdef CONFIG_FSL_ESDHC
|
#ifdef CONFIG_FSL_ESDHC
|
||||||
#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
|
#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
|
||||||
clock = sys_info.freq_cga_m2;
|
clock = sys_info.freq_cga_m2;
|
||||||
#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A)
|
#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2162A)
|
||||||
clock = sys_info.freq_systembus;
|
clock = sys_info.freq_systembus;
|
||||||
#endif
|
#endif
|
||||||
gd->arch.sdhc_per_clk = clock / CONFIG_SYS_FSL_SDHC_CLK_DIV;
|
gd->arch.sdhc_per_clk = clock / CONFIG_SYS_FSL_SDHC_CLK_DIV;
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0+
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
/*
|
/*
|
||||||
* Copyright 2018 NXP
|
* Copyright 2018, 2020 NXP
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
@ -11,6 +11,22 @@ struct serdes_config {
|
|||||||
u8 lanes[SRDS_MAX_LANES];
|
u8 lanes[SRDS_MAX_LANES];
|
||||||
};
|
};
|
||||||
|
|
||||||
|
#if defined(CONFIG_ARCH_LX2162A)
|
||||||
|
static struct serdes_config serdes1_cfg_tbl[] = {
|
||||||
|
/* SerDes 1 */
|
||||||
|
{0x01, {PCIE1, PCIE1, PCIE1, PCIE1 } },
|
||||||
|
{0x02, {SGMII6, SGMII5, SGMII4, SGMII3 } },
|
||||||
|
{0x03, {XFI6, XFI5, XFI4, XFI3 } },
|
||||||
|
{0x09, {SGMII6, SGMII5, SGMII4, PCIE1 } },
|
||||||
|
{0x0B, {SGMII6, SGMII5, PCIE1, PCIE1 } },
|
||||||
|
{0x0F, {_50GE2, _50GE2, _50GE1, _50GE1 } },
|
||||||
|
{0x10, {_25GE6, _25GE5, _50GE1, _50GE1 } },
|
||||||
|
{0x11, {_25GE6, _25GE5, _25GE4, _25GE3 } },
|
||||||
|
{0x12, {_25GE6, _25GE5, XFI4, XFI3 } },
|
||||||
|
{0x14, {_40GE1, _40GE1, _40GE1, _40GE1 } },
|
||||||
|
{}
|
||||||
|
};
|
||||||
|
#else
|
||||||
static struct serdes_config serdes1_cfg_tbl[] = {
|
static struct serdes_config serdes1_cfg_tbl[] = {
|
||||||
/* SerDes 1 */
|
/* SerDes 1 */
|
||||||
{0x01, {PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } },
|
{0x01, {PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } },
|
||||||
@ -48,6 +64,7 @@ static struct serdes_config serdes1_cfg_tbl[] = {
|
|||||||
{0x16, {XFI10, XFI9, PCIE2, PCIE2, XFI6, XFI5, XFI4, XFI3 } },
|
{0x16, {XFI10, XFI9, PCIE2, PCIE2, XFI6, XFI5, XFI4, XFI3 } },
|
||||||
{}
|
{}
|
||||||
};
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
static struct serdes_config serdes2_cfg_tbl[] = {
|
static struct serdes_config serdes2_cfg_tbl[] = {
|
||||||
/* SerDes 2 */
|
/* SerDes 2 */
|
||||||
|
@ -1,7 +1,7 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0+
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
/*
|
/*
|
||||||
* Copyright 2014-2015 Freescale Semiconductor
|
* Copyright 2014-2015 Freescale Semiconductor
|
||||||
* Copyright 2019 NXP
|
* Copyright 2019-2020 NXP
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
@ -33,13 +33,10 @@
|
|||||||
#include <fsl_validate.h>
|
#include <fsl_validate.h>
|
||||||
#endif
|
#endif
|
||||||
#include <fsl_immap.h>
|
#include <fsl_immap.h>
|
||||||
#ifdef CONFIG_TFABOOT
|
|
||||||
#include <env_internal.h>
|
|
||||||
#endif
|
|
||||||
#include <dm.h>
|
#include <dm.h>
|
||||||
#include <dm/device_compat.h>
|
#include <dm/device_compat.h>
|
||||||
#include <linux/err.h>
|
#include <linux/err.h>
|
||||||
#if defined(CONFIG_TFABOOT) || defined(CONFIG_GIC_V3_ITS)
|
#ifdef CONFIG_GIC_V3_ITS
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
@ -186,7 +183,8 @@ static void erratum_a008997(void)
|
|||||||
out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
|
out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
|
||||||
|
|
||||||
#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
|
#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
|
||||||
defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A)
|
defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A) || \
|
||||||
|
defined(CONFIG_ARCH_LX2162A)
|
||||||
|
|
||||||
#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
|
#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
|
||||||
out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
|
out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
|
||||||
@ -222,7 +220,7 @@ static void erratum_a009007(void)
|
|||||||
#if defined(CONFIG_FSL_LSCH3)
|
#if defined(CONFIG_FSL_LSCH3)
|
||||||
static void erratum_a050106(void)
|
static void erratum_a050106(void)
|
||||||
{
|
{
|
||||||
#if defined(CONFIG_ARCH_LX2160A)
|
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
|
||||||
void __iomem *dcsr = (void __iomem *)DCSR_BASE;
|
void __iomem *dcsr = (void __iomem *)DCSR_BASE;
|
||||||
|
|
||||||
PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
|
PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
|
||||||
@ -392,7 +390,8 @@ void fsl_lsch3_early_init_f(void)
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
|
#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
|
||||||
defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
|
defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) || \
|
||||||
|
defined(CONFIG_ARCH_LX2162A)
|
||||||
set_icids();
|
set_icids();
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
@ -954,28 +953,12 @@ int board_late_init(void)
|
|||||||
#endif
|
#endif
|
||||||
#ifdef CONFIG_TFABOOT
|
#ifdef CONFIG_TFABOOT
|
||||||
/*
|
/*
|
||||||
* check if gd->env_addr is default_environment; then setenv bootcmd
|
* Set bootcmd and mcinitcmd if they don't exist in the environment.
|
||||||
* and mcinitcmd.
|
|
||||||
*/
|
*/
|
||||||
#ifdef CONFIG_SYS_RELOC_GD_ENV_ADDR
|
if (!env_get("bootcmd"))
|
||||||
if (gd->env_addr == (ulong)&default_environment[0]) {
|
|
||||||
#else
|
|
||||||
if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) {
|
|
||||||
#endif
|
|
||||||
fsl_setenv_bootcmd();
|
fsl_setenv_bootcmd();
|
||||||
|
if (!env_get("mcinitcmd"))
|
||||||
fsl_setenv_mcinitcmd();
|
fsl_setenv_mcinitcmd();
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* If the boot mode is secure, default environment is not present then
|
|
||||||
* setenv command needs to be run by default
|
|
||||||
*/
|
|
||||||
#ifdef CONFIG_CHAIN_OF_TRUST
|
|
||||||
if ((fsl_check_boot_mode_secure() == 1)) {
|
|
||||||
fsl_setenv_bootcmd();
|
|
||||||
fsl_setenv_mcinitcmd();
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
#endif
|
#endif
|
||||||
#ifdef CONFIG_QSPI_AHB_INIT
|
#ifdef CONFIG_QSPI_AHB_INIT
|
||||||
qspi_ahb_init();
|
qspi_ahb_init();
|
||||||
|
@ -414,7 +414,11 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
|
|||||||
fsl-lx2160a-qds-19-x-x.dtb \
|
fsl-lx2160a-qds-19-x-x.dtb \
|
||||||
fsl-lx2160a-qds-19-11-x.dtb \
|
fsl-lx2160a-qds-19-11-x.dtb \
|
||||||
fsl-lx2160a-qds-20-x-x.dtb \
|
fsl-lx2160a-qds-20-x-x.dtb \
|
||||||
fsl-lx2160a-qds-20-11-x.dtb
|
fsl-lx2160a-qds-20-11-x.dtb \
|
||||||
|
fsl-lx2162a-qds.dtb\
|
||||||
|
fsl-lx2162a-qds-17-x.dtb\
|
||||||
|
fsl-lx2162a-qds-18-x.dtb\
|
||||||
|
fsl-lx2162a-qds-20-x.dtb
|
||||||
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
|
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
|
||||||
fsl-ls1043a-qds-lpuart.dtb \
|
fsl-ls1043a-qds-lpuart.dtb \
|
||||||
fsl-ls1043a-rdb.dtb \
|
fsl-ls1043a-rdb.dtb \
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||||
/*
|
/*
|
||||||
|
* Copyright 2020 NXP
|
||||||
* Copyright 2016 Freescale Semiconductor
|
* Copyright 2016 Freescale Semiconductor
|
||||||
*/
|
*/
|
||||||
|
|
||||||
@ -116,7 +117,7 @@
|
|||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
pcie@3400000 {
|
pcie1: pcie@3400000 {
|
||||||
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
||||||
reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
|
reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
|
||||||
0x00 0x03480000 0x0 0x40000 /* lut registers */
|
0x00 0x03480000 0x0 0x40000 /* lut registers */
|
||||||
|
@ -2,7 +2,7 @@
|
|||||||
/*
|
/*
|
||||||
* NXP ls1028a SOC common device tree source
|
* NXP ls1028a SOC common device tree source
|
||||||
*
|
*
|
||||||
* Copyright 2019 NXP
|
* Copyright 2019-2020 NXP
|
||||||
*
|
*
|
||||||
*/
|
*/
|
||||||
|
|
||||||
@ -91,7 +91,7 @@
|
|||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
pcie@3400000 {
|
pcie1: pcie@3400000 {
|
||||||
compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
|
compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
|
||||||
reg = <0x00 0x03400000 0x0 0x80000
|
reg = <0x00 0x03400000 0x0 0x80000
|
||||||
0x00 0x03480000 0x0 0x40000 /* lut registers */
|
0x00 0x03480000 0x0 0x40000 /* lut registers */
|
||||||
@ -107,7 +107,7 @@
|
|||||||
0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||||
};
|
};
|
||||||
|
|
||||||
pcie@3500000 {
|
pcie2: pcie@3500000 {
|
||||||
compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
|
compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
|
||||||
reg = <0x00 0x03500000 0x0 0x80000
|
reg = <0x00 0x03500000 0x0 0x80000
|
||||||
0x00 0x03580000 0x0 0x40000 /* lut registers */
|
0x00 0x03580000 0x0 0x40000 /* lut registers */
|
||||||
|
@ -1,7 +1,8 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||||
/*
|
/*
|
||||||
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
|
* Device Tree Include file for NXP Layerscape-1043A family SoC.
|
||||||
*
|
*
|
||||||
|
* Copyright 2020 NXP
|
||||||
* Copyright (C) 2014-2015, Freescale Semiconductor
|
* Copyright (C) 2014-2015, Freescale Semiconductor
|
||||||
*
|
*
|
||||||
* Mingkai Hu <Mingkai.hu@freescale.com>
|
* Mingkai Hu <Mingkai.hu@freescale.com>
|
||||||
@ -240,7 +241,7 @@
|
|||||||
dr_mode = "host";
|
dr_mode = "host";
|
||||||
};
|
};
|
||||||
|
|
||||||
pcie@3400000 {
|
pcie1: pcie@3400000 {
|
||||||
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
||||||
reg = <0x00 0x03400000 0x0 0x10000 /* dbi registers */
|
reg = <0x00 0x03400000 0x0 0x10000 /* dbi registers */
|
||||||
0x00 0x03410000 0x0 0x10000 /* lut registers */
|
0x00 0x03410000 0x0 0x10000 /* lut registers */
|
||||||
@ -255,7 +256,7 @@
|
|||||||
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||||
};
|
};
|
||||||
|
|
||||||
pcie@3500000 {
|
pcie2: pcie@3500000 {
|
||||||
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
||||||
reg = <0x00 0x03500000 0x0 0x10000 /* dbi registers */
|
reg = <0x00 0x03500000 0x0 0x10000 /* dbi registers */
|
||||||
0x00 0x03510000 0x0 0x10000 /* lut registers */
|
0x00 0x03510000 0x0 0x10000 /* lut registers */
|
||||||
@ -271,7 +272,7 @@
|
|||||||
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||||
};
|
};
|
||||||
|
|
||||||
pcie@3600000 {
|
pcie3: pcie@3600000 {
|
||||||
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
||||||
reg = <0x00 0x03600000 0x0 0x10000 /* dbi registers */
|
reg = <0x00 0x03600000 0x0 0x10000 /* dbi registers */
|
||||||
0x00 0x03610000 0x0 0x10000 /* lut registers */
|
0x00 0x03610000 0x0 0x10000 /* lut registers */
|
||||||
|
@ -241,7 +241,7 @@
|
|||||||
dr_mode = "host";
|
dr_mode = "host";
|
||||||
};
|
};
|
||||||
|
|
||||||
pcie@3400000 {
|
pcie1: pcie@3400000 {
|
||||||
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
||||||
reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
|
reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
|
||||||
0x00 0x03480000 0x0 0x40000 /* lut registers */
|
0x00 0x03480000 0x0 0x40000 /* lut registers */
|
||||||
@ -257,7 +257,7 @@
|
|||||||
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||||
};
|
};
|
||||||
|
|
||||||
pcie_ep@3400000 {
|
pcie_ep1: pcie_ep@3400000 {
|
||||||
compatible = "fsl,ls-pcie-ep";
|
compatible = "fsl,ls-pcie-ep";
|
||||||
reg = <0x00 0x03400000 0x0 0x80000
|
reg = <0x00 0x03400000 0x0 0x80000
|
||||||
0x00 0x034c0000 0x0 0x40000
|
0x00 0x034c0000 0x0 0x40000
|
||||||
@ -268,7 +268,7 @@
|
|||||||
big-endian;
|
big-endian;
|
||||||
};
|
};
|
||||||
|
|
||||||
pcie@3500000 {
|
pcie2: pcie@3500000 {
|
||||||
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
||||||
reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
|
reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
|
||||||
0x00 0x03580000 0x0 0x40000 /* lut registers */
|
0x00 0x03580000 0x0 0x40000 /* lut registers */
|
||||||
@ -285,7 +285,7 @@
|
|||||||
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||||
};
|
};
|
||||||
|
|
||||||
pcie_ep@3500000 {
|
pcie_ep2: pcie_ep@3500000 {
|
||||||
compatible = "fsl,ls-pcie-ep";
|
compatible = "fsl,ls-pcie-ep";
|
||||||
reg = <0x00 0x03500000 0x0 0x80000
|
reg = <0x00 0x03500000 0x0 0x80000
|
||||||
0x00 0x035c0000 0x0 0x40000
|
0x00 0x035c0000 0x0 0x40000
|
||||||
@ -296,7 +296,7 @@
|
|||||||
big-endian;
|
big-endian;
|
||||||
};
|
};
|
||||||
|
|
||||||
pcie@3600000 {
|
pcie3: pcie@3600000 {
|
||||||
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
||||||
reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
|
reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
|
||||||
0x00 0x03680000 0x0 0x40000 /* lut registers */
|
0x00 0x03680000 0x0 0x40000 /* lut registers */
|
||||||
@ -312,7 +312,7 @@
|
|||||||
0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||||
};
|
};
|
||||||
|
|
||||||
pcie_ep@3600000 {
|
pcie_ep3: pcie_ep@3600000 {
|
||||||
compatible = "fsl,ls-pcie-ep";
|
compatible = "fsl,ls-pcie-ep";
|
||||||
reg = <0x00 0x03600000 0x0 0x80000
|
reg = <0x00 0x03600000 0x0 0x80000
|
||||||
0x00 0x036c0000 0x0 0x40000
|
0x00 0x036c0000 0x0 0x40000
|
||||||
|
@ -2,7 +2,7 @@
|
|||||||
/*
|
/*
|
||||||
* NXP ls1088a SOC common device tree source
|
* NXP ls1088a SOC common device tree source
|
||||||
*
|
*
|
||||||
* Copyright 2017 NXP
|
* Copyright 2017, 2020 NXP
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/ {
|
/ {
|
||||||
@ -135,7 +135,7 @@
|
|||||||
dr_mode = "host";
|
dr_mode = "host";
|
||||||
};
|
};
|
||||||
|
|
||||||
pcie@3400000 {
|
pcie1: pcie@3400000 {
|
||||||
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
||||||
reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
|
reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
|
||||||
0x00 0x03480000 0x0 0x80000 /* lut registers */
|
0x00 0x03480000 0x0 0x80000 /* lut registers */
|
||||||
@ -151,7 +151,7 @@
|
|||||||
0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||||
};
|
};
|
||||||
|
|
||||||
pcie@3500000 {
|
pcie2: pcie@3500000 {
|
||||||
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
||||||
reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
|
reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
|
||||||
0x00 0x03580000 0x0 0x80000 /* lut registers */
|
0x00 0x03580000 0x0 0x80000 /* lut registers */
|
||||||
@ -167,7 +167,7 @@
|
|||||||
0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||||
};
|
};
|
||||||
|
|
||||||
pcie@3600000 {
|
pcie3: pcie@3600000 {
|
||||||
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
||||||
reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
|
reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
|
||||||
0x00 0x03680000 0x0 0x80000 /* lut registers */
|
0x00 0x03680000 0x0 0x80000 /* lut registers */
|
||||||
|
@ -1,7 +1,8 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||||
/*
|
/*
|
||||||
* Freescale ls2080a SOC common device tree source
|
* NXP ls2080a SOC common device tree source
|
||||||
*
|
*
|
||||||
|
* Copyright 2020 NXP
|
||||||
* Copyright 2013-2015 Freescale Semiconductor, Inc.
|
* Copyright 2013-2015 Freescale Semiconductor, Inc.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
@ -133,7 +134,7 @@
|
|||||||
dr_mode = "host";
|
dr_mode = "host";
|
||||||
};
|
};
|
||||||
|
|
||||||
pcie@3400000 {
|
pcie1: pcie@3400000 {
|
||||||
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
||||||
reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
|
reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
|
||||||
0x00 0x03480000 0x0 0x80000 /* lut registers */
|
0x00 0x03480000 0x0 0x80000 /* lut registers */
|
||||||
@ -148,7 +149,7 @@
|
|||||||
0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||||
};
|
};
|
||||||
|
|
||||||
pcie@3500000 {
|
pcie2: pcie@3500000 {
|
||||||
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
||||||
reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
|
reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
|
||||||
0x00 0x03580000 0x0 0x80000 /* lut registers */
|
0x00 0x03580000 0x0 0x80000 /* lut registers */
|
||||||
@ -163,7 +164,7 @@
|
|||||||
0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||||
};
|
};
|
||||||
|
|
||||||
pcie@3600000 {
|
pcie3: pcie@3600000 {
|
||||||
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
||||||
reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
|
reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
|
||||||
0x00 0x03680000 0x0 0x80000 /* lut registers */
|
0x00 0x03680000 0x0 0x80000 /* lut registers */
|
||||||
@ -178,7 +179,7 @@
|
|||||||
0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||||
};
|
};
|
||||||
|
|
||||||
pcie@3700000 {
|
pcie4: pcie@3700000 {
|
||||||
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
||||||
reg = <0x00 0x03700000 0x0 0x80000 /* dbi registers */
|
reg = <0x00 0x03700000 0x0 0x80000 /* dbi registers */
|
||||||
0x00 0x03780000 0x0 0x80000 /* lut registers */
|
0x00 0x03780000 0x0 0x80000 /* lut registers */
|
||||||
|
@ -13,7 +13,4 @@
|
|||||||
/ {
|
/ {
|
||||||
model = "NXP Layerscape LX2160AQDS Board";
|
model = "NXP Layerscape LX2160AQDS Board";
|
||||||
compatible = "fsl,lx2160aqds", "fsl,lx2160a";
|
compatible = "fsl,lx2160aqds", "fsl,lx2160a";
|
||||||
aliases {
|
|
||||||
spi0 = &fspi;
|
|
||||||
};
|
|
||||||
};
|
};
|
||||||
|
@ -2,12 +2,18 @@
|
|||||||
/*
|
/*
|
||||||
* NXP LX2160AQDS common device tree source
|
* NXP LX2160AQDS common device tree source
|
||||||
*
|
*
|
||||||
* Copyright 2018-2019 NXP
|
* Copyright 2018-2020 NXP
|
||||||
*
|
*
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include "fsl-lx2160a.dtsi"
|
#include "fsl-lx2160a.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
aliases {
|
||||||
|
spi0 = &fspi;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
&dpmac17 {
|
&dpmac17 {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
phy-handle = <&rgmii_phy1>;
|
phy-handle = <&rgmii_phy1>;
|
||||||
@ -251,6 +257,20 @@
|
|||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
&fspi {
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
mt35xu512aba0: flash@0 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
compatible = "jedec,spi-nor";
|
||||||
|
spi-max-frequency = <50000000>;
|
||||||
|
reg = <0>;
|
||||||
|
spi-rx-bus-width = <8>;
|
||||||
|
spi-tx-bus-width = <1>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
&sata0 {
|
&sata0 {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
|
@ -325,7 +325,7 @@
|
|||||||
|
|
||||||
};
|
};
|
||||||
|
|
||||||
pcie@3400000 {
|
pcie1: pcie@3400000 {
|
||||||
compatible = "fsl,lx2160a-pcie";
|
compatible = "fsl,lx2160a-pcie";
|
||||||
reg = <0x00 0x03400000 0x0 0x80000 /* PAB registers */
|
reg = <0x00 0x03400000 0x0 0x80000 /* PAB registers */
|
||||||
0x00 0x03480000 0x0 0x40000 /* LUT registers */
|
0x00 0x03480000 0x0 0x40000 /* LUT registers */
|
||||||
@ -340,7 +340,7 @@
|
|||||||
0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||||
};
|
};
|
||||||
|
|
||||||
pcie@3500000 {
|
pcie2: pcie@3500000 {
|
||||||
compatible = "fsl,lx2160a-pcie";
|
compatible = "fsl,lx2160a-pcie";
|
||||||
reg = <0x00 0x03500000 0x0 0x80000 /* PAB registers */
|
reg = <0x00 0x03500000 0x0 0x80000 /* PAB registers */
|
||||||
0x00 0x03580000 0x0 0x40000 /* LUT registers */
|
0x00 0x03580000 0x0 0x40000 /* LUT registers */
|
||||||
@ -356,7 +356,7 @@
|
|||||||
0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||||
};
|
};
|
||||||
|
|
||||||
pcie@3600000 {
|
pcie3: pcie@3600000 {
|
||||||
compatible = "fsl,lx2160a-pcie";
|
compatible = "fsl,lx2160a-pcie";
|
||||||
reg = <0x00 0x03600000 0x0 0x80000 /* PAB registers */
|
reg = <0x00 0x03600000 0x0 0x80000 /* PAB registers */
|
||||||
0x00 0x03680000 0x0 0x40000 /* LUT registers */
|
0x00 0x03680000 0x0 0x40000 /* LUT registers */
|
||||||
@ -371,7 +371,7 @@
|
|||||||
0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||||
};
|
};
|
||||||
|
|
||||||
pcie@3700000 {
|
pcie4: pcie@3700000 {
|
||||||
compatible = "fsl,lx2160a-pcie";
|
compatible = "fsl,lx2160a-pcie";
|
||||||
reg = <0x00 0x03700000 0x0 0x80000 /* PAB registers */
|
reg = <0x00 0x03700000 0x0 0x80000 /* PAB registers */
|
||||||
0x00 0x03780000 0x0 0x40000 /* LUT registers */
|
0x00 0x03780000 0x0 0x40000 /* LUT registers */
|
||||||
@ -386,7 +386,7 @@
|
|||||||
0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||||
};
|
};
|
||||||
|
|
||||||
pcie@3800000 {
|
pcie5: pcie@3800000 {
|
||||||
compatible = "fsl,lx2160a-pcie";
|
compatible = "fsl,lx2160a-pcie";
|
||||||
reg = <0x00 0x03800000 0x0 0x80000 /* PAB registers */
|
reg = <0x00 0x03800000 0x0 0x80000 /* PAB registers */
|
||||||
0x00 0x03880000 0x0 0x40000 /* LUT registers */
|
0x00 0x03880000 0x0 0x40000 /* LUT registers */
|
||||||
@ -401,7 +401,7 @@
|
|||||||
0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||||
};
|
};
|
||||||
|
|
||||||
pcie@3900000 {
|
pcie6: pcie@3900000 {
|
||||||
compatible = "fsl,lx2160a-pcie";
|
compatible = "fsl,lx2160a-pcie";
|
||||||
reg = <0x00 0x03900000 0x0 0x80000 /* PAB registers */
|
reg = <0x00 0x03900000 0x0 0x80000 /* PAB registers */
|
||||||
0x00 0x03980000 0x0 0x40000 /* LUT registers */
|
0x00 0x03980000 0x0 0x40000 /* LUT registers */
|
||||||
|
17
arch/arm/dts/fsl-lx2162a-qds-17-x.dts
Normal file
17
arch/arm/dts/fsl-lx2162a-qds-17-x.dts
Normal file
@ -0,0 +1,17 @@
|
|||||||
|
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||||
|
/*
|
||||||
|
* NXP LX2162AQDS device tree source for SERDES protocol 17.x
|
||||||
|
*
|
||||||
|
* Copyright 2020 NXP
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
#include "fsl-lx2162a-qds-sd1-17.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "NXP Layerscape LX2160AQDS Board (DTS 17.x)";
|
||||||
|
compatible = "fsl,lx2162aqds", "fsl,lx2160a";
|
||||||
|
|
||||||
|
};
|
17
arch/arm/dts/fsl-lx2162a-qds-18-x.dts
Normal file
17
arch/arm/dts/fsl-lx2162a-qds-18-x.dts
Normal file
@ -0,0 +1,17 @@
|
|||||||
|
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||||
|
/*
|
||||||
|
* NXP LX2162AQDS device tree source for SERDES protocol 18.x
|
||||||
|
*
|
||||||
|
* Copyright 2020 NXP
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
#include "fsl-lx2162a-qds-sd1-18.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "NXP Layerscape LX2160AQDS Board (DTS 18.x)";
|
||||||
|
compatible = "fsl,lx2162aqds", "fsl,lx2160a";
|
||||||
|
|
||||||
|
};
|
17
arch/arm/dts/fsl-lx2162a-qds-20-x.dts
Normal file
17
arch/arm/dts/fsl-lx2162a-qds-20-x.dts
Normal file
@ -0,0 +1,17 @@
|
|||||||
|
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||||
|
/*
|
||||||
|
* NXP LX2162AQDS device tree source for SERDES protocol 20.x
|
||||||
|
*
|
||||||
|
* Copyright 2020 NXP
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
#include "fsl-lx2162a-qds-sd1-20.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "NXP Layerscape LX2160AQDS Board (DTS 20.x)";
|
||||||
|
compatible = "fsl,lx2162aqds", "fsl,lx2160a";
|
||||||
|
|
||||||
|
};
|
58
arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi
Normal file
58
arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi
Normal file
@ -0,0 +1,58 @@
|
|||||||
|
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||||
|
/*
|
||||||
|
* NXP LX2162AQDS device tree source for the SERDES block #1 - protocol 17
|
||||||
|
*
|
||||||
|
* Some assumptions are made:
|
||||||
|
* * mezzanine card M8 is connected to IO SLOT1 (25g-aui for DPMAC 3,4,5,6)
|
||||||
|
*
|
||||||
|
* Copyright 2020 NXP
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "fsl-lx2160a-qds.dtsi"
|
||||||
|
|
||||||
|
&dpmac3 {
|
||||||
|
status = "okay";
|
||||||
|
phy-handle = <&inphi_phy0>;
|
||||||
|
phy-connection-type = "25g-aui";
|
||||||
|
};
|
||||||
|
|
||||||
|
&dpmac4 {
|
||||||
|
status = "okay";
|
||||||
|
phy-handle = <&inphi_phy1>;
|
||||||
|
phy-connection-type = "25g-aui";
|
||||||
|
};
|
||||||
|
|
||||||
|
&dpmac5 {
|
||||||
|
status = "okay";
|
||||||
|
phy-handle = <&inphi_phy2>;
|
||||||
|
phy-connection-type = "25g-aui";
|
||||||
|
};
|
||||||
|
|
||||||
|
&dpmac6 {
|
||||||
|
status = "okay";
|
||||||
|
phy-handle = <&inphi_phy3>;
|
||||||
|
phy-connection-type = "25g-aui";
|
||||||
|
};
|
||||||
|
|
||||||
|
&emdio1_slot1 {
|
||||||
|
inphi_phy0: ethernet-phy@0 {
|
||||||
|
compatible = "ethernet-phy-id0210.7440";
|
||||||
|
reg = <0x0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
inphi_phy1: ethernet-phy@1 {
|
||||||
|
compatible = "ethernet-phy-id0210.7440";
|
||||||
|
reg = <0x1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
inphi_phy2: ethernet-phy@2 {
|
||||||
|
compatible = "ethernet-phy-id0210.7440";
|
||||||
|
reg = <0x2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
inphi_phy3: ethernet-phy@3 {
|
||||||
|
compatible = "ethernet-phy-id0210.7440";
|
||||||
|
reg = <0x3>;
|
||||||
|
};
|
||||||
|
};
|
61
arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi
Normal file
61
arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi
Normal file
@ -0,0 +1,61 @@
|
|||||||
|
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||||
|
/*
|
||||||
|
* NXP LX2162AQDS device tree source for the SERDES block #1 - protocol 18
|
||||||
|
*
|
||||||
|
* Some assumptions are made:
|
||||||
|
* * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4)
|
||||||
|
* * mezzanine card M13/M8 is connected to IO SLOT6 (25g-aui for DPMAC 5,6)
|
||||||
|
*
|
||||||
|
* Copyright 2020 NXP
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "fsl-lx2160a-qds.dtsi"
|
||||||
|
|
||||||
|
&dpmac3 {
|
||||||
|
status = "okay";
|
||||||
|
phy-handle = <&aquantia_phy1>;
|
||||||
|
phy-connection-type = "usxgmii";
|
||||||
|
};
|
||||||
|
|
||||||
|
&dpmac4 {
|
||||||
|
status = "okay";
|
||||||
|
phy-handle = <&aquantia_phy2>;
|
||||||
|
phy-connection-type = "usxgmii";
|
||||||
|
};
|
||||||
|
|
||||||
|
&dpmac5 {
|
||||||
|
status = "okay";
|
||||||
|
phy-handle = <&inphi_phy0>;
|
||||||
|
phy-connection-type = "25g-aui";
|
||||||
|
};
|
||||||
|
|
||||||
|
&dpmac6 {
|
||||||
|
status = "okay";
|
||||||
|
phy-handle = <&inphi_phy1>;
|
||||||
|
phy-connection-type = "25g-aui";
|
||||||
|
};
|
||||||
|
|
||||||
|
&emdio1_slot1 {
|
||||||
|
aquantia_phy1: ethernet-phy@4 {
|
||||||
|
compatible = "ethernet-phy-ieee802.3-c45";
|
||||||
|
reg = <0x0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
aquantia_phy2: ethernet-phy@5 {
|
||||||
|
compatible = "ethernet-phy-ieee802.3-c45";
|
||||||
|
reg = <0x1>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&emdio1_slot6 {
|
||||||
|
inphi_phy0: ethernet-phy@0 {
|
||||||
|
compatible = "ethernet-phy-id0210.7440";
|
||||||
|
reg = <0x0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
inphi_phy1: ethernet-phy@1 {
|
||||||
|
compatible = "ethernet-phy-id0210.7440";
|
||||||
|
reg = <0x1>;
|
||||||
|
};
|
||||||
|
};
|
26
arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi
Normal file
26
arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi
Normal file
@ -0,0 +1,26 @@
|
|||||||
|
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||||
|
/*
|
||||||
|
* NXP LX2162AQDS device tree source for the SERDES block #1 - protocol 20
|
||||||
|
*
|
||||||
|
* Some assumptions are made:
|
||||||
|
* * Mezzanine card M8 is connected to IO SLOT1
|
||||||
|
* (xlaui4 for DPMAC 1)
|
||||||
|
*
|
||||||
|
* Copyright 2020 NXP
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "fsl-lx2160a-qds.dtsi"
|
||||||
|
|
||||||
|
&dpmac1 {
|
||||||
|
status = "okay";
|
||||||
|
phy-handle = <&cortina_phy1_0>;
|
||||||
|
phy-connection-type = "xlaui4";
|
||||||
|
};
|
||||||
|
|
||||||
|
&emdio1_slot1 {
|
||||||
|
cortina_phy1_0: ethernet-phy@0 {
|
||||||
|
compatible = "ethernet-phy-ieee802.3-c45";
|
||||||
|
reg = <0x0>;
|
||||||
|
};
|
||||||
|
};
|
34
arch/arm/dts/fsl-lx2162a-qds.dts
Normal file
34
arch/arm/dts/fsl-lx2162a-qds.dts
Normal file
@ -0,0 +1,34 @@
|
|||||||
|
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||||
|
/*
|
||||||
|
* NXP LX2162AQDS device tree source
|
||||||
|
*
|
||||||
|
* Copyright 2020 NXP
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
#include "fsl-lx2160a-qds.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "NXP Layerscape LX2162AQDS Board";
|
||||||
|
compatible = "fsl,lx2162aqds", "fsl,lx2160a";
|
||||||
|
|
||||||
|
aliases {
|
||||||
|
pcie@3500000 {
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
pcie@3800000 {
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
pcie@3900000 {
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&usb1 {
|
||||||
|
status = "disabled";
|
||||||
|
};
|
@ -1,6 +1,6 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
/*
|
/*
|
||||||
* Copyright 2016-2018 NXP
|
* Copyright 2016-2018, 2020 NXP
|
||||||
* Copyright 2015, Freescale Semiconductor
|
* Copyright 2015, Freescale Semiconductor
|
||||||
*/
|
*/
|
||||||
|
|
||||||
@ -179,8 +179,8 @@
|
|||||||
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
|
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
|
||||||
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
|
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
|
||||||
|
|
||||||
/* LX2160A Soc Support */
|
/* LX2160A/LX2162A Soc Support */
|
||||||
#elif defined(CONFIG_ARCH_LX2160A)
|
#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
|
||||||
#define TZPC_BASE 0x02200000
|
#define TZPC_BASE 0x02200000
|
||||||
#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
|
#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
|
||||||
#if !defined(CONFIG_DM_I2C)
|
#if !defined(CONFIG_DM_I2C)
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
/*
|
/*
|
||||||
* Copyright 2017-2018 NXP
|
* Copyright 2017-2018, 2020 NXP
|
||||||
* Copyright 2014-2015, Freescale Semiconductor
|
* Copyright 2014-2015, Freescale Semiconductor
|
||||||
*/
|
*/
|
||||||
|
|
||||||
@ -53,7 +53,7 @@
|
|||||||
#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
|
#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
|
||||||
#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000
|
#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000
|
||||||
#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000
|
#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000
|
||||||
#ifndef CONFIG_ARCH_LX2160A
|
#if !defined(CONFIG_ARCH_LX2160A) || !defined(CONFIG_ARCH_LX2162)
|
||||||
#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000
|
#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000
|
||||||
#else
|
#else
|
||||||
#define CONFIG_SYS_FSL_PEBUF_BASE 0x1c00000000
|
#define CONFIG_SYS_FSL_PEBUF_BASE 0x1c00000000
|
||||||
|
@ -2,7 +2,7 @@
|
|||||||
/*
|
/*
|
||||||
* LayerScape Internal Memory Map
|
* LayerScape Internal Memory Map
|
||||||
*
|
*
|
||||||
* Copyright 2017-2019 NXP
|
* Copyright 2017-2020 NXP
|
||||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
@ -15,7 +15,7 @@
|
|||||||
#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
|
#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
|
||||||
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
|
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
|
||||||
#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
|
#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
|
||||||
#ifdef CONFIG_ARCH_LX2160A
|
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
|
||||||
#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180)
|
#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180)
|
||||||
#else
|
#else
|
||||||
#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
|
#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
|
||||||
@ -198,12 +198,12 @@
|
|||||||
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
|
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
|
||||||
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
|
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
|
||||||
#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000)
|
#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000)
|
||||||
#ifdef CONFIG_ARCH_LX2160A
|
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
|
||||||
#define SYS_PCIE5_ADDR (CONFIG_SYS_IMMR + 0x2800000)
|
#define SYS_PCIE5_ADDR (CONFIG_SYS_IMMR + 0x2800000)
|
||||||
#define SYS_PCIE6_ADDR (CONFIG_SYS_IMMR + 0x2900000)
|
#define SYS_PCIE6_ADDR (CONFIG_SYS_IMMR + 0x2900000)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_LX2160A
|
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
|
||||||
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL
|
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL
|
||||||
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL
|
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL
|
||||||
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x9000000000ULL
|
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x9000000000ULL
|
||||||
@ -267,7 +267,7 @@
|
|||||||
defined(CONFIG_ARCH_LS1028A)
|
defined(CONFIG_ARCH_LS1028A)
|
||||||
#define USB_PHY_RX_EQ_VAL_3 0x0380
|
#define USB_PHY_RX_EQ_VAL_3 0x0380
|
||||||
#define USB_PHY_RX_EQ_VAL_4 0x0b80
|
#define USB_PHY_RX_EQ_VAL_4 0x0b80
|
||||||
#elif defined(CONFIG_ARCH_LX2160A)
|
#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
|
||||||
#define USB_PHY_RX_EQ_VAL_3 0x0080
|
#define USB_PHY_RX_EQ_VAL_3 0x0080
|
||||||
#define USB_PHY_RX_EQ_VAL_4 0x0880
|
#define USB_PHY_RX_EQ_VAL_4 0x0880
|
||||||
#endif
|
#endif
|
||||||
@ -391,7 +391,7 @@ struct ccsr_gur {
|
|||||||
#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
|
#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
|
||||||
#define FSL_CHASSIS3_SRDS1_REGSR 29
|
#define FSL_CHASSIS3_SRDS1_REGSR 29
|
||||||
#define FSL_CHASSIS3_SRDS2_REGSR 29
|
#define FSL_CHASSIS3_SRDS2_REGSR 29
|
||||||
#elif defined(CONFIG_ARCH_LX2160A)
|
#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
|
||||||
#define FSL_CHASSIS3_EC1_REGSR 27
|
#define FSL_CHASSIS3_EC1_REGSR 27
|
||||||
#define FSL_CHASSIS3_EC2_REGSR 27
|
#define FSL_CHASSIS3_EC2_REGSR 27
|
||||||
#define FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK 0x00000003
|
#define FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK 0x00000003
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
/*
|
/*
|
||||||
* Copyright 2017-2019 NXP
|
* Copyright 2017-2020 NXP
|
||||||
* Copyright 2015 Freescale Semiconductor
|
* Copyright 2015 Freescale Semiconductor
|
||||||
*/
|
*/
|
||||||
|
|
||||||
@ -106,13 +106,16 @@ enum boot_src get_boot_src(void);
|
|||||||
#define SVR_LX2160A 0x873600
|
#define SVR_LX2160A 0x873600
|
||||||
#define SVR_LX2120A 0x873620
|
#define SVR_LX2120A 0x873620
|
||||||
#define SVR_LX2080A 0x873602
|
#define SVR_LX2080A 0x873602
|
||||||
|
#define SVR_LX2162A 0x873608
|
||||||
|
#define SVR_LX2122A 0x873628
|
||||||
|
#define SVR_LX2082A 0x87360A
|
||||||
|
|
||||||
#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
|
#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
|
||||||
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
|
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
|
||||||
#define SVR_REV(svr) (((svr) >> 0) & 0xff)
|
#define SVR_REV(svr) (((svr) >> 0) & 0xff)
|
||||||
#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
|
#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
|
||||||
#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
|
#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
|
||||||
#ifdef CONFIG_ARCH_LX2160A
|
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
|
||||||
#define IS_C_PROCESSOR(svr) (!((svr >> 12) & 0x1))
|
#define IS_C_PROCESSOR(svr) (!((svr >> 12) & 0x1))
|
||||||
#endif
|
#endif
|
||||||
#ifdef CONFIG_ARCH_LS1028A
|
#ifdef CONFIG_ARCH_LS1028A
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
/*
|
/*
|
||||||
* Copyright 2015-2019 NXP
|
* Copyright 2015-2020 NXP
|
||||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||||
*
|
*
|
||||||
*/
|
*/
|
||||||
@ -74,11 +74,13 @@
|
|||||||
#define FSL_SDMMC_STREAM_ID 3
|
#define FSL_SDMMC_STREAM_ID 3
|
||||||
#define FSL_SATA1_STREAM_ID 4
|
#define FSL_SATA1_STREAM_ID 4
|
||||||
|
|
||||||
#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
|
#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) || \
|
||||||
|
defined(CONFIG_ARCH_LX2162A)
|
||||||
#define FSL_SATA2_STREAM_ID 5
|
#define FSL_SATA2_STREAM_ID 5
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
|
#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) || \
|
||||||
|
defined(CONFIG_ARCH_LX2162A)
|
||||||
#define FSL_DMA_STREAM_ID 6
|
#define FSL_DMA_STREAM_ID 6
|
||||||
#elif defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A)
|
#elif defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A)
|
||||||
#define FSL_DMA_STREAM_ID 5
|
#define FSL_DMA_STREAM_ID 5
|
||||||
@ -91,7 +93,7 @@
|
|||||||
#define FSL_PEX_STREAM_ID_END 22
|
#define FSL_PEX_STREAM_ID_END 22
|
||||||
#elif defined(CONFIG_ARCH_LS1088A)
|
#elif defined(CONFIG_ARCH_LS1088A)
|
||||||
#define FSL_PEX_STREAM_ID_END 18
|
#define FSL_PEX_STREAM_ID_END 18
|
||||||
#elif defined(CONFIG_ARCH_LX2160A)
|
#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
|
||||||
#define FSL_PEX_STREAM_ID_END (0x100)
|
#define FSL_PEX_STREAM_ID_END (0x100)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -116,7 +116,9 @@
|
|||||||
#define CONFIG_SYS_NUM_FMAN 1
|
#define CONFIG_SYS_NUM_FMAN 1
|
||||||
#define CONFIG_SYS_NUM_FM1_DTSEC 5
|
#define CONFIG_SYS_NUM_FM1_DTSEC 5
|
||||||
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
||||||
|
#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
|
||||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
||||||
|
#endif
|
||||||
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
|
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
|
||||||
#define CONFIG_SYS_FSL_TBCLK_DIV 32
|
#define CONFIG_SYS_FSL_TBCLK_DIV 32
|
||||||
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
|
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
|
||||||
|
@ -141,4 +141,29 @@ void qixis_write_i2c(unsigned int reg, u8 value);
|
|||||||
|
|
||||||
#define QIXIS_EVDD_BY_SDHC_VS 0x0c
|
#define QIXIS_EVDD_BY_SDHC_VS 0x0c
|
||||||
|
|
||||||
|
#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) || \
|
||||||
|
defined(CONFIG_TARGET_LX2160ARDB)
|
||||||
|
#define QIXIS_XMAP_MASK 0x07
|
||||||
|
#define QIXIS_RST_CTL_RESET_EN 0x30
|
||||||
|
#define QIXIS_LBMAP_DFLTBANK 0x00
|
||||||
|
#define QIXIS_LBMAP_ALTBANK 0x20
|
||||||
|
#define QIXIS_LBMAP_QSPI 0x00
|
||||||
|
#define QIXIS_RCW_SRC_QSPI 0xff
|
||||||
|
#define QIXIS_RST_CTL_RESET 0x31
|
||||||
|
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
|
||||||
|
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
|
||||||
|
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
|
||||||
|
#define QIXIS_LBMAP_MASK 0x0f
|
||||||
|
#define QIXIS_LBMAP_SD
|
||||||
|
#define QIXIS_LBMAP_EMMC
|
||||||
|
#define QIXIS_RCW_SRC_SD 0x08
|
||||||
|
#define QIXIS_RCW_SRC_EMMC 0x09
|
||||||
|
#define NON_EXTENDED_DUTCFG
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
|
||||||
|
#define QIXIS_SDID_MASK 0x07
|
||||||
|
#define QIXIS_ESDHC_NO_ADAPTER 0x7
|
||||||
|
#endif
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
@ -175,9 +175,11 @@ static int read_eeprom(void)
|
|||||||
struct udevice *dev;
|
struct udevice *dev;
|
||||||
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
|
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
|
||||||
ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
|
ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
|
||||||
CONFIG_SYS_I2C_EEPROM_ADDR, 1, &dev);
|
CONFIG_SYS_I2C_EEPROM_ADDR,
|
||||||
|
CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev);
|
||||||
#else
|
#else
|
||||||
ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, 1, &dev);
|
ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR,
|
||||||
|
CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev);
|
||||||
#endif
|
#endif
|
||||||
if (!ret)
|
if (!ret)
|
||||||
ret = dm_i2c_read(dev, 0, (void *)&e, sizeof(e));
|
ret = dm_i2c_read(dev, 0, (void *)&e, sizeof(e));
|
||||||
|
@ -1,6 +1,7 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0+
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
/*
|
/*
|
||||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||||
|
* Copyright 2020 NXP
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
@ -484,10 +485,10 @@ int adjust_vdd(ulong vdd_override)
|
|||||||
u8 vid;
|
u8 vid;
|
||||||
#endif
|
#endif
|
||||||
int vdd_target, vdd_current, vdd_last;
|
int vdd_target, vdd_current, vdd_last;
|
||||||
int ret, i2caddress;
|
int ret, i2caddress = 0;
|
||||||
unsigned long vdd_string_override;
|
unsigned long vdd_string_override;
|
||||||
char *vdd_string;
|
char *vdd_string;
|
||||||
#ifdef CONFIG_ARCH_LX2160A
|
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
|
||||||
static const u16 vdd[32] = {
|
static const u16 vdd[32] = {
|
||||||
8250,
|
8250,
|
||||||
7875,
|
7875,
|
||||||
|
@ -1,6 +1,7 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
/*
|
/*
|
||||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||||
|
* Copyright 2020 NXP
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __VID_H_
|
#ifndef __VID_H_
|
||||||
@ -37,6 +38,35 @@
|
|||||||
*/
|
*/
|
||||||
#define EN_WRITE_ALL_CMD (0)
|
#define EN_WRITE_ALL_CMD (0)
|
||||||
|
|
||||||
|
#ifdef CONFIG_TARGET_LX2160ARDB
|
||||||
|
/* The lowest and highest voltage allowed*/
|
||||||
|
#define VDD_MV_MIN 775
|
||||||
|
#define VDD_MV_MAX 855
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
|
||||||
|
/* The lowest and highest voltage allowed*/
|
||||||
|
#define VDD_MV_MIN 775
|
||||||
|
#define VDD_MV_MAX 925
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) || \
|
||||||
|
defined(CONFIG_TARGET_LX2160ARDB)
|
||||||
|
/* PM Bus commands code for LTC3882*/
|
||||||
|
#define PWM_CHANNEL0 0x0
|
||||||
|
#define PMBUS_CMD_PAGE 0x0
|
||||||
|
#define PMBUS_CMD_READ_VOUT 0x8B
|
||||||
|
#define PMBUS_CMD_VOUT_COMMAND 0x21
|
||||||
|
#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
|
||||||
|
|
||||||
|
/* Voltage monitor on channel 2*/
|
||||||
|
#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
|
||||||
|
#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
|
||||||
|
#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
|
||||||
|
#define I2C_VOL_MONITOR_ADDR 0x63
|
||||||
|
#define I2C_MUX_CH_VOL_MONITOR 0xA
|
||||||
|
#endif
|
||||||
|
|
||||||
int adjust_vdd(ulong vdd_override);
|
int adjust_vdd(ulong vdd_override);
|
||||||
|
|
||||||
#endif /* __VID_H_ */
|
#endif /* __VID_H_ */
|
||||||
|
@ -350,6 +350,9 @@ void fdt_fixup_board_enet(void *fdt)
|
|||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
case PHY_INTERFACE_MODE_RGMII:
|
case PHY_INTERFACE_MODE_RGMII:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_TXID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_RXID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_ID:
|
||||||
fdt_status_okay_by_alias(fdt, "emi1_rgmii");
|
fdt_status_okay_by_alias(fdt, "emi1_rgmii");
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
@ -449,6 +452,9 @@ int board_eth_init(struct bd_info *bis)
|
|||||||
miiphy_get_dev_by_name("HYDRA_SGMII_MDIO"));
|
miiphy_get_dev_by_name("HYDRA_SGMII_MDIO"));
|
||||||
break;
|
break;
|
||||||
case PHY_INTERFACE_MODE_RGMII:
|
case PHY_INTERFACE_MODE_RGMII:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_TXID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_RXID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_ID:
|
||||||
/*
|
/*
|
||||||
* If DTSEC4 is RGMII, then it's routed via via EC1 to
|
* If DTSEC4 is RGMII, then it's routed via via EC1 to
|
||||||
* the first on-board RGMII port. If DTSEC5 is RGMII,
|
* the first on-board RGMII port. If DTSEC5 is RGMII,
|
||||||
|
@ -367,6 +367,9 @@ int board_eth_init(struct bd_info *bis)
|
|||||||
};
|
};
|
||||||
break;
|
break;
|
||||||
case PHY_INTERFACE_MODE_RGMII:
|
case PHY_INTERFACE_MODE_RGMII:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_TXID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_RXID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_ID:
|
||||||
fm_info_set_phy_address(i, 0);
|
fm_info_set_phy_address(i, 0);
|
||||||
mdio_mux[i] = EMI1_RGMII;
|
mdio_mux[i] = EMI1_RGMII;
|
||||||
fm_info_set_mdio(i,
|
fm_info_set_mdio(i,
|
||||||
@ -434,6 +437,9 @@ int board_eth_init(struct bd_info *bis)
|
|||||||
};
|
};
|
||||||
break;
|
break;
|
||||||
case PHY_INTERFACE_MODE_RGMII:
|
case PHY_INTERFACE_MODE_RGMII:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_TXID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_RXID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_ID:
|
||||||
fm_info_set_phy_address(i, 0);
|
fm_info_set_phy_address(i, 0);
|
||||||
mdio_mux[i] = EMI1_RGMII;
|
mdio_mux[i] = EMI1_RGMII;
|
||||||
fm_info_set_mdio(i,
|
fm_info_set_mdio(i,
|
||||||
|
@ -317,6 +317,9 @@ void fdt_fixup_board_enet(void *fdt)
|
|||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
case PHY_INTERFACE_MODE_RGMII:
|
case PHY_INTERFACE_MODE_RGMII:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_TXID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_RXID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_ID:
|
||||||
fdt_status_okay_by_alias(fdt, "hydra_rg");
|
fdt_status_okay_by_alias(fdt, "hydra_rg");
|
||||||
debug("Enabled MDIO node hydra_rg\n");
|
debug("Enabled MDIO node hydra_rg\n");
|
||||||
break;
|
break;
|
||||||
@ -353,6 +356,9 @@ void fdt_fixup_board_enet(void *fdt)
|
|||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
case PHY_INTERFACE_MODE_RGMII:
|
case PHY_INTERFACE_MODE_RGMII:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_TXID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_RXID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_ID:
|
||||||
fdt_status_okay_by_alias(fdt, "hydra_rg");
|
fdt_status_okay_by_alias(fdt, "hydra_rg");
|
||||||
debug("Enabled MDIO node hydra_rg\n");
|
debug("Enabled MDIO node hydra_rg\n");
|
||||||
break;
|
break;
|
||||||
@ -557,6 +563,9 @@ int board_eth_init(struct bd_info *bis)
|
|||||||
miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO"));
|
miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO"));
|
||||||
break;
|
break;
|
||||||
case PHY_INTERFACE_MODE_RGMII:
|
case PHY_INTERFACE_MODE_RGMII:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_TXID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_RXID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_ID:
|
||||||
/*
|
/*
|
||||||
* FM1 DTSEC5 is routed via EC1 to the first on-board
|
* FM1 DTSEC5 is routed via EC1 to the first on-board
|
||||||
* RGMII port. FM2 DTSEC5 is routed via EC2 to the
|
* RGMII port. FM2 DTSEC5 is routed via EC2 to the
|
||||||
@ -704,6 +713,9 @@ int board_eth_init(struct bd_info *bis)
|
|||||||
|
|
||||||
break;
|
break;
|
||||||
case PHY_INTERFACE_MODE_RGMII:
|
case PHY_INTERFACE_MODE_RGMII:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_TXID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_RXID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_ID:
|
||||||
/*
|
/*
|
||||||
* FM1 DTSEC5 is routed via EC1 to the first on-board
|
* FM1 DTSEC5 is routed via EC1 to the first on-board
|
||||||
* RGMII port. FM2 DTSEC5 is routed via EC2 to the
|
* RGMII port. FM2 DTSEC5 is routed via EC2 to the
|
||||||
|
@ -16,6 +16,10 @@ config SYS_LS_PFE_FW_ADDR
|
|||||||
hex "Flash address of PFE firmware"
|
hex "Flash address of PFE firmware"
|
||||||
default 0x40a00000
|
default 0x40a00000
|
||||||
|
|
||||||
|
config SYS_LS_PFE_FW_LENGTH
|
||||||
|
hex "length of PFE firmware"
|
||||||
|
default 0x40000
|
||||||
|
|
||||||
config SYS_LS_PPA_FW_ADDR
|
config SYS_LS_PPA_FW_ADDR
|
||||||
hex "PPA Firmware Addr"
|
hex "PPA Firmware Addr"
|
||||||
default 0x40400000
|
default 0x40400000
|
||||||
@ -65,6 +69,10 @@ config SYS_LS_PFE_FW_ADDR
|
|||||||
hex "Flash address of PFE firmware"
|
hex "Flash address of PFE firmware"
|
||||||
default 0x40020000
|
default 0x40020000
|
||||||
|
|
||||||
|
config SYS_LS_PFE_FW_LENGTH
|
||||||
|
hex "length of PFE firmware"
|
||||||
|
default 0x40000
|
||||||
|
|
||||||
config SYS_LS_PPA_FW_ADDR
|
config SYS_LS_PPA_FW_ADDR
|
||||||
hex "PPA Firmware Addr"
|
hex "PPA Firmware Addr"
|
||||||
default 0x40060000
|
default 0x40060000
|
||||||
@ -77,6 +85,9 @@ config SYS_LS_PFE_ESBC_ADDR
|
|||||||
hex "PFE Firmware HDR Addr"
|
hex "PFE Firmware HDR Addr"
|
||||||
default 0x401f8000
|
default 0x401f8000
|
||||||
|
|
||||||
|
config SYS_LS_PFE_ESBC_LENGTH
|
||||||
|
hex "length of PFE Firmware HDR"
|
||||||
|
default 0xc00
|
||||||
endif
|
endif
|
||||||
|
|
||||||
if TARGET_LS1012AFRDM || TARGET_LS1012AFRWY
|
if TARGET_LS1012AFRDM || TARGET_LS1012AFRWY
|
||||||
|
@ -20,6 +20,14 @@ if CHAIN_OF_TRUST
|
|||||||
config SYS_LS_PPA_ESBC_ADDR
|
config SYS_LS_PPA_ESBC_ADDR
|
||||||
hex "PPA Firmware HDR Addr"
|
hex "PPA Firmware HDR Addr"
|
||||||
default 0x40680000
|
default 0x40680000
|
||||||
|
|
||||||
|
config SYS_LS_PFE_ESBC_ADDR
|
||||||
|
hex "PFE Firmware HDR Addr"
|
||||||
|
default 0x40700000
|
||||||
|
|
||||||
|
config SYS_LS_PFE_ESBC_LENGTH
|
||||||
|
hex "length of PFE Firmware HDR"
|
||||||
|
default 0xc00
|
||||||
endif
|
endif
|
||||||
|
|
||||||
if FSL_PFE
|
if FSL_PFE
|
||||||
@ -39,9 +47,9 @@ config SYS_LS_PFE_FW_ADDR
|
|||||||
hex "Flash address of PFE firmware"
|
hex "Flash address of PFE firmware"
|
||||||
default 0x40a00000
|
default 0x40a00000
|
||||||
|
|
||||||
config SYS_LS_PFE_ESBC_ADDR
|
config SYS_LS_PFE_FW_LENGTH
|
||||||
hex "PFE Firmware HDR Addr"
|
hex "length of PFE firmware"
|
||||||
default 0x40700000
|
default 0x300000
|
||||||
|
|
||||||
config DDR_PFE_PHYS_BASEADDR
|
config DDR_PFE_PHYS_BASEADDR
|
||||||
hex "PFE DDR physical base address"
|
hex "PFE DDR physical base address"
|
||||||
|
@ -20,6 +20,14 @@ if CHAIN_OF_TRUST
|
|||||||
config SYS_LS_PPA_ESBC_ADDR
|
config SYS_LS_PPA_ESBC_ADDR
|
||||||
hex "PPA Firmware HDR Addr"
|
hex "PPA Firmware HDR Addr"
|
||||||
default 0x40680000
|
default 0x40680000
|
||||||
|
|
||||||
|
config SYS_LS_PFE_ESBC_ADDR
|
||||||
|
hex "PFE Firmware HDR Addr"
|
||||||
|
default 0x40640000
|
||||||
|
|
||||||
|
config SYS_LS_PFE_ESBC_LENGTH
|
||||||
|
hex "length of PFE Firmware HDR"
|
||||||
|
default 0xc00
|
||||||
endif
|
endif
|
||||||
|
|
||||||
if FSL_PFE
|
if FSL_PFE
|
||||||
@ -33,9 +41,9 @@ config SYS_LS_PFE_FW_ADDR
|
|||||||
hex "Flash address of PFE firmware"
|
hex "Flash address of PFE firmware"
|
||||||
default 0x40a00000
|
default 0x40a00000
|
||||||
|
|
||||||
config SYS_LS_PFE_ESBC_ADDR
|
config SYS_LS_PFE_FW_LENGTH
|
||||||
hex "PFE Firmware HDR Addr"
|
hex "length of PFE firmware"
|
||||||
default 0x40640000
|
default 0x300000
|
||||||
|
|
||||||
config DDR_PFE_PHYS_BASEADDR
|
config DDR_PFE_PHYS_BASEADDR
|
||||||
hex "PFE DDR physical base address"
|
hex "PFE DDR physical base address"
|
||||||
@ -89,6 +97,10 @@ config SYS_LS_PFE_FW_ADDR
|
|||||||
hex "Flash address of PFE firmware"
|
hex "Flash address of PFE firmware"
|
||||||
default 0x40a00000
|
default 0x40a00000
|
||||||
|
|
||||||
|
config SYS_LS_PFE_FW_LENGTH
|
||||||
|
hex "length of PFE firmware"
|
||||||
|
default 0x300000
|
||||||
|
|
||||||
config DDR_PFE_PHYS_BASEADDR
|
config DDR_PFE_PHYS_BASEADDR
|
||||||
hex "PFE DDR physical base address"
|
hex "PFE DDR physical base address"
|
||||||
default 0x03800000
|
default 0x03800000
|
||||||
|
@ -479,6 +479,8 @@ int board_eth_init(struct bd_info *bis)
|
|||||||
break;
|
break;
|
||||||
case PHY_INTERFACE_MODE_RGMII:
|
case PHY_INTERFACE_MODE_RGMII:
|
||||||
case PHY_INTERFACE_MODE_RGMII_TXID:
|
case PHY_INTERFACE_MODE_RGMII_TXID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_RXID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_ID:
|
||||||
if (i == FM1_DTSEC3)
|
if (i == FM1_DTSEC3)
|
||||||
mdio_mux[i] = EMI1_RGMII1;
|
mdio_mux[i] = EMI1_RGMII1;
|
||||||
else if (i == FM1_DTSEC4)
|
else if (i == FM1_DTSEC4)
|
||||||
|
@ -409,6 +409,8 @@ int board_eth_init(struct bd_info *bis)
|
|||||||
break;
|
break;
|
||||||
case PHY_INTERFACE_MODE_RGMII:
|
case PHY_INTERFACE_MODE_RGMII:
|
||||||
case PHY_INTERFACE_MODE_RGMII_TXID:
|
case PHY_INTERFACE_MODE_RGMII_TXID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_RXID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_ID:
|
||||||
if (i == FM1_DTSEC3)
|
if (i == FM1_DTSEC3)
|
||||||
mdio_mux[i] = EMI1_RGMII1;
|
mdio_mux[i] = EMI1_RGMII1;
|
||||||
else if (i == FM1_DTSEC4)
|
else if (i == FM1_DTSEC4)
|
||||||
|
@ -32,3 +32,19 @@ config SYS_CONFIG_NAME
|
|||||||
source "board/freescale/common/Kconfig"
|
source "board/freescale/common/Kconfig"
|
||||||
endif
|
endif
|
||||||
|
|
||||||
|
if TARGET_LX2162AQDS
|
||||||
|
|
||||||
|
config SYS_BOARD
|
||||||
|
default "lx2160a"
|
||||||
|
|
||||||
|
config SYS_VENDOR
|
||||||
|
default "freescale"
|
||||||
|
|
||||||
|
config SYS_SOC
|
||||||
|
default "fsl-layerscape"
|
||||||
|
|
||||||
|
config SYS_CONFIG_NAME
|
||||||
|
default "lx2162aqds"
|
||||||
|
|
||||||
|
source "board/freescale/common/Kconfig"
|
||||||
|
endif
|
||||||
|
@ -1,4 +1,5 @@
|
|||||||
LX2160ARDB BOARD
|
LX2160ARDB BOARD
|
||||||
|
M: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
|
||||||
M: Priyanka Jain <priyanka.jain@nxp.com>
|
M: Priyanka Jain <priyanka.jain@nxp.com>
|
||||||
S: Maintained
|
S: Maintained
|
||||||
F: board/freescale/lx2160a/
|
F: board/freescale/lx2160a/
|
||||||
@ -14,6 +15,7 @@ S: Maintained
|
|||||||
F: configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
|
F: configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
|
||||||
|
|
||||||
LX2160AQDS BOARD
|
LX2160AQDS BOARD
|
||||||
|
M: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
|
||||||
M: Pankaj Bansal <pankaj.bansal@nxp.com>
|
M: Pankaj Bansal <pankaj.bansal@nxp.com>
|
||||||
S: Maintained
|
S: Maintained
|
||||||
F: board/freescale/lx2160a/eth_lx2160aqds.h
|
F: board/freescale/lx2160a/eth_lx2160aqds.h
|
||||||
@ -25,3 +27,27 @@ LX2160AQDS_SECURE_BOOT BOARD
|
|||||||
M: Udit Agarwal <udit.agarwal@nxp.com>
|
M: Udit Agarwal <udit.agarwal@nxp.com>
|
||||||
S: Maintained
|
S: Maintained
|
||||||
F: configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
|
F: configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
|
||||||
|
|
||||||
|
LX2162AQDS BOARD
|
||||||
|
M: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
|
||||||
|
S: Maintained
|
||||||
|
F: board/freescale/lx2160a/eth_lx2162aqds.h
|
||||||
|
F: include/configs/lx2162aqds.h
|
||||||
|
F: configs/lx2162aqds_tfa_defconfig
|
||||||
|
F: arch/arm/dts/fsl-lx2162a-qds.dts
|
||||||
|
F: arch/arm/dts/fsl-lx2162a-qds-17-x.dts
|
||||||
|
F: arch/arm/dts/fsl-lx2162a-qds-18-x.dts
|
||||||
|
F: arch/arm/dts/fsl-lx2162a-qds-20-x.dts
|
||||||
|
F: arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi
|
||||||
|
F: arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi
|
||||||
|
F: arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi
|
||||||
|
|
||||||
|
LX2162AQDS_SECURE_BOOT BOARD
|
||||||
|
M: Manish Tomar <Manish.Tomar@nxp.com>
|
||||||
|
S: Maintained
|
||||||
|
F: configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
|
||||||
|
|
||||||
|
LX2162AQDS_VERIFIED_BOOT BOARD
|
||||||
|
M: Manish Tomar <Manish.Tomar@nxp.com>
|
||||||
|
S: Maintained
|
||||||
|
F: configs/lx2162aqds_tfa_verified_boot_defconfig
|
||||||
|
@ -8,3 +8,4 @@ obj-y += lx2160a.o
|
|||||||
obj-y += ddr.o
|
obj-y += ddr.o
|
||||||
obj-$(CONFIG_TARGET_LX2160ARDB) += eth_lx2160ardb.o
|
obj-$(CONFIG_TARGET_LX2160ARDB) += eth_lx2160ardb.o
|
||||||
obj-$(CONFIG_TARGET_LX2160AQDS) += eth_lx2160aqds.o
|
obj-$(CONFIG_TARGET_LX2160AQDS) += eth_lx2160aqds.o
|
||||||
|
obj-$(CONFIG_TARGET_LX2162AQDS) += eth_lx2162aqds.o
|
||||||
|
@ -195,3 +195,135 @@ SERDES3 |CARDS
|
|||||||
|Connect I/O cable to IO_SLOT6(J125)
|
|Connect I/O cable to IO_SLOT6(J125)
|
||||||
-------------------------------------------------------------------------
|
-------------------------------------------------------------------------
|
||||||
|
|
||||||
|
LX2162A SoC Overview
|
||||||
|
--------------------------------------
|
||||||
|
For details, please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
|
||||||
|
|
||||||
|
LX2162AQDS board Overview
|
||||||
|
----------------------
|
||||||
|
DDR Memory
|
||||||
|
One ports of 72-bits (8-bits ECC) DDR4.
|
||||||
|
Each port supports four chip-selects and two DIMM
|
||||||
|
connectors. Data rate upto 2.9 GT/s.
|
||||||
|
|
||||||
|
SERDES ports
|
||||||
|
Two serdes controllers (12 lanes)
|
||||||
|
Serdes1: Supports two USXGMII connectors, each connected through
|
||||||
|
Aquantia AQR107 phy, two 25GbE SFP+ modules connected through an Inphi
|
||||||
|
IN112525 phy and one 40 GbE QSFP+ module connected through an Inphi
|
||||||
|
CS4223 phy.
|
||||||
|
|
||||||
|
Serdes2: Supports two PCIe x4 (Gen3) and one PCIe x8 (Gen3) connector,
|
||||||
|
four SATA 3.0 connectors
|
||||||
|
|
||||||
|
eSDHC
|
||||||
|
eSDHC1: Supports a SD connector for connecting SD cards
|
||||||
|
eSDHC2: Supports 128GB Micron MTFC128GAJAECE-IT eMMC
|
||||||
|
|
||||||
|
Octal SPI (XSPI)
|
||||||
|
Supports two 64 MB onbpard octal SPI flash memories, one SPI emulator
|
||||||
|
for off-board emulation
|
||||||
|
|
||||||
|
I2C All system devices on I2C1 multiplexed using PCA9547 multiplexer
|
||||||
|
Serial Ports
|
||||||
|
|
||||||
|
USB 3.0
|
||||||
|
One high speed USB 3.0 ports. First USB 3.0 port configured as Host
|
||||||
|
with Type-A connector, second USB 3.0 port configured as OTG with
|
||||||
|
micro-AB connector
|
||||||
|
|
||||||
|
Serial Ports Two UART ports
|
||||||
|
Ethernet Two RGMII interfaces
|
||||||
|
Debug ARM JTAG support
|
||||||
|
|
||||||
|
Booting Options
|
||||||
|
---------------
|
||||||
|
a) Flexspi boot
|
||||||
|
b) SD boot
|
||||||
|
c) eMMC boot
|
||||||
|
|
||||||
|
Memory map for Flexspi flash
|
||||||
|
----------------------------
|
||||||
|
Image Flash Offset
|
||||||
|
bl2_flexspi_nor.pbl (RCW+PBI+bl2.pbl) 0x00000000
|
||||||
|
fip.bin (bl31 + bl33(u-boot) +
|
||||||
|
header for Secure-boot(secure-boot only)) 0x00100000
|
||||||
|
Boot firmware Environment 0x00500000
|
||||||
|
DDR PHY Firmware (fip_ddr_all.bin) 0x00800000
|
||||||
|
DPAA2 MC Firmware 0x00A00000
|
||||||
|
DPAA2 DPL 0x00D00000
|
||||||
|
DPAA2 DPC 0x00E00000
|
||||||
|
Kernel.itb 0x01000000
|
||||||
|
|
||||||
|
Memory map for sd/eMMC card
|
||||||
|
----------------------------
|
||||||
|
Image SD/eMMC card Offset
|
||||||
|
bl2_sd.pbl (RCW+PBI+bl2.pbl) 0x00008
|
||||||
|
fip.bin (bl31 + bl33(u-boot) +
|
||||||
|
header for Secure-boot(secure-boot only)) 0x00800
|
||||||
|
Boot firmware Environment 0x02800
|
||||||
|
DDR PHY Firmware (fip_ddr_all.bin) 0x04000
|
||||||
|
DPAA2 MC Firmware 0x05000
|
||||||
|
DPAA2 DPL 0x06800
|
||||||
|
DPAA2 DPC 0x07000
|
||||||
|
Kernel.itb 0x08000
|
||||||
|
|
||||||
|
Various Mezzanine cards and their connection for different SERDES protocols is
|
||||||
|
as below:
|
||||||
|
|
||||||
|
SERDES1 |CARDS
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
1 |Mezzanine:X-M4-PCIE-SGMII (29733)
|
||||||
|
|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
|
||||||
|
|Connect I/O cable to IO_SLOT1(J110)
|
||||||
|
------------------------------------------------------------------------
|
||||||
|
3 |Mezzanine:X-M11-USXGMII (29828)
|
||||||
|
|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
|
||||||
|
|Connect I/O cable to IO_SLOT1(J110)
|
||||||
|
------------------------------------------------------------------------
|
||||||
|
15 |Mezzanine:X-M8-50G (29734)
|
||||||
|
|Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108)
|
||||||
|
|Connect I/O cable to IO_SLOT1(J110)
|
||||||
|
------------------------------------------------------------------------
|
||||||
|
17 |Mezzanine:X-M13-25G (32133)
|
||||||
|
|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
|
||||||
|
|Connect I/O cable to IO_SLOT1(J110)
|
||||||
|
------------------------------------------------------------------------
|
||||||
|
18 |Mezzanine:X-M11-USXGMII (29828), X-M13-25G (32133)
|
||||||
|
|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
|
||||||
|
|Connect M11 I/O cable to IO_SLOT1(J110), M13 I/O cable to IO_SLOT6(J125)
|
||||||
|
------------------------------------------------------------------------
|
||||||
|
20 |Mezzanine:X-M7-40G (29738)
|
||||||
|
|Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108)
|
||||||
|
|Connect I/O cable to IO_SLOT1(J108)
|
||||||
|
------------------------------------------------------------------------
|
||||||
|
|
||||||
|
|
||||||
|
SERDES2 |CARDS
|
||||||
|
-----------------------------------------------------------------------
|
||||||
|
2 |Mezzanine:X-M6-PCIE-X8 (29737) *
|
||||||
|
|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)
|
||||||
|
|Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT4 (J117)
|
||||||
|
|Connect I/O cable to IO_SLOT3(J116)
|
||||||
|
------------------------------------------------------------------------
|
||||||
|
3 |Mezzanine:X-M4-PCIE-SGMII (29733)
|
||||||
|
|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)
|
||||||
|
|Connect I/O cable to IO_SLOT3(J116)
|
||||||
|
|Mezzanine:X-M4-PCIE-SGMII (29733)
|
||||||
|
|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117)
|
||||||
|
|Connect I/O cable to IO_SLOT4(J119)
|
||||||
|
------------------------------------------------------------------------
|
||||||
|
5 |Mezzanine:X-M4-PCIE-SGMII (29733)
|
||||||
|
|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)
|
||||||
|
|Connect I/O cable to IO_SLOT3(J116)
|
||||||
|
|Mezzanine:X-M5-SATA (29687)
|
||||||
|
|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117)
|
||||||
|
|Connect I/O cable to IO_SLOT4(J119)
|
||||||
|
------------------------------------------------------------------------
|
||||||
|
11 |Mezzanine:X-M4-PCIE-SGMII (29733)
|
||||||
|
|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)
|
||||||
|
|Connect I/O cable to IO_SLOT7(J127)
|
||||||
|
|Mezzanine:X-M4-PCIE-SGMII (29733)
|
||||||
|
|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117)
|
||||||
|
|Connect I/O cable to IO_SLOT8(J131)
|
||||||
|
------------------------------------------------------------------------
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0+
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
/*
|
/*
|
||||||
* Copyright 2018 NXP
|
* Copyright 2018, 2020 NXP
|
||||||
*
|
*
|
||||||
*/
|
*/
|
||||||
|
|
||||||
@ -19,6 +19,7 @@
|
|||||||
#include <asm/arch/fsl_serdes.h>
|
#include <asm/arch/fsl_serdes.h>
|
||||||
#include <fsl-mc/fsl_mc.h>
|
#include <fsl-mc/fsl_mc.h>
|
||||||
#include <fsl-mc/ldpaa_wriop.h>
|
#include <fsl-mc/ldpaa_wriop.h>
|
||||||
|
#include "lx2160a.h"
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
974
board/freescale/lx2160a/eth_lx2162aqds.c
Normal file
974
board/freescale/lx2160a/eth_lx2162aqds.c
Normal file
@ -0,0 +1,974 @@
|
|||||||
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
|
/*
|
||||||
|
* Copyright 2020 NXP
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <env.h>
|
||||||
|
#include <fdt_support.h>
|
||||||
|
#include <hwconfig.h>
|
||||||
|
#include <command.h>
|
||||||
|
#include <log.h>
|
||||||
|
#include <net.h>
|
||||||
|
#include <netdev.h>
|
||||||
|
#include <malloc.h>
|
||||||
|
#include <fsl_mdio.h>
|
||||||
|
#include <miiphy.h>
|
||||||
|
#include <phy.h>
|
||||||
|
#include <fm_eth.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
#include <exports.h>
|
||||||
|
#include <asm/arch/fsl_serdes.h>
|
||||||
|
#include <fsl-mc/fsl_mc.h>
|
||||||
|
#include <fsl-mc/ldpaa_wriop.h>
|
||||||
|
#include <linux/libfdt.h>
|
||||||
|
|
||||||
|
#include "../common/qixis.h"
|
||||||
|
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
#ifndef CONFIG_DM_ETH
|
||||||
|
#define EMI_NONE 0
|
||||||
|
#define EMI1 1 /* Mdio Bus 1 */
|
||||||
|
#define EMI2 2 /* Mdio Bus 2 */
|
||||||
|
|
||||||
|
#if defined(CONFIG_FSL_MC_ENET)
|
||||||
|
enum io_slot {
|
||||||
|
IO_SLOT_NONE = 0,
|
||||||
|
IO_SLOT_1,
|
||||||
|
IO_SLOT_2,
|
||||||
|
IO_SLOT_3,
|
||||||
|
IO_SLOT_4,
|
||||||
|
IO_SLOT_5,
|
||||||
|
IO_SLOT_6,
|
||||||
|
IO_SLOT_7,
|
||||||
|
IO_SLOT_8,
|
||||||
|
EMI1_RGMII1,
|
||||||
|
EMI1_RGMII2,
|
||||||
|
IO_SLOT_MAX
|
||||||
|
};
|
||||||
|
|
||||||
|
struct lx2162a_qds_mdio {
|
||||||
|
enum io_slot ioslot : 4;
|
||||||
|
u8 realbusnum : 4;
|
||||||
|
struct mii_dev *realbus;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* structure explaining the phy configuration on 8 lanes of a serdes*/
|
||||||
|
struct serdes_phy_config {
|
||||||
|
u8 serdes; /* serdes protocol */
|
||||||
|
struct phy_config {
|
||||||
|
u8 dpmacid;
|
||||||
|
/* -1 terminated array */
|
||||||
|
int phy_address[WRIOP_MAX_PHY_NUM + 1];
|
||||||
|
u8 mdio_bus;
|
||||||
|
enum io_slot ioslot;
|
||||||
|
} phy_config[SRDS_MAX_LANES];
|
||||||
|
};
|
||||||
|
|
||||||
|
/* Table defining the phy configuration on 8 lanes of a serdes.
|
||||||
|
* Various assumptions have been made while defining this table.
|
||||||
|
* e.g. for serdes1 protocol 19 it is being assumed that X-M11-USXGMII
|
||||||
|
* card is being used for dpmac 3-4. (X-M12-XFI could also have been used)
|
||||||
|
* And also that this card is connected to IO Slot 1 (could have been connected
|
||||||
|
* to any of the 8 IO slots (IO slot 1 - IO slot 8)).
|
||||||
|
* similarly, it is also being assumed that MDIO 1 is selected on X-M7-40G card
|
||||||
|
* used in serdes1 protocol 19 (could have selected MDIO 2)
|
||||||
|
* To override these settings "dpmac" environment variable can be used after
|
||||||
|
* defining "dpmac_override" in hwconfig environment variable.
|
||||||
|
* This table has limited serdes protocol entries. It can be expanded as per
|
||||||
|
* requirement.
|
||||||
|
*/
|
||||||
|
/*****************************************************************
|
||||||
|
*| SERDES_1 PROTOCOL | IO_SLOT | CARD |
|
||||||
|
******************************************************************
|
||||||
|
*| 2 | IO_SLOT_1 | M4-PCIE-SGMII |
|
||||||
|
*| 3 | IO_SLOT_1 | M11-USXGMII |
|
||||||
|
*| 15 | IO_SLOT_1 | M13-25G |
|
||||||
|
*| 17 | IO_SLOT_1 | M13-25G |
|
||||||
|
*| 18 | IO_SLOT_1 | M11-USXGMII |
|
||||||
|
*| | IO_SLOT_6 | M13-25G |
|
||||||
|
*| 20 | IO_SLOT_1 | M7-40G |
|
||||||
|
*****************************************************************
|
||||||
|
*/
|
||||||
|
static const struct serdes_phy_config serdes1_phy_config[] = {
|
||||||
|
{1, {} },
|
||||||
|
{2, {{WRIOP1_DPMAC3, {SGMII_CARD_PORT1_PHY_ADDR, -1},
|
||||||
|
EMI1, IO_SLOT_1},
|
||||||
|
{WRIOP1_DPMAC4, {SGMII_CARD_PORT2_PHY_ADDR, -1},
|
||||||
|
EMI1, IO_SLOT_1},
|
||||||
|
{WRIOP1_DPMAC5, {SGMII_CARD_PORT3_PHY_ADDR, -1},
|
||||||
|
EMI1, IO_SLOT_1},
|
||||||
|
{WRIOP1_DPMAC6, {SGMII_CARD_PORT4_PHY_ADDR, -1},
|
||||||
|
EMI1, IO_SLOT_1} } },
|
||||||
|
{3, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
|
||||||
|
EMI1, IO_SLOT_1},
|
||||||
|
{WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
|
||||||
|
EMI1, IO_SLOT_1},
|
||||||
|
{WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
|
||||||
|
EMI1, IO_SLOT_1},
|
||||||
|
{WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
|
||||||
|
EMI1, IO_SLOT_1} } },
|
||||||
|
{15, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
|
||||||
|
EMI1, IO_SLOT_1},
|
||||||
|
{WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
|
||||||
|
EMI1, IO_SLOT_1} } },
|
||||||
|
{17, {{WRIOP1_DPMAC3, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
|
||||||
|
EMI1, IO_SLOT_1},
|
||||||
|
{WRIOP1_DPMAC4, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
|
||||||
|
EMI1, IO_SLOT_1},
|
||||||
|
{WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
|
||||||
|
EMI1, IO_SLOT_1},
|
||||||
|
{WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
|
||||||
|
EMI1, IO_SLOT_1} } },
|
||||||
|
{18, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
|
||||||
|
EMI1, IO_SLOT_1},
|
||||||
|
{WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
|
||||||
|
EMI1, IO_SLOT_1},
|
||||||
|
{WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
|
||||||
|
EMI1, IO_SLOT_6},
|
||||||
|
{WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
|
||||||
|
EMI1, IO_SLOT_6} } },
|
||||||
|
{20, {{WRIOP1_DPMAC1, {CORTINA_PHY_ADDR1, -1},
|
||||||
|
EMI1, IO_SLOT_1} } }
|
||||||
|
};
|
||||||
|
|
||||||
|
/*****************************************************************
|
||||||
|
*| SERDES_2 PROTOCOL | IO_SLOT | CARD |
|
||||||
|
******************************************************************
|
||||||
|
*| 2 | IO_SLOT_7 | M4-PCIE-SGMII |
|
||||||
|
*| | IO_SLOT_8 | M4-PCIE-SGMII |
|
||||||
|
*| 3 | IO_SLOT_7 | M4-PCIE-SGMII |
|
||||||
|
*| | IO_SLOT_8 | M4-PCIE-SGMII |
|
||||||
|
*| 5 | IO_SLOT_7 | M4-PCIE-SGMII |
|
||||||
|
*| 10 | IO_SLOT_7 | M4-PCIE-SGMII |
|
||||||
|
*| | IO_SLOT_8 | M4-PCIE-SGMII |
|
||||||
|
*| 11 | IO_SLOT_7 | M4-PCIE-SGMII |
|
||||||
|
*| | IO_SLOT_8 | M4-PCIE-SGMII |
|
||||||
|
*| 12 | IO_SLOT_7 | M4-PCIE-SGMII |
|
||||||
|
*| | IO_SLOT_8 | M4-PCIE-SGMII |
|
||||||
|
******************************************************************
|
||||||
|
*/
|
||||||
|
static const struct serdes_phy_config serdes2_phy_config[] = {
|
||||||
|
{2, {} },
|
||||||
|
{3, {} },
|
||||||
|
{5, {} },
|
||||||
|
{10, {{WRIOP1_DPMAC11, {SGMII_CARD_PORT1_PHY_ADDR, -1},
|
||||||
|
EMI1, IO_SLOT_7},
|
||||||
|
{WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
|
||||||
|
EMI1, IO_SLOT_7},
|
||||||
|
{WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
|
||||||
|
EMI1, IO_SLOT_7},
|
||||||
|
{WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
|
||||||
|
EMI1, IO_SLOT_7} } },
|
||||||
|
{11, {{WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
|
||||||
|
EMI1, IO_SLOT_7},
|
||||||
|
{WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
|
||||||
|
EMI1, IO_SLOT_7},
|
||||||
|
{WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
|
||||||
|
EMI1, IO_SLOT_7},
|
||||||
|
{WRIOP1_DPMAC16, {SGMII_CARD_PORT2_PHY_ADDR, -1},
|
||||||
|
EMI1, IO_SLOT_8},
|
||||||
|
{WRIOP1_DPMAC13, {SGMII_CARD_PORT3_PHY_ADDR, -1},
|
||||||
|
EMI1, IO_SLOT_8},
|
||||||
|
{WRIOP1_DPMAC14, {SGMII_CARD_PORT4_PHY_ADDR, -1},
|
||||||
|
EMI1, IO_SLOT_8} } },
|
||||||
|
{12, {{WRIOP1_DPMAC11, {SGMII_CARD_PORT1_PHY_ADDR, -1},
|
||||||
|
EMI1, IO_SLOT_7},
|
||||||
|
{WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
|
||||||
|
EMI1, IO_SLOT_7},
|
||||||
|
{WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
|
||||||
|
EMI1, IO_SLOT_7},
|
||||||
|
{WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
|
||||||
|
EMI1, IO_SLOT_7} } }
|
||||||
|
};
|
||||||
|
|
||||||
|
static inline
|
||||||
|
const struct phy_config *get_phy_config(u8 serdes,
|
||||||
|
const struct serdes_phy_config *table,
|
||||||
|
u8 table_size)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for (i = 0; i < table_size; i++) {
|
||||||
|
if (table[i].serdes == serdes)
|
||||||
|
return table[i].phy_config;
|
||||||
|
}
|
||||||
|
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* BRDCFG4 controls EMI routing for the board.
|
||||||
|
* Bits Function
|
||||||
|
* 7-6 EMI Interface #1 Primary Routing (CFG_MUX1_EMI1) (1.8V):
|
||||||
|
* EMI1 00= On-board PHY #1
|
||||||
|
* 01= On-board PHY #2
|
||||||
|
* 10= (reserved)
|
||||||
|
* 11= Slots 1..8 multiplexer and translator.
|
||||||
|
* 5-3 EMI Interface #1 Secondary Routing (CFG_MUX2_EMI1) (2.5V):
|
||||||
|
* EMI1X 000= Slot #1
|
||||||
|
* 001= Slot #2
|
||||||
|
* 010= Slot #3
|
||||||
|
* 011= Slot #4
|
||||||
|
* 100= Slot #5
|
||||||
|
* 101= Slot #6
|
||||||
|
* 110= Slot #7
|
||||||
|
* 111= Slot #8
|
||||||
|
* 2-0 EMI Interface #2 Routing (CFG_MUX_EMI2):
|
||||||
|
* EMI2 000= Slot #1 (secondary EMI)
|
||||||
|
* 001= Slot #2 (secondary EMI)
|
||||||
|
* 010= Slot #3 (secondary EMI)
|
||||||
|
* 011= Slot #4 (secondary EMI)
|
||||||
|
* 100= Slot #5 (secondary EMI)
|
||||||
|
* 101= Slot #6 (secondary EMI)
|
||||||
|
* 110= Slot #7 (secondary EMI)
|
||||||
|
* 111= Slot #8 (secondary EMI)
|
||||||
|
*/
|
||||||
|
static int lx2162a_qds_get_mdio_mux_val(u8 realbusnum, enum io_slot ioslot)
|
||||||
|
{
|
||||||
|
switch (realbusnum) {
|
||||||
|
case EMI1:
|
||||||
|
switch (ioslot) {
|
||||||
|
case EMI1_RGMII1:
|
||||||
|
return 0;
|
||||||
|
case EMI1_RGMII2:
|
||||||
|
return 0x40;
|
||||||
|
default:
|
||||||
|
return (((ioslot - 1) << BRDCFG4_EMI1SEL_SHIFT) | 0xC0);
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case EMI2:
|
||||||
|
return ((ioslot - 1) << BRDCFG4_EMI2SEL_SHIFT);
|
||||||
|
default:
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void lx2162a_qds_mux_mdio(struct lx2162a_qds_mdio *priv)
|
||||||
|
{
|
||||||
|
u8 brdcfg4, mux_val, reg;
|
||||||
|
|
||||||
|
brdcfg4 = QIXIS_READ(brdcfg[4]);
|
||||||
|
reg = brdcfg4;
|
||||||
|
mux_val = lx2162a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
|
||||||
|
|
||||||
|
switch (priv->realbusnum) {
|
||||||
|
case EMI1:
|
||||||
|
brdcfg4 &= ~BRDCFG4_EMI1SEL_MASK;
|
||||||
|
brdcfg4 |= mux_val;
|
||||||
|
break;
|
||||||
|
case EMI2:
|
||||||
|
brdcfg4 &= ~BRDCFG4_EMI2SEL_MASK;
|
||||||
|
brdcfg4 |= mux_val;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (brdcfg4 ^ reg)
|
||||||
|
QIXIS_WRITE(brdcfg[4], brdcfg4);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int lx2162a_qds_mdio_read(struct mii_dev *bus, int addr,
|
||||||
|
int devad, int regnum)
|
||||||
|
{
|
||||||
|
struct lx2162a_qds_mdio *priv = bus->priv;
|
||||||
|
|
||||||
|
lx2162a_qds_mux_mdio(priv);
|
||||||
|
|
||||||
|
return priv->realbus->read(priv->realbus, addr, devad, regnum);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int lx2162a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
|
||||||
|
int regnum, u16 value)
|
||||||
|
{
|
||||||
|
struct lx2162a_qds_mdio *priv = bus->priv;
|
||||||
|
|
||||||
|
lx2162a_qds_mux_mdio(priv);
|
||||||
|
|
||||||
|
return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int lx2162a_qds_mdio_reset(struct mii_dev *bus)
|
||||||
|
{
|
||||||
|
struct lx2162a_qds_mdio *priv = bus->priv;
|
||||||
|
|
||||||
|
return priv->realbus->reset(priv->realbus);
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct mii_dev *lx2162a_qds_mdio_init(u8 realbusnum, enum io_slot ioslot)
|
||||||
|
{
|
||||||
|
struct lx2162a_qds_mdio *pmdio;
|
||||||
|
struct mii_dev *bus;
|
||||||
|
/*should be within MDIO_NAME_LEN*/
|
||||||
|
char dummy_mdio_name[] = "LX2162A_QDS_MDIO1_IOSLOT1";
|
||||||
|
|
||||||
|
if (realbusnum == EMI2) {
|
||||||
|
if (ioslot < IO_SLOT_1 || ioslot > IO_SLOT_8) {
|
||||||
|
printf("invalid ioslot %d\n", ioslot);
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
} else if (realbusnum == EMI1) {
|
||||||
|
if (ioslot < IO_SLOT_1 || ioslot > EMI1_RGMII2) {
|
||||||
|
printf("invalid ioslot %d\n", ioslot);
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
printf("not supported real mdio bus %d\n", realbusnum);
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (ioslot == EMI1_RGMII1)
|
||||||
|
strcpy(dummy_mdio_name, "LX2162A_QDS_MDIO1_RGMII1");
|
||||||
|
else if (ioslot == EMI1_RGMII2)
|
||||||
|
strcpy(dummy_mdio_name, "LX2162A_QDS_MDIO1_RGMII2");
|
||||||
|
else
|
||||||
|
sprintf(dummy_mdio_name, "LX2162A_QDS_MDIO%d_IOSLOT%d",
|
||||||
|
realbusnum, ioslot);
|
||||||
|
bus = miiphy_get_dev_by_name(dummy_mdio_name);
|
||||||
|
|
||||||
|
if (bus)
|
||||||
|
return bus;
|
||||||
|
|
||||||
|
bus = mdio_alloc();
|
||||||
|
if (!bus) {
|
||||||
|
printf("Failed to allocate %s bus\n", dummy_mdio_name);
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
pmdio = malloc(sizeof(*pmdio));
|
||||||
|
if (!pmdio) {
|
||||||
|
printf("Failed to allocate %s private data\n", dummy_mdio_name);
|
||||||
|
free(bus);
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
switch (realbusnum) {
|
||||||
|
case EMI1:
|
||||||
|
pmdio->realbus =
|
||||||
|
miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
|
||||||
|
break;
|
||||||
|
case EMI2:
|
||||||
|
pmdio->realbus =
|
||||||
|
miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!pmdio->realbus) {
|
||||||
|
printf("No real mdio bus num %d found\n", realbusnum);
|
||||||
|
free(bus);
|
||||||
|
free(pmdio);
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
pmdio->realbusnum = realbusnum;
|
||||||
|
pmdio->ioslot = ioslot;
|
||||||
|
bus->read = lx2162a_qds_mdio_read;
|
||||||
|
bus->write = lx2162a_qds_mdio_write;
|
||||||
|
bus->reset = lx2162a_qds_mdio_reset;
|
||||||
|
strcpy(bus->name, dummy_mdio_name);
|
||||||
|
bus->priv = pmdio;
|
||||||
|
|
||||||
|
if (!mdio_register(bus))
|
||||||
|
return bus;
|
||||||
|
|
||||||
|
printf("No bus with name %s\n", dummy_mdio_name);
|
||||||
|
free(bus);
|
||||||
|
free(pmdio);
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void do_phy_config(const struct phy_config *phy_config)
|
||||||
|
{
|
||||||
|
struct mii_dev *bus;
|
||||||
|
int i, phy_num, phy_address;
|
||||||
|
|
||||||
|
for (i = 0; i < SRDS_MAX_LANES; i++) {
|
||||||
|
if (!phy_config[i].dpmacid)
|
||||||
|
continue;
|
||||||
|
|
||||||
|
for (phy_num = 0;
|
||||||
|
phy_num < ARRAY_SIZE(phy_config[i].phy_address);
|
||||||
|
phy_num++) {
|
||||||
|
phy_address = phy_config[i].phy_address[phy_num];
|
||||||
|
if (phy_address == -1)
|
||||||
|
break;
|
||||||
|
wriop_set_phy_address(phy_config[i].dpmacid,
|
||||||
|
phy_num, phy_address);
|
||||||
|
}
|
||||||
|
/*Register the muxing front-ends to the MDIO buses*/
|
||||||
|
bus = lx2162a_qds_mdio_init(phy_config[i].mdio_bus,
|
||||||
|
phy_config[i].ioslot);
|
||||||
|
if (!bus)
|
||||||
|
printf("could not get bus for mdio %d ioslot %d\n",
|
||||||
|
phy_config[i].mdio_bus,
|
||||||
|
phy_config[i].ioslot);
|
||||||
|
else
|
||||||
|
wriop_set_mdio(phy_config[i].dpmacid, bus);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void do_dpmac_config(int dpmac, const char *arg_dpmacid,
|
||||||
|
char *env_dpmac)
|
||||||
|
{
|
||||||
|
const char *ret;
|
||||||
|
size_t len;
|
||||||
|
u8 realbusnum, ioslot;
|
||||||
|
struct mii_dev *bus;
|
||||||
|
int phy_num;
|
||||||
|
char *phystr = "phy00";
|
||||||
|
|
||||||
|
/*search phy in dpmac arg*/
|
||||||
|
for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
|
||||||
|
sprintf(phystr, "phy%d", phy_num + 1);
|
||||||
|
ret = hwconfig_subarg_f(arg_dpmacid, phystr, &len, env_dpmac);
|
||||||
|
if (!ret) {
|
||||||
|
/*look for phy instead of phy1*/
|
||||||
|
if (!phy_num)
|
||||||
|
ret = hwconfig_subarg_f(arg_dpmacid, "phy",
|
||||||
|
&len, env_dpmac);
|
||||||
|
if (!ret)
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (len != 4 || strncmp(ret, "0x", 2))
|
||||||
|
printf("invalid phy format in %s variable.\n"
|
||||||
|
"specify phy%d for %s in hex format e.g. 0x12\n",
|
||||||
|
env_dpmac, phy_num + 1, arg_dpmacid);
|
||||||
|
else
|
||||||
|
wriop_set_phy_address(dpmac, phy_num,
|
||||||
|
simple_strtoul(ret, NULL, 16));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*search mdio in dpmac arg*/
|
||||||
|
ret = hwconfig_subarg_f(arg_dpmacid, "mdio", &len, env_dpmac);
|
||||||
|
if (ret)
|
||||||
|
realbusnum = *ret - '0';
|
||||||
|
else
|
||||||
|
realbusnum = EMI_NONE;
|
||||||
|
|
||||||
|
if (realbusnum) {
|
||||||
|
/*search io in dpmac arg*/
|
||||||
|
ret = hwconfig_subarg_f(arg_dpmacid, "io", &len, env_dpmac);
|
||||||
|
if (ret)
|
||||||
|
ioslot = *ret - '0';
|
||||||
|
else
|
||||||
|
ioslot = IO_SLOT_NONE;
|
||||||
|
/*Register the muxing front-ends to the MDIO buses*/
|
||||||
|
bus = lx2162a_qds_mdio_init(realbusnum, ioslot);
|
||||||
|
if (!bus)
|
||||||
|
printf("could not get bus for mdio %d ioslot %d\n",
|
||||||
|
realbusnum, ioslot);
|
||||||
|
else
|
||||||
|
wriop_set_mdio(dpmac, bus);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
#endif /* !CONFIG_DM_ETH */
|
||||||
|
|
||||||
|
int board_eth_init(struct bd_info *bis)
|
||||||
|
{
|
||||||
|
#ifndef CONFIG_DM_ETH
|
||||||
|
#if defined(CONFIG_FSL_MC_ENET)
|
||||||
|
struct memac_mdio_info mdio_info;
|
||||||
|
struct memac_mdio_controller *regs;
|
||||||
|
int i;
|
||||||
|
const char *ret;
|
||||||
|
char *env_dpmac;
|
||||||
|
char dpmacid[] = "dpmac00", srds[] = "00_00_00";
|
||||||
|
size_t len;
|
||||||
|
struct mii_dev *bus;
|
||||||
|
const struct phy_config *phy_config;
|
||||||
|
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||||
|
u32 srds_s1, srds_s2;
|
||||||
|
|
||||||
|
srds_s1 = in_le32(&gur->rcwsr[28]) &
|
||||||
|
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
|
||||||
|
srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
|
||||||
|
|
||||||
|
srds_s2 = in_le32(&gur->rcwsr[28]) &
|
||||||
|
FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
|
||||||
|
srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
|
||||||
|
|
||||||
|
sprintf(srds, "%d_%d", srds_s1, srds_s2);
|
||||||
|
|
||||||
|
regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
|
||||||
|
mdio_info.regs = regs;
|
||||||
|
mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
|
||||||
|
|
||||||
|
/*Register the EMI 1*/
|
||||||
|
fm_memac_mdio_init(bis, &mdio_info);
|
||||||
|
|
||||||
|
regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
|
||||||
|
mdio_info.regs = regs;
|
||||||
|
mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
|
||||||
|
|
||||||
|
/*Register the EMI 2*/
|
||||||
|
fm_memac_mdio_init(bis, &mdio_info);
|
||||||
|
|
||||||
|
/* "dpmac" environment variable can be used after
|
||||||
|
* defining "dpmac_override" in hwconfig environment variable.
|
||||||
|
*/
|
||||||
|
if (hwconfig("dpmac_override")) {
|
||||||
|
env_dpmac = env_get("dpmac");
|
||||||
|
if (env_dpmac) {
|
||||||
|
ret = hwconfig_arg_f("srds", &len, env_dpmac);
|
||||||
|
if (ret) {
|
||||||
|
if (strncmp(ret, srds, strlen(srds))) {
|
||||||
|
printf("SERDES configuration changed.\n"
|
||||||
|
"previous: %.*s, current: %s.\n"
|
||||||
|
"update dpmac variable.\n",
|
||||||
|
(int)len, ret, srds);
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
printf("SERDES configuration not found.\n"
|
||||||
|
"Please add srds:%s in dpmac variable\n",
|
||||||
|
srds);
|
||||||
|
}
|
||||||
|
|
||||||
|
for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
|
||||||
|
/* Look for dpmac1 to dpmac24(current max) arg
|
||||||
|
* in dpmac environment variable
|
||||||
|
*/
|
||||||
|
sprintf(dpmacid, "dpmac%d", i);
|
||||||
|
ret = hwconfig_arg_f(dpmacid, &len, env_dpmac);
|
||||||
|
if (ret)
|
||||||
|
do_dpmac_config(i, dpmacid, env_dpmac);
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
printf("Warning: environment dpmac not found.\n"
|
||||||
|
"DPAA network interfaces may not work\n");
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
/*Look for phy config for serdes1 in phy config table*/
|
||||||
|
phy_config = get_phy_config(srds_s1, serdes1_phy_config,
|
||||||
|
ARRAY_SIZE(serdes1_phy_config));
|
||||||
|
if (!phy_config) {
|
||||||
|
printf("%s WRIOP: Unsupported SerDes1 Protocol %d\n",
|
||||||
|
__func__, srds_s1);
|
||||||
|
} else {
|
||||||
|
do_phy_config(phy_config);
|
||||||
|
}
|
||||||
|
phy_config = get_phy_config(srds_s2, serdes2_phy_config,
|
||||||
|
ARRAY_SIZE(serdes2_phy_config));
|
||||||
|
if (!phy_config) {
|
||||||
|
printf("%s WRIOP: Unsupported SerDes2 Protocol %d\n",
|
||||||
|
__func__, srds_s2);
|
||||||
|
} else {
|
||||||
|
do_phy_config(phy_config);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (wriop_get_enet_if(WRIOP1_DPMAC17) == PHY_INTERFACE_MODE_RGMII_ID) {
|
||||||
|
wriop_set_phy_address(WRIOP1_DPMAC17, 0, RGMII_PHY_ADDR1);
|
||||||
|
bus = lx2162a_qds_mdio_init(EMI1, EMI1_RGMII1);
|
||||||
|
if (!bus)
|
||||||
|
printf("could not get bus for RGMII1\n");
|
||||||
|
else
|
||||||
|
wriop_set_mdio(WRIOP1_DPMAC17, bus);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (wriop_get_enet_if(WRIOP1_DPMAC18) == PHY_INTERFACE_MODE_RGMII_ID) {
|
||||||
|
wriop_set_phy_address(WRIOP1_DPMAC18, 0, RGMII_PHY_ADDR2);
|
||||||
|
bus = lx2162a_qds_mdio_init(EMI1, EMI1_RGMII2);
|
||||||
|
if (!bus)
|
||||||
|
printf("could not get bus for RGMII2\n");
|
||||||
|
else
|
||||||
|
wriop_set_mdio(WRIOP1_DPMAC18, bus);
|
||||||
|
}
|
||||||
|
|
||||||
|
cpu_eth_init(bis);
|
||||||
|
#endif /* CONFIG_FMAN_ENET */
|
||||||
|
#endif /* !CONFIG_DM_ETH */
|
||||||
|
|
||||||
|
#ifdef CONFIG_PHY_AQUANTIA
|
||||||
|
/*
|
||||||
|
* Export functions to be used by AQ firmware
|
||||||
|
* upload application
|
||||||
|
*/
|
||||||
|
gd->jt->strcpy = strcpy;
|
||||||
|
gd->jt->mdelay = mdelay;
|
||||||
|
gd->jt->mdio_get_current_dev = mdio_get_current_dev;
|
||||||
|
gd->jt->phy_find_by_mask = phy_find_by_mask;
|
||||||
|
gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
|
||||||
|
gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_DM_ETH
|
||||||
|
return 0;
|
||||||
|
#else
|
||||||
|
return pci_eth_init(bis);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
#if defined(CONFIG_RESET_PHY_R)
|
||||||
|
void reset_phy(void)
|
||||||
|
{
|
||||||
|
#if defined(CONFIG_FSL_MC_ENET)
|
||||||
|
mc_env_boot();
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
#endif /* CONFIG_RESET_PHY_R */
|
||||||
|
|
||||||
|
#ifndef CONFIG_DM_ETH
|
||||||
|
#if defined(CONFIG_FSL_MC_ENET)
|
||||||
|
int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle)
|
||||||
|
{
|
||||||
|
int offset;
|
||||||
|
int ret;
|
||||||
|
char dpmac_str[] = "dpmacs@00";
|
||||||
|
const char *phy_string;
|
||||||
|
|
||||||
|
offset = fdt_path_offset(fdt, "/soc/fsl-mc/dpmacs");
|
||||||
|
|
||||||
|
if (offset < 0)
|
||||||
|
offset = fdt_path_offset(fdt, "/fsl-mc/dpmacs");
|
||||||
|
|
||||||
|
if (offset < 0) {
|
||||||
|
printf("dpmacs node not found in device tree\n");
|
||||||
|
return offset;
|
||||||
|
}
|
||||||
|
|
||||||
|
sprintf(dpmac_str, "dpmac@%x", dpmac_id);
|
||||||
|
debug("dpmac_str = %s\n", dpmac_str);
|
||||||
|
|
||||||
|
offset = fdt_subnode_offset(fdt, offset, dpmac_str);
|
||||||
|
if (offset < 0) {
|
||||||
|
printf("%s node not found in device tree\n", dpmac_str);
|
||||||
|
return offset;
|
||||||
|
}
|
||||||
|
|
||||||
|
phy_string = fdt_getprop(fdt, offset, "phy-connection-type", NULL);
|
||||||
|
if (is_backplane_mode(phy_string)) {
|
||||||
|
/* Backplane KR mode: skip fixups */
|
||||||
|
printf("Interface %d in backplane KR mode\n", dpmac_id);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = fdt_appendprop_cell(fdt, offset, "phy-handle", node_phandle);
|
||||||
|
if (ret)
|
||||||
|
printf("%d@%s %d\n", __LINE__, __func__, ret);
|
||||||
|
|
||||||
|
phy_string = phy_string_for_interface(wriop_get_enet_if(dpmac_id));
|
||||||
|
ret = fdt_setprop_string(fdt, offset, "phy-connection-type",
|
||||||
|
phy_string);
|
||||||
|
if (ret)
|
||||||
|
printf("%d@%s %d\n", __LINE__, __func__, ret);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
|
||||||
|
{
|
||||||
|
char mdio_ioslot_str[] = "mdio@00";
|
||||||
|
struct lx2162a_qds_mdio *priv;
|
||||||
|
u64 reg;
|
||||||
|
u32 phandle;
|
||||||
|
int offset, mux_val;
|
||||||
|
|
||||||
|
/*Test if the MDIO bus is real mdio bus or muxing front end ?*/
|
||||||
|
if (strncmp(mii_dev->name, "LX2162A_QDS_MDIO",
|
||||||
|
strlen("LX2162A_QDS_MDIO")))
|
||||||
|
return -1;
|
||||||
|
|
||||||
|
/*Get the real MDIO bus num and ioslot info from bus's priv data*/
|
||||||
|
priv = mii_dev->priv;
|
||||||
|
|
||||||
|
debug("real_bus_num = %d, ioslot = %d\n",
|
||||||
|
priv->realbusnum, priv->ioslot);
|
||||||
|
|
||||||
|
if (priv->realbusnum == EMI1)
|
||||||
|
reg = CONFIG_SYS_FSL_WRIOP1_MDIO1;
|
||||||
|
else
|
||||||
|
reg = CONFIG_SYS_FSL_WRIOP1_MDIO2;
|
||||||
|
|
||||||
|
offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg);
|
||||||
|
if (offset < 0) {
|
||||||
|
printf("mdio@%llx node not found in device tree\n", reg);
|
||||||
|
return offset;
|
||||||
|
}
|
||||||
|
|
||||||
|
phandle = fdt_get_phandle(fdt, offset);
|
||||||
|
phandle = cpu_to_fdt32(phandle);
|
||||||
|
offset = fdt_node_offset_by_prop_value(fdt, -1, "mdio-parent-bus",
|
||||||
|
&phandle, 4);
|
||||||
|
if (offset < 0) {
|
||||||
|
printf("mdio-mux-%d node not found in device tree\n",
|
||||||
|
priv->realbusnum == EMI1 ? 1 : 2);
|
||||||
|
return offset;
|
||||||
|
}
|
||||||
|
|
||||||
|
mux_val = lx2162a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
|
||||||
|
if (priv->realbusnum == EMI1)
|
||||||
|
mux_val >>= BRDCFG4_EMI1SEL_SHIFT;
|
||||||
|
else
|
||||||
|
mux_val >>= BRDCFG4_EMI2SEL_SHIFT;
|
||||||
|
sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val);
|
||||||
|
|
||||||
|
offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str);
|
||||||
|
if (offset < 0) {
|
||||||
|
printf("%s node not found in device tree\n", mdio_ioslot_str);
|
||||||
|
return offset;
|
||||||
|
}
|
||||||
|
|
||||||
|
return offset;
|
||||||
|
}
|
||||||
|
|
||||||
|
int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset,
|
||||||
|
struct phy_device *phy_dev, int phandle)
|
||||||
|
{
|
||||||
|
char phy_node_name[] = "ethernet-phy@00";
|
||||||
|
char phy_id_compatible_str[] = "ethernet-phy-id0000.0000,";
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
sprintf(phy_node_name, "ethernet-phy@%x", phyaddr);
|
||||||
|
debug("phy_node_name = %s\n", phy_node_name);
|
||||||
|
|
||||||
|
*subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name);
|
||||||
|
if (*subnodeoffset <= 0) {
|
||||||
|
printf("Could not add subnode %s inside node %s err = %s\n",
|
||||||
|
phy_node_name, fdt_get_name(fdt, offset, NULL),
|
||||||
|
fdt_strerror(*subnodeoffset));
|
||||||
|
return *subnodeoffset;
|
||||||
|
}
|
||||||
|
|
||||||
|
sprintf(phy_id_compatible_str, "ethernet-phy-id%04x.%04x,",
|
||||||
|
phy_dev->phy_id >> 16, phy_dev->phy_id & 0xFFFF);
|
||||||
|
debug("phy_id_compatible_str %s\n", phy_id_compatible_str);
|
||||||
|
|
||||||
|
ret = fdt_setprop_string(fdt, *subnodeoffset, "compatible",
|
||||||
|
phy_id_compatible_str);
|
||||||
|
if (ret) {
|
||||||
|
printf("%d@%s %d\n", __LINE__, __func__, ret);
|
||||||
|
goto out;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (phy_dev->is_c45) {
|
||||||
|
ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
|
||||||
|
"ethernet-phy-ieee802.3-c45");
|
||||||
|
if (ret) {
|
||||||
|
printf("%d@%s %d\n", __LINE__, __func__, ret);
|
||||||
|
goto out;
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
|
||||||
|
"ethernet-phy-ieee802.3-c22");
|
||||||
|
if (ret) {
|
||||||
|
printf("%d@%s %d\n", __LINE__, __func__, ret);
|
||||||
|
goto out;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = fdt_setprop_cell(fdt, *subnodeoffset, "reg", phyaddr);
|
||||||
|
if (ret) {
|
||||||
|
printf("%d@%s %d\n", __LINE__, __func__, ret);
|
||||||
|
goto out;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = fdt_set_phandle(fdt, *subnodeoffset, phandle);
|
||||||
|
if (ret) {
|
||||||
|
printf("%d@%s %d\n", __LINE__, __func__, ret);
|
||||||
|
goto out;
|
||||||
|
}
|
||||||
|
|
||||||
|
out:
|
||||||
|
if (ret)
|
||||||
|
fdt_del_node(fdt, *subnodeoffset);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
#define is_rgmii(dpmac_id) \
|
||||||
|
wriop_get_enet_if((dpmac_id)) == PHY_INTERFACE_MODE_RGMII_ID
|
||||||
|
|
||||||
|
int fdt_fixup_board_phy(void *fdt)
|
||||||
|
{
|
||||||
|
int fpga_offset, offset, subnodeoffset;
|
||||||
|
struct mii_dev *mii_dev;
|
||||||
|
struct list_head *mii_devs, *entry;
|
||||||
|
int ret, dpmac_id, phandle, i;
|
||||||
|
struct phy_device *phy_dev;
|
||||||
|
char ethname[ETH_NAME_LEN];
|
||||||
|
phy_interface_t phy_iface;
|
||||||
|
|
||||||
|
ret = 0;
|
||||||
|
/* we know FPGA is connected to i2c0, therefore search path directly,
|
||||||
|
* instead of compatible property, as it saves time
|
||||||
|
*/
|
||||||
|
fpga_offset = fdt_path_offset(fdt, "/soc/i2c@2000000/fpga");
|
||||||
|
|
||||||
|
if (fpga_offset < 0)
|
||||||
|
fpga_offset = fdt_path_offset(fdt, "/i2c@2000000/fpga");
|
||||||
|
|
||||||
|
if (fpga_offset < 0) {
|
||||||
|
printf("i2c@2000000/fpga node not found in device tree\n");
|
||||||
|
return fpga_offset;
|
||||||
|
}
|
||||||
|
|
||||||
|
phandle = fdt_alloc_phandle(fdt);
|
||||||
|
mii_devs = mdio_get_list_head();
|
||||||
|
|
||||||
|
list_for_each(entry, mii_devs) {
|
||||||
|
mii_dev = list_entry(entry, struct mii_dev, link);
|
||||||
|
debug("mii_dev name : %s\n", mii_dev->name);
|
||||||
|
offset = fdt_get_ioslot_offset(fdt, mii_dev, fpga_offset);
|
||||||
|
if (offset < 0)
|
||||||
|
continue;
|
||||||
|
|
||||||
|
// Look for phy devices attached to MDIO bus muxing front end
|
||||||
|
// and create their entries with compatible being the device id
|
||||||
|
for (i = 0; i < PHY_MAX_ADDR; i++) {
|
||||||
|
phy_dev = mii_dev->phymap[i];
|
||||||
|
if (!phy_dev)
|
||||||
|
continue;
|
||||||
|
|
||||||
|
// TODO: use sscanf instead of loop
|
||||||
|
dpmac_id = WRIOP1_DPMAC1;
|
||||||
|
while (dpmac_id < NUM_WRIOP_PORTS) {
|
||||||
|
phy_iface = wriop_get_enet_if(dpmac_id);
|
||||||
|
snprintf(ethname, ETH_NAME_LEN, "DPMAC%d@%s",
|
||||||
|
dpmac_id,
|
||||||
|
phy_string_for_interface(phy_iface));
|
||||||
|
if (strcmp(ethname, phy_dev->dev->name) == 0)
|
||||||
|
break;
|
||||||
|
dpmac_id++;
|
||||||
|
}
|
||||||
|
if (dpmac_id == NUM_WRIOP_PORTS)
|
||||||
|
continue;
|
||||||
|
|
||||||
|
if ((dpmac_id == 17 || dpmac_id == 18) &&
|
||||||
|
is_rgmii(dpmac_id))
|
||||||
|
continue;
|
||||||
|
|
||||||
|
ret = fdt_create_phy_node(fdt, offset, i,
|
||||||
|
&subnodeoffset,
|
||||||
|
phy_dev, phandle);
|
||||||
|
if (ret)
|
||||||
|
break;
|
||||||
|
|
||||||
|
ret = fdt_fixup_dpmac_phy_handle(fdt,
|
||||||
|
dpmac_id, phandle);
|
||||||
|
if (ret) {
|
||||||
|
fdt_del_node(fdt, subnodeoffset);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
/* calculate offset again as new node addition may have
|
||||||
|
* changed offset;
|
||||||
|
*/
|
||||||
|
offset = fdt_get_ioslot_offset(fdt, mii_dev,
|
||||||
|
fpga_offset);
|
||||||
|
phandle++;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (ret)
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
#endif // CONFIG_FSL_MC_ENET
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT)
|
||||||
|
|
||||||
|
/* Structure to hold SERDES protocols supported in case of
|
||||||
|
* CONFIG_DM_ETH enabled (network interfaces are described in the DTS).
|
||||||
|
*
|
||||||
|
* @serdes_block: the index of the SERDES block
|
||||||
|
* @serdes_protocol: the decimal value of the protocol supported
|
||||||
|
* @dts_needed: DTS notes describing the current configuration are needed
|
||||||
|
*
|
||||||
|
* When dts_needed is true, the board_fit_config_name_match() function
|
||||||
|
* will try to exactly match the current configuration of the block with a DTS
|
||||||
|
* name provided.
|
||||||
|
*/
|
||||||
|
static struct serdes_configuration {
|
||||||
|
u8 serdes_block;
|
||||||
|
u32 serdes_protocol;
|
||||||
|
bool dts_needed;
|
||||||
|
} supported_protocols[] = {
|
||||||
|
/* Serdes block #1 */
|
||||||
|
{1, 2, true},
|
||||||
|
{1, 3, true},
|
||||||
|
{1, 15, true},
|
||||||
|
{1, 17, true},
|
||||||
|
{1, 18, true},
|
||||||
|
{1, 20, true},
|
||||||
|
|
||||||
|
/* Serdes block #2 */
|
||||||
|
{2, 2, false},
|
||||||
|
{2, 3, false},
|
||||||
|
{2, 5, false},
|
||||||
|
{2, 10, false},
|
||||||
|
{2, 11, true},
|
||||||
|
{2, 12, true},
|
||||||
|
};
|
||||||
|
|
||||||
|
#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols)
|
||||||
|
|
||||||
|
static bool protocol_supported(u8 serdes_block, u32 protocol)
|
||||||
|
{
|
||||||
|
struct serdes_configuration serdes_conf;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
|
||||||
|
serdes_conf = supported_protocols[i];
|
||||||
|
if (serdes_conf.serdes_block == serdes_block &&
|
||||||
|
serdes_conf.serdes_protocol == protocol)
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
|
||||||
|
{
|
||||||
|
struct serdes_configuration serdes_conf;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
|
||||||
|
serdes_conf = supported_protocols[i];
|
||||||
|
if (serdes_conf.serdes_block == serdes_block &&
|
||||||
|
serdes_conf.serdes_protocol == protocol) {
|
||||||
|
if (serdes_conf.dts_needed == true)
|
||||||
|
sprintf(str, "%u", protocol);
|
||||||
|
else
|
||||||
|
sprintf(str, "x");
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
int board_fit_config_name_match(const char *name)
|
||||||
|
{
|
||||||
|
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||||
|
u32 rcw_status = in_le32(&gur->rcwsr[28]);
|
||||||
|
char srds_s1_str[2], srds_s2_str[2];
|
||||||
|
u32 srds_s1, srds_s2;
|
||||||
|
char expected_dts[100];
|
||||||
|
|
||||||
|
srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
|
||||||
|
srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
|
||||||
|
|
||||||
|
srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
|
||||||
|
srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
|
||||||
|
|
||||||
|
/* Check for supported protocols. The default DTS will be used
|
||||||
|
* in this case
|
||||||
|
*/
|
||||||
|
if (!protocol_supported(1, srds_s1) ||
|
||||||
|
!protocol_supported(2, srds_s2))
|
||||||
|
return -1;
|
||||||
|
|
||||||
|
get_str_protocol(1, srds_s1, srds_s1_str);
|
||||||
|
get_str_protocol(2, srds_s2, srds_s2_str);
|
||||||
|
|
||||||
|
sprintf(expected_dts, "fsl-lx2160a-qds-%s-%s",
|
||||||
|
srds_s1_str, srds_s2_str);
|
||||||
|
|
||||||
|
if (!strcmp(name, expected_dts))
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
#endif
|
@ -32,12 +32,13 @@
|
|||||||
#include "../common/vid.h"
|
#include "../common/vid.h"
|
||||||
#include <fsl_immap.h>
|
#include <fsl_immap.h>
|
||||||
#include <asm/arch-fsl-layerscape/fsl_icid.h>
|
#include <asm/arch-fsl-layerscape/fsl_icid.h>
|
||||||
|
#include "lx2160a.h"
|
||||||
|
|
||||||
#ifdef CONFIG_EMC2305
|
#ifdef CONFIG_EMC2305
|
||||||
#include "../common/emc2305.h"
|
#include "../common/emc2305.h"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_TARGET_LX2160AQDS
|
#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
|
||||||
#define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value)
|
#define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value)
|
||||||
#define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f)
|
#define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f)
|
||||||
#define SET_CFG_MUX2_SDHC1_SPI(reg, value) ((reg & 0xcf) | value)
|
#define SET_CFG_MUX2_SDHC1_SPI(reg, value) ((reg & 0xcf) | value)
|
||||||
@ -47,7 +48,7 @@
|
|||||||
#define SDHC1_BASE_PMUX_DSPI 2
|
#define SDHC1_BASE_PMUX_DSPI 2
|
||||||
#define SDHC2_BASE_PMUX_DSPI 2
|
#define SDHC2_BASE_PMUX_DSPI 2
|
||||||
#define IIC5_PMUX_SPI3 3
|
#define IIC5_PMUX_SPI3 3
|
||||||
#endif /* CONFIG_TARGET_LX2160AQDS */
|
#endif /* CONFIG_TARGET_LX2160AQDS or CONFIG_TARGET_LX2162AQDS */
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
@ -191,7 +192,7 @@ int board_fix_fdt(void *fdt)
|
|||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(CONFIG_TARGET_LX2160AQDS)
|
#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
|
||||||
void esdhc_dspi_status_fixup(void *blob)
|
void esdhc_dspi_status_fixup(void *blob)
|
||||||
{
|
{
|
||||||
const char esdhc0_path[] = "/soc/esdhc@2140000";
|
const char esdhc0_path[] = "/soc/esdhc@2140000";
|
||||||
@ -259,7 +260,7 @@ void esdhc_dspi_status_fixup(void *blob)
|
|||||||
|
|
||||||
int esdhc_status_fixup(void *blob, const char *compat)
|
int esdhc_status_fixup(void *blob, const char *compat)
|
||||||
{
|
{
|
||||||
#if defined(CONFIG_TARGET_LX2160AQDS)
|
#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
|
||||||
/* Enable esdhc and dspi DT nodes based on RCW fields */
|
/* Enable esdhc and dspi DT nodes based on RCW fields */
|
||||||
esdhc_dspi_status_fixup(blob);
|
esdhc_dspi_status_fixup(blob);
|
||||||
#else
|
#else
|
||||||
@ -297,7 +298,7 @@ int checkboard(void)
|
|||||||
enum boot_src src = get_boot_src();
|
enum boot_src src = get_boot_src();
|
||||||
char buf[64];
|
char buf[64];
|
||||||
u8 sw;
|
u8 sw;
|
||||||
#ifdef CONFIG_TARGET_LX2160AQDS
|
#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
|
||||||
int clock;
|
int clock;
|
||||||
static const char *const freq[] = {"100", "125", "156.25",
|
static const char *const freq[] = {"100", "125", "156.25",
|
||||||
"161.13", "322.26", "", "", "",
|
"161.13", "322.26", "", "", "",
|
||||||
@ -306,7 +307,7 @@ int checkboard(void)
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
cpu_name(buf);
|
cpu_name(buf);
|
||||||
#ifdef CONFIG_TARGET_LX2160AQDS
|
#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
|
||||||
printf("Board: %s-QDS, ", buf);
|
printf("Board: %s-QDS, ", buf);
|
||||||
#else
|
#else
|
||||||
printf("Board: %s-RDB, ", buf);
|
printf("Board: %s-RDB, ", buf);
|
||||||
@ -339,7 +340,13 @@ int checkboard(void)
|
|||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
#ifdef CONFIG_TARGET_LX2160AQDS
|
#if defined(CONFIG_TARGET_LX2160ARDB)
|
||||||
|
printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
|
||||||
|
|
||||||
|
puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
|
||||||
|
puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
|
||||||
|
puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
|
||||||
|
#else
|
||||||
printf("FPGA: v%d (%s), build %d",
|
printf("FPGA: v%d (%s), build %d",
|
||||||
(int)QIXIS_READ(scver), qixis_read_tag(buf),
|
(int)QIXIS_READ(scver), qixis_read_tag(buf),
|
||||||
(int)qixis_read_minor());
|
(int)qixis_read_minor());
|
||||||
@ -350,31 +357,27 @@ int checkboard(void)
|
|||||||
sw = QIXIS_READ(brdcfg[2]);
|
sw = QIXIS_READ(brdcfg[2]);
|
||||||
clock = sw >> 4;
|
clock = sw >> 4;
|
||||||
printf("Clock1 = %sMHz ", freq[clock]);
|
printf("Clock1 = %sMHz ", freq[clock]);
|
||||||
|
#if defined(CONFIG_TARGET_LX2160AQDS)
|
||||||
clock = sw & 0x0f;
|
clock = sw & 0x0f;
|
||||||
printf("Clock2 = %sMHz", freq[clock]);
|
printf("Clock2 = %sMHz", freq[clock]);
|
||||||
|
#endif
|
||||||
sw = QIXIS_READ(brdcfg[3]);
|
sw = QIXIS_READ(brdcfg[3]);
|
||||||
puts("\nSERDES2 Reference : ");
|
puts("\nSERDES2 Reference : ");
|
||||||
clock = sw >> 4;
|
clock = sw >> 4;
|
||||||
printf("Clock1 = %sMHz ", freq[clock]);
|
printf("Clock1 = %sMHz ", freq[clock]);
|
||||||
clock = sw & 0x0f;
|
clock = sw & 0x0f;
|
||||||
printf("Clock2 = %sMHz", freq[clock]);
|
printf("Clock2 = %sMHz\n", freq[clock]);
|
||||||
|
#if defined(CONFIG_TARGET_LX2160AQDS)
|
||||||
sw = QIXIS_READ(brdcfg[12]);
|
sw = QIXIS_READ(brdcfg[12]);
|
||||||
puts("\nSERDES3 Reference : ");
|
puts("SERDES3 Reference : ");
|
||||||
clock = sw >> 4;
|
clock = sw >> 4;
|
||||||
printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
|
printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
|
||||||
#else
|
#endif
|
||||||
printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
|
|
||||||
|
|
||||||
puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
|
|
||||||
puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
|
|
||||||
puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
|
|
||||||
#endif
|
#endif
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_TARGET_LX2160AQDS
|
#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
|
||||||
/*
|
/*
|
||||||
* implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
|
* implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
|
||||||
*/
|
*/
|
||||||
@ -562,7 +565,7 @@ int config_board_mux(void)
|
|||||||
|
|
||||||
unsigned long get_board_sys_clk(void)
|
unsigned long get_board_sys_clk(void)
|
||||||
{
|
{
|
||||||
#ifdef CONFIG_TARGET_LX2160AQDS
|
#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
|
||||||
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
|
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
|
||||||
|
|
||||||
switch (sysclk_conf & 0x03) {
|
switch (sysclk_conf & 0x03) {
|
||||||
@ -581,7 +584,7 @@ unsigned long get_board_sys_clk(void)
|
|||||||
|
|
||||||
unsigned long get_board_ddr_clk(void)
|
unsigned long get_board_ddr_clk(void)
|
||||||
{
|
{
|
||||||
#ifdef CONFIG_TARGET_LX2160AQDS
|
#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
|
||||||
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
|
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
|
||||||
|
|
||||||
switch ((ddrclk_conf & 0x30) >> 4) {
|
switch ((ddrclk_conf & 0x30) >> 4) {
|
||||||
|
61
board/freescale/lx2160a/lx2160a.h
Normal file
61
board/freescale/lx2160a/lx2160a.h
Normal file
@ -0,0 +1,61 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
|
/*
|
||||||
|
* Copyright 2020 NXP
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __LX2160_H
|
||||||
|
#define __LX2160_H
|
||||||
|
|
||||||
|
#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
|
||||||
|
/* SYSCLK */
|
||||||
|
#define QIXIS_SYSCLK_100 0x0
|
||||||
|
#define QIXIS_SYSCLK_125 0x1
|
||||||
|
#define QIXIS_SYSCLK_133 0x2
|
||||||
|
|
||||||
|
/* DDRCLK */
|
||||||
|
#define QIXIS_DDRCLK_100 0x0
|
||||||
|
#define QIXIS_DDRCLK_125 0x1
|
||||||
|
#define QIXIS_DDRCLK_133 0x2
|
||||||
|
|
||||||
|
#define BRDCFG4_EMI1SEL_MASK 0xF8
|
||||||
|
#define BRDCFG4_EMI1SEL_SHIFT 3
|
||||||
|
#define BRDCFG4_EMI2SEL_MASK 0x07
|
||||||
|
#define BRDCFG4_EMI2SEL_SHIFT 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define QIXIS_XMAP_SHIFT 5
|
||||||
|
|
||||||
|
/* RTC */
|
||||||
|
#define I2C_MUX_CH_RTC 0xB
|
||||||
|
|
||||||
|
/* MAC/PHY configuration */
|
||||||
|
#if defined(CONFIG_FSL_MC_ENET)
|
||||||
|
#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
|
||||||
|
#define AQ_PHY_ADDR1 0x00
|
||||||
|
#define AQ_PHY_ADDR2 0x01
|
||||||
|
#define AQ_PHY_ADDR3 0x02
|
||||||
|
#define AQ_PHY_ADDR4 0x03
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_TARGET_LX2160ARDB
|
||||||
|
#define AQR107_PHY_ADDR1 0x04
|
||||||
|
#define AQR107_PHY_ADDR2 0x05
|
||||||
|
#define AQR107_IRQ_MASK 0x0C
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define CORTINA_PHY_ADDR1 0x0
|
||||||
|
#define INPHI_PHY_ADDR1 0x0
|
||||||
|
|
||||||
|
#define RGMII_PHY_ADDR1 0x01
|
||||||
|
#define RGMII_PHY_ADDR2 0x02
|
||||||
|
|
||||||
|
#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
|
||||||
|
#define INPHI_PHY_ADDR2 0x1
|
||||||
|
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
|
||||||
|
#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
|
||||||
|
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
|
||||||
|
#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __LX2160_H */
|
@ -81,17 +81,21 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
|
|||||||
{
|
{
|
||||||
phy_interface_t intf = fm_info_get_enet_if(port);
|
phy_interface_t intf = fm_info_get_enet_if(port);
|
||||||
char phy[16];
|
char phy[16];
|
||||||
|
int lane;
|
||||||
|
u8 slot;
|
||||||
|
|
||||||
|
switch (intf) {
|
||||||
/* The RGMII PHY is identified by the MAC connected to it */
|
/* The RGMII PHY is identified by the MAC connected to it */
|
||||||
if (intf == PHY_INTERFACE_MODE_RGMII) {
|
case PHY_INTERFACE_MODE_RGMII:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_TXID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_RXID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_ID:
|
||||||
sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC5 ? 0 : 1);
|
sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC5 ? 0 : 1);
|
||||||
fdt_set_phy_handle(fdt, compat, addr, phy);
|
fdt_set_phy_handle(fdt, compat, addr, phy);
|
||||||
}
|
break;
|
||||||
|
|
||||||
/* The SGMII PHY is identified by the MAC connected to it */
|
/* The SGMII PHY is identified by the MAC connected to it */
|
||||||
if (intf == PHY_INTERFACE_MODE_SGMII) {
|
case PHY_INTERFACE_MODE_SGMII:
|
||||||
int lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port);
|
lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port);
|
||||||
u8 slot;
|
|
||||||
if (lane < 0)
|
if (lane < 0)
|
||||||
return;
|
return;
|
||||||
slot = lane_to_slot[lane];
|
slot = lane_to_slot[lane];
|
||||||
@ -106,16 +110,18 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
|
|||||||
+ (port - FM1_DTSEC1));
|
+ (port - FM1_DTSEC1));
|
||||||
fdt_set_phy_handle(fdt, compat, addr, phy);
|
fdt_set_phy_handle(fdt, compat, addr, phy);
|
||||||
}
|
}
|
||||||
}
|
break;
|
||||||
|
case PHY_INTERFACE_MODE_XGMII:
|
||||||
if (intf == PHY_INTERFACE_MODE_XGMII) {
|
|
||||||
/* XAUI */
|
/* XAUI */
|
||||||
int lane = serdes_get_first_lane(XAUI_FM1);
|
lane = serdes_get_first_lane(XAUI_FM1);
|
||||||
if (lane >= 0) {
|
if (lane >= 0) {
|
||||||
/* The XAUI PHY is identified by the slot */
|
/* The XAUI PHY is identified by the slot */
|
||||||
sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]);
|
sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]);
|
||||||
fdt_set_phy_handle(fdt, compat, addr, phy);
|
fdt_set_phy_handle(fdt, compat, addr, phy);
|
||||||
}
|
}
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
#endif /* #ifdef CONFIG_FMAN_ENET */
|
#endif /* #ifdef CONFIG_FMAN_ENET */
|
||||||
@ -169,6 +175,9 @@ int board_eth_init(struct bd_info *bis)
|
|||||||
fm_info_set_phy_address(i, riser_phy_addr[i]);
|
fm_info_set_phy_address(i, riser_phy_addr[i]);
|
||||||
break;
|
break;
|
||||||
case PHY_INTERFACE_MODE_RGMII:
|
case PHY_INTERFACE_MODE_RGMII:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_TXID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_RXID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_ID:
|
||||||
/* Only DTSEC4 and DTSEC5 can be routed to RGMII */
|
/* Only DTSEC4 and DTSEC5 can be routed to RGMII */
|
||||||
fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
|
fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
|
||||||
CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
|
CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
|
||||||
|
@ -89,6 +89,9 @@ int board_eth_init(struct bd_info *bis)
|
|||||||
interface = fm_info_get_enet_if(i);
|
interface = fm_info_get_enet_if(i);
|
||||||
switch (interface) {
|
switch (interface) {
|
||||||
case PHY_INTERFACE_MODE_RGMII:
|
case PHY_INTERFACE_MODE_RGMII:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_TXID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_RXID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_ID:
|
||||||
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
|
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
|
||||||
fm_info_set_mdio(i, dev);
|
fm_info_set_mdio(i, dev);
|
||||||
break;
|
break;
|
||||||
|
@ -77,6 +77,9 @@ int board_eth_init(struct bd_info *bis)
|
|||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
case PHY_INTERFACE_MODE_RGMII:
|
case PHY_INTERFACE_MODE_RGMII:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_TXID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_RXID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_ID:
|
||||||
if (FM1_DTSEC4 == i)
|
if (FM1_DTSEC4 == i)
|
||||||
phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;
|
phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;
|
||||||
if (FM1_DTSEC5 == i)
|
if (FM1_DTSEC5 == i)
|
||||||
|
@ -765,6 +765,9 @@ int board_eth_init(struct bd_info *bis)
|
|||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
case PHY_INTERFACE_MODE_RGMII:
|
case PHY_INTERFACE_MODE_RGMII:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_TXID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_RXID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_ID:
|
||||||
if (i == FM1_DTSEC3)
|
if (i == FM1_DTSEC3)
|
||||||
mdio_mux[i] = EMI1_RGMII1;
|
mdio_mux[i] = EMI1_RGMII1;
|
||||||
else if (i == FM1_DTSEC4 || FM1_DTSEC10)
|
else if (i == FM1_DTSEC4 || FM1_DTSEC10)
|
||||||
|
@ -76,6 +76,9 @@ int board_eth_init(struct bd_info *bis)
|
|||||||
interface = fm_info_get_enet_if(i);
|
interface = fm_info_get_enet_if(i);
|
||||||
switch (interface) {
|
switch (interface) {
|
||||||
case PHY_INTERFACE_MODE_RGMII:
|
case PHY_INTERFACE_MODE_RGMII:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_TXID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_RXID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_ID:
|
||||||
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
|
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
|
||||||
fm_info_set_mdio(i, dev);
|
fm_info_set_mdio(i, dev);
|
||||||
break;
|
break;
|
||||||
|
@ -56,6 +56,7 @@ CONFIG_SPI_FLASH_SST=y
|
|||||||
CONFIG_PHYLIB=y
|
CONFIG_PHYLIB=y
|
||||||
CONFIG_PHY_AQUANTIA=y
|
CONFIG_PHY_AQUANTIA=y
|
||||||
CONFIG_PHY_CORTINA=y
|
CONFIG_PHY_CORTINA=y
|
||||||
|
CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
|
||||||
CONFIG_PHY_REALTEK=y
|
CONFIG_PHY_REALTEK=y
|
||||||
CONFIG_PHY_VITESSE=y
|
CONFIG_PHY_VITESSE=y
|
||||||
CONFIG_DM_ETH=y
|
CONFIG_DM_ETH=y
|
||||||
@ -69,6 +70,7 @@ CONFIG_PCI=y
|
|||||||
CONFIG_DM_PCI=y
|
CONFIG_DM_PCI=y
|
||||||
CONFIG_DM_PCI_COMPAT=y
|
CONFIG_DM_PCI_COMPAT=y
|
||||||
CONFIG_PCIE_LAYERSCAPE_RC=y
|
CONFIG_PCIE_LAYERSCAPE_RC=y
|
||||||
|
CONFIG_PCIE_LAYERSCAPE_GEN4=y
|
||||||
CONFIG_DM_RTC=y
|
CONFIG_DM_RTC=y
|
||||||
CONFIG_RTC_PCF2127=y
|
CONFIG_RTC_PCF2127=y
|
||||||
CONFIG_DM_SCSI=y
|
CONFIG_DM_SCSI=y
|
||||||
|
@ -63,6 +63,7 @@ CONFIG_SPI_FLASH_SST=y
|
|||||||
CONFIG_PHYLIB=y
|
CONFIG_PHYLIB=y
|
||||||
CONFIG_PHY_AQUANTIA=y
|
CONFIG_PHY_AQUANTIA=y
|
||||||
CONFIG_PHY_CORTINA=y
|
CONFIG_PHY_CORTINA=y
|
||||||
|
CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
|
||||||
CONFIG_PHY_REALTEK=y
|
CONFIG_PHY_REALTEK=y
|
||||||
CONFIG_PHY_VITESSE=y
|
CONFIG_PHY_VITESSE=y
|
||||||
CONFIG_DM_ETH=y
|
CONFIG_DM_ETH=y
|
||||||
@ -76,6 +77,7 @@ CONFIG_PCI=y
|
|||||||
CONFIG_DM_PCI=y
|
CONFIG_DM_PCI=y
|
||||||
CONFIG_DM_PCI_COMPAT=y
|
CONFIG_DM_PCI_COMPAT=y
|
||||||
CONFIG_PCIE_LAYERSCAPE_RC=y
|
CONFIG_PCIE_LAYERSCAPE_RC=y
|
||||||
|
CONFIG_PCIE_LAYERSCAPE_GEN4=y
|
||||||
CONFIG_DM_RTC=y
|
CONFIG_DM_RTC=y
|
||||||
CONFIG_RTC_PCF2127=y
|
CONFIG_RTC_PCF2127=y
|
||||||
CONFIG_DM_SCSI=y
|
CONFIG_DM_SCSI=y
|
||||||
|
@ -52,6 +52,7 @@ CONFIG_PHYLIB=y
|
|||||||
CONFIG_PHY_AQUANTIA=y
|
CONFIG_PHY_AQUANTIA=y
|
||||||
CONFIG_PHY_ATHEROS=y
|
CONFIG_PHY_ATHEROS=y
|
||||||
CONFIG_PHY_CORTINA=y
|
CONFIG_PHY_CORTINA=y
|
||||||
|
CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
|
||||||
CONFIG_DM_ETH=y
|
CONFIG_DM_ETH=y
|
||||||
CONFIG_DM_MDIO=y
|
CONFIG_DM_MDIO=y
|
||||||
CONFIG_E1000=y
|
CONFIG_E1000=y
|
||||||
@ -61,6 +62,7 @@ CONFIG_PCI=y
|
|||||||
CONFIG_DM_PCI=y
|
CONFIG_DM_PCI=y
|
||||||
CONFIG_DM_PCI_COMPAT=y
|
CONFIG_DM_PCI_COMPAT=y
|
||||||
CONFIG_PCIE_LAYERSCAPE_RC=y
|
CONFIG_PCIE_LAYERSCAPE_RC=y
|
||||||
|
CONFIG_PCIE_LAYERSCAPE_GEN4=y
|
||||||
CONFIG_DM_RTC=y
|
CONFIG_DM_RTC=y
|
||||||
CONFIG_RTC_PCF2127=y
|
CONFIG_RTC_PCF2127=y
|
||||||
CONFIG_DM_SCSI=y
|
CONFIG_DM_SCSI=y
|
||||||
|
@ -61,6 +61,7 @@ CONFIG_PHYLIB=y
|
|||||||
CONFIG_PHY_AQUANTIA=y
|
CONFIG_PHY_AQUANTIA=y
|
||||||
CONFIG_PHY_ATHEROS=y
|
CONFIG_PHY_ATHEROS=y
|
||||||
CONFIG_PHY_CORTINA=y
|
CONFIG_PHY_CORTINA=y
|
||||||
|
CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
|
||||||
CONFIG_DM_ETH=y
|
CONFIG_DM_ETH=y
|
||||||
CONFIG_DM_MDIO=y
|
CONFIG_DM_MDIO=y
|
||||||
CONFIG_E1000=y
|
CONFIG_E1000=y
|
||||||
@ -70,6 +71,7 @@ CONFIG_PCI=y
|
|||||||
CONFIG_DM_PCI=y
|
CONFIG_DM_PCI=y
|
||||||
CONFIG_DM_PCI_COMPAT=y
|
CONFIG_DM_PCI_COMPAT=y
|
||||||
CONFIG_PCIE_LAYERSCAPE_RC=y
|
CONFIG_PCIE_LAYERSCAPE_RC=y
|
||||||
|
CONFIG_PCIE_LAYERSCAPE_GEN4=y
|
||||||
CONFIG_DM_RTC=y
|
CONFIG_DM_RTC=y
|
||||||
CONFIG_RTC_PCF2127=y
|
CONFIG_RTC_PCF2127=y
|
||||||
CONFIG_DM_SCSI=y
|
CONFIG_DM_SCSI=y
|
||||||
|
@ -61,6 +61,7 @@ CONFIG_PHYLIB=y
|
|||||||
CONFIG_PHY_AQUANTIA=y
|
CONFIG_PHY_AQUANTIA=y
|
||||||
CONFIG_PHY_ATHEROS=y
|
CONFIG_PHY_ATHEROS=y
|
||||||
CONFIG_PHY_CORTINA=y
|
CONFIG_PHY_CORTINA=y
|
||||||
|
CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
|
||||||
CONFIG_DM_ETH=y
|
CONFIG_DM_ETH=y
|
||||||
CONFIG_DM_MDIO=y
|
CONFIG_DM_MDIO=y
|
||||||
CONFIG_E1000=y
|
CONFIG_E1000=y
|
||||||
@ -70,6 +71,7 @@ CONFIG_PCI=y
|
|||||||
CONFIG_DM_PCI=y
|
CONFIG_DM_PCI=y
|
||||||
CONFIG_DM_PCI_COMPAT=y
|
CONFIG_DM_PCI_COMPAT=y
|
||||||
CONFIG_PCIE_LAYERSCAPE_RC=y
|
CONFIG_PCIE_LAYERSCAPE_RC=y
|
||||||
|
CONFIG_PCIE_LAYERSCAPE_GEN4=y
|
||||||
CONFIG_DM_RTC=y
|
CONFIG_DM_RTC=y
|
||||||
CONFIG_RTC_PCF2127=y
|
CONFIG_RTC_PCF2127=y
|
||||||
CONFIG_DM_SCSI=y
|
CONFIG_DM_SCSI=y
|
||||||
|
101
configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
Normal file
101
configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
Normal file
@ -0,0 +1,101 @@
|
|||||||
|
CONFIG_ARM=y
|
||||||
|
CONFIG_TARGET_LX2162AQDS=y
|
||||||
|
CONFIG_TFABOOT=y
|
||||||
|
CONFIG_SYS_TEXT_BASE=0x82000000
|
||||||
|
CONFIG_SYS_MALLOC_F_LEN=0x6000
|
||||||
|
CONFIG_NXP_ESBC=y
|
||||||
|
CONFIG_ENV_SIZE=0x2000
|
||||||
|
CONFIG_ENV_SECT_SIZE=0x20000
|
||||||
|
CONFIG_ENV_OFFSET=0x500000
|
||||||
|
CONFIG_FSPI_AHB_EN_4BYTE=y
|
||||||
|
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||||
|
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||||
|
CONFIG_AHCI=y
|
||||||
|
CONFIG_NR_DRAM_BANKS=3
|
||||||
|
CONFIG_FIT_VERBOSE=y
|
||||||
|
CONFIG_OF_BOARD_SETUP=y
|
||||||
|
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||||
|
CONFIG_USE_BOOTARGS=y
|
||||||
|
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
|
||||||
|
# CONFIG_USE_BOOTCOMMAND is not set
|
||||||
|
CONFIG_BOARD_EARLY_INIT_R=y
|
||||||
|
CONFIG_MISC_INIT_R=y
|
||||||
|
CONFIG_BOARD_EARLY_INIT_R=y
|
||||||
|
CONFIG_CMD_GREPENV=y
|
||||||
|
CONFIG_CMD_EEPROM=y
|
||||||
|
CONFIG_CMD_DM=y
|
||||||
|
CONFIG_CMD_GPT=y
|
||||||
|
CONFIG_CMD_GPIO=y
|
||||||
|
CONFIG_CMD_I2C=y
|
||||||
|
CONFIG_CMD_MMC=y
|
||||||
|
CONFIG_CMD_PCI=y
|
||||||
|
CONFIG_CMD_SF=y
|
||||||
|
CONFIG_CMD_USB=y
|
||||||
|
CONFIG_CMD_WDT=y
|
||||||
|
CONFIG_CMD_CACHE=y
|
||||||
|
CONFIG_MP=y
|
||||||
|
CONFIG_OF_CONTROL=y
|
||||||
|
CONFIG_OF_BOARD_FIXUP=y
|
||||||
|
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds"
|
||||||
|
CONFIG_OF_LIST="fsl-lx2162a-qds-17-x fsl-lx2162a-qds-18-x fsl-lx2162a-qds-20-x"
|
||||||
|
CONFIG_MULTI_DTB_FIT=y
|
||||||
|
CONFIG_ENV_OVERWRITE=y
|
||||||
|
CONFIG_ENV_IS_IN_MMC=y
|
||||||
|
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||||
|
CONFIG_ENV_ADDR=0x20500000
|
||||||
|
CONFIG_NET_RANDOM_ETHADDR=y
|
||||||
|
CONFIG_DM=y
|
||||||
|
CONFIG_SATA_CEVA=y
|
||||||
|
CONFIG_DM_MMC=y
|
||||||
|
CONFIG_MMC_HS400_SUPPORT=y
|
||||||
|
CONFIG_FSL_ESDHC=y
|
||||||
|
CONFIG_MTD=y
|
||||||
|
CONFIG_DM_SPI_FLASH=y
|
||||||
|
CONFIG_SPI_FLASH_EON=y
|
||||||
|
CONFIG_SPI_FLASH_SST=y
|
||||||
|
CONFIG_SPI_FLASH=y
|
||||||
|
CONFIG_SPI_FLASH_STMICRO=y
|
||||||
|
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||||
|
CONFIG_PHYLIB=y
|
||||||
|
CONFIG_PHY_AQUANTIA=y
|
||||||
|
CONFIG_PHY_CORTINA=y
|
||||||
|
CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
|
||||||
|
CONFIG_PHY_REALTEK=y
|
||||||
|
CONFIG_PHY_VITESSE=y
|
||||||
|
CONFIG_DM_ETH=y
|
||||||
|
CONFIG_DM_MDIO=y
|
||||||
|
CONFIG_DM_MDIO_MUX=y
|
||||||
|
CONFIG_E1000=y
|
||||||
|
CONFIG_MDIO_MUX_I2CREG=y
|
||||||
|
CONFIG_FSL_LS_MDIO=y
|
||||||
|
CONFIG_PCI=y
|
||||||
|
CONFIG_DM_PCI=y
|
||||||
|
CONFIG_DM_PCI_COMPAT=y
|
||||||
|
CONFIG_PCIE_LAYERSCAPE_RC=y
|
||||||
|
CONFIG_DM_SCSI=y
|
||||||
|
CONFIG_DM_SERIAL=y
|
||||||
|
CONFIG_SPI=y
|
||||||
|
CONFIG_DM_SPI=y
|
||||||
|
CONFIG_FSL_DSPI=y
|
||||||
|
CONFIG_NXP_FSPI=y
|
||||||
|
CONFIG_USB=y
|
||||||
|
CONFIG_DM_USB=y
|
||||||
|
CONFIG_USB_XHCI_HCD=y
|
||||||
|
CONFIG_USB_XHCI_DWC3=y
|
||||||
|
CONFIG_WDT=y
|
||||||
|
CONFIG_WDT_SBSA=y
|
||||||
|
CONFIG_RSA=y
|
||||||
|
CONFIG_SPL_RSA=y
|
||||||
|
CONFIG_RSA_SOFTWARE_EXP=y
|
||||||
|
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||||
|
CONFIG_GIC_V3_ITS=y
|
||||||
|
CONFIG_DM_I2C=y
|
||||||
|
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
|
||||||
|
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
|
||||||
|
CONFIG_DM_RTC=y
|
||||||
|
CONFIG_DM_GPIO=y
|
||||||
|
CONFIG_CMD_DATE=y
|
||||||
|
CONFIG_RTC_PCF2127=y
|
||||||
|
CONFIG_I2C_MUX=y
|
||||||
|
CONFIG_I2C_MUX_PCA954x=y
|
||||||
|
CONFIG_MPC8XXX_GPIO=y
|
104
configs/lx2162aqds_tfa_defconfig
Normal file
104
configs/lx2162aqds_tfa_defconfig
Normal file
@ -0,0 +1,104 @@
|
|||||||
|
CONFIG_ARM=y
|
||||||
|
CONFIG_TARGET_LX2162AQDS=y
|
||||||
|
CONFIG_SYS_TEXT_BASE=0x82000000
|
||||||
|
CONFIG_SYS_MALLOC_F_LEN=0x6000
|
||||||
|
CONFIG_ENV_SIZE=0x2000
|
||||||
|
CONFIG_ENV_SECT_SIZE=0x20000
|
||||||
|
CONFIG_ENV_OFFSET=0x500000
|
||||||
|
CONFIG_FSPI_AHB_EN_4BYTE=y
|
||||||
|
CONFIG_TFABOOT=y
|
||||||
|
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||||
|
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||||
|
CONFIG_AHCI=y
|
||||||
|
CONFIG_NR_DRAM_BANKS=3
|
||||||
|
CONFIG_FIT_VERBOSE=y
|
||||||
|
CONFIG_OF_BOARD_SETUP=y
|
||||||
|
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||||
|
CONFIG_BOOTDELAY=10
|
||||||
|
CONFIG_USE_BOOTARGS=y
|
||||||
|
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
|
||||||
|
# CONFIG_USE_BOOTCOMMAND is not set
|
||||||
|
CONFIG_BOARD_EARLY_INIT_R=y
|
||||||
|
CONFIG_MISC_INIT_R=y
|
||||||
|
CONFIG_BOARD_EARLY_INIT_R=y
|
||||||
|
CONFIG_CMD_GREPENV=y
|
||||||
|
CONFIG_CMD_EEPROM=y
|
||||||
|
CONFIG_CMD_DM=y
|
||||||
|
CONFIG_CMD_GPT=y
|
||||||
|
CONFIG_CMD_GPIO=y
|
||||||
|
CONFIG_CMD_I2C=y
|
||||||
|
CONFIG_CMD_MMC=y
|
||||||
|
CONFIG_CMD_PCI=y
|
||||||
|
CONFIG_CMD_SF=y
|
||||||
|
CONFIG_CMD_USB=y
|
||||||
|
CONFIG_CMD_WDT=y
|
||||||
|
CONFIG_CMD_CACHE=y
|
||||||
|
CONFIG_MP=y
|
||||||
|
CONFIG_OF_CONTROL=y
|
||||||
|
CONFIG_OF_BOARD_FIXUP=y
|
||||||
|
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds"
|
||||||
|
CONFIG_OF_LIST="fsl-lx2162a-qds-17-x fsl-lx2162a-qds-18-x fsl-lx2162a-qds-20-x"
|
||||||
|
CONFIG_MULTI_DTB_FIT=y
|
||||||
|
CONFIG_ENV_OVERWRITE=y
|
||||||
|
CONFIG_ENV_IS_IN_MMC=y
|
||||||
|
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||||
|
CONFIG_ENV_ADDR=0x20500000
|
||||||
|
CONFIG_NET_RANDOM_ETHADDR=y
|
||||||
|
CONFIG_DM=y
|
||||||
|
CONFIG_SATA_CEVA=y
|
||||||
|
CONFIG_FSL_CAAM=y
|
||||||
|
CONFIG_DM_MMC=y
|
||||||
|
CONFIG_MMC_HS400_SUPPORT=y
|
||||||
|
CONFIG_FSL_ESDHC=y
|
||||||
|
CONFIG_MTD=y
|
||||||
|
CONFIG_DM_SPI_FLASH=y
|
||||||
|
CONFIG_SPI_FLASH_EON=y
|
||||||
|
CONFIG_SPI_FLASH_SST=y
|
||||||
|
CONFIG_SPI_FLASH=y
|
||||||
|
CONFIG_SPI_FLASH_STMICRO=y
|
||||||
|
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||||
|
CONFIG_PHYLIB=y
|
||||||
|
CONFIG_PHY_AQUANTIA=y
|
||||||
|
CONFIG_PHY_CORTINA=y
|
||||||
|
CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
|
||||||
|
CONFIG_PHY_REALTEK=y
|
||||||
|
CONFIG_PHY_VITESSE=y
|
||||||
|
CONFIG_DM_ETH=y
|
||||||
|
CONFIG_DM_MDIO=y
|
||||||
|
CONFIG_DM_MDIO_MUX=y
|
||||||
|
CONFIG_E1000=y
|
||||||
|
CONFIG_MDIO_MUX_I2CREG=y
|
||||||
|
CONFIG_FSL_LS_MDIO=y
|
||||||
|
CONFIG_PCI=y
|
||||||
|
CONFIG_DM_PCI=y
|
||||||
|
CONFIG_DM_PCI_COMPAT=y
|
||||||
|
CONFIG_PCIE_LAYERSCAPE_RC=y
|
||||||
|
CONFIG_DM_SCSI=y
|
||||||
|
CONFIG_DM_SERIAL=y
|
||||||
|
CONFIG_SPI=y
|
||||||
|
CONFIG_DM_SPI=y
|
||||||
|
CONFIG_FSL_DSPI=y
|
||||||
|
CONFIG_NXP_FSPI=y
|
||||||
|
CONFIG_USB=y
|
||||||
|
CONFIG_DM_USB=y
|
||||||
|
CONFIG_USB_XHCI_HCD=y
|
||||||
|
CONFIG_USB_XHCI_DWC3=y
|
||||||
|
CONFIG_WDT=y
|
||||||
|
CONFIG_WDT_SBSA=y
|
||||||
|
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||||
|
CONFIG_GIC_V3_ITS=y
|
||||||
|
CONFIG_DM_I2C=y
|
||||||
|
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
|
||||||
|
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
|
||||||
|
CONFIG_DM_RTC=y
|
||||||
|
CONFIG_DM_GPIO=y
|
||||||
|
CONFIG_CMD_DATE=y
|
||||||
|
CONFIG_RTC_PCF2127=y
|
||||||
|
CONFIG_I2C_MUX=y
|
||||||
|
CONFIG_I2C_MUX_PCA954x=y
|
||||||
|
CONFIG_MPC8XXX_GPIO=y
|
||||||
|
CONFIG_TEE=y
|
||||||
|
CONFIG_OPTEE=y
|
||||||
|
CONFIG_OPTEE_TA_AVB=y
|
||||||
|
CONFIG_SUPPORT_EMMC_RPMB=y
|
||||||
|
CONFIG_CMD_OPTEE_RPMB=y
|
106
configs/lx2162aqds_tfa_verified_boot_defconfig
Normal file
106
configs/lx2162aqds_tfa_verified_boot_defconfig
Normal file
@ -0,0 +1,106 @@
|
|||||||
|
CONFIG_ARM=y
|
||||||
|
CONFIG_TARGET_LX2162AQDS=y
|
||||||
|
CONFIG_SYS_TEXT_BASE=0x82000000
|
||||||
|
CONFIG_SYS_MALLOC_F_LEN=0x6000
|
||||||
|
CONFIG_ENV_SIZE=0x2000
|
||||||
|
CONFIG_ENV_SECT_SIZE=0x20000
|
||||||
|
CONFIG_ENV_OFFSET=0x500000
|
||||||
|
CONFIG_FSPI_AHB_EN_4BYTE=y
|
||||||
|
CONFIG_TFABOOT=y
|
||||||
|
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||||
|
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||||
|
CONFIG_AHCI=y
|
||||||
|
CONFIG_NR_DRAM_BANKS=3
|
||||||
|
CONFIG_FIT_VERBOSE=y
|
||||||
|
CONFIG_FIT_SIGNATURE=y
|
||||||
|
CONFIG_RSA=y
|
||||||
|
CONFIG_OF_BOARD_SETUP=y
|
||||||
|
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||||
|
CONFIG_BOOTDELAY=10
|
||||||
|
CONFIG_USE_BOOTARGS=y
|
||||||
|
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
|
||||||
|
# CONFIG_USE_BOOTCOMMAND is not set
|
||||||
|
CONFIG_BOARD_EARLY_INIT_R=y
|
||||||
|
CONFIG_MISC_INIT_R=y
|
||||||
|
CONFIG_BOARD_EARLY_INIT_R=y
|
||||||
|
CONFIG_CMD_GREPENV=y
|
||||||
|
CONFIG_CMD_EEPROM=y
|
||||||
|
CONFIG_CMD_DM=y
|
||||||
|
CONFIG_CMD_GPT=y
|
||||||
|
CONFIG_CMD_GPIO=y
|
||||||
|
CONFIG_CMD_I2C=y
|
||||||
|
CONFIG_CMD_MMC=y
|
||||||
|
CONFIG_CMD_PCI=y
|
||||||
|
CONFIG_CMD_SF=y
|
||||||
|
CONFIG_CMD_USB=y
|
||||||
|
CONFIG_CMD_WDT=y
|
||||||
|
CONFIG_CMD_CACHE=y
|
||||||
|
CONFIG_MP=y
|
||||||
|
CONFIG_OF_CONTROL=y
|
||||||
|
CONFIG_OF_BOARD_FIXUP=y
|
||||||
|
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds"
|
||||||
|
CONFIG_OF_LIST="fsl-lx2162a-qds-17-x fsl-lx2162a-qds-18-x fsl-lx2162a-qds-20-x"
|
||||||
|
CONFIG_MULTI_DTB_FIT=y
|
||||||
|
CONFIG_ENV_OVERWRITE=y
|
||||||
|
CONFIG_ENV_IS_IN_MMC=y
|
||||||
|
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||||
|
CONFIG_ENV_ADDR=0x20500000
|
||||||
|
CONFIG_NET_RANDOM_ETHADDR=y
|
||||||
|
CONFIG_DM=y
|
||||||
|
CONFIG_SATA_CEVA=y
|
||||||
|
CONFIG_FSL_CAAM=y
|
||||||
|
CONFIG_DM_MMC=y
|
||||||
|
CONFIG_MMC_HS400_SUPPORT=y
|
||||||
|
CONFIG_FSL_ESDHC=y
|
||||||
|
CONFIG_MTD=y
|
||||||
|
CONFIG_DM_SPI_FLASH=y
|
||||||
|
CONFIG_SPI_FLASH_EON=y
|
||||||
|
CONFIG_SPI_FLASH_SST=y
|
||||||
|
CONFIG_SPI_FLASH=y
|
||||||
|
CONFIG_SPI_FLASH_STMICRO=y
|
||||||
|
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||||
|
CONFIG_PHYLIB=y
|
||||||
|
CONFIG_PHY_AQUANTIA=y
|
||||||
|
CONFIG_PHY_CORTINA=y
|
||||||
|
CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
|
||||||
|
CONFIG_PHY_REALTEK=y
|
||||||
|
CONFIG_PHY_VITESSE=y
|
||||||
|
CONFIG_DM_ETH=y
|
||||||
|
CONFIG_DM_MDIO=y
|
||||||
|
CONFIG_DM_MDIO_MUX=y
|
||||||
|
CONFIG_E1000=y
|
||||||
|
CONFIG_MDIO_MUX_I2CREG=y
|
||||||
|
CONFIG_FSL_LS_MDIO=y
|
||||||
|
CONFIG_PCI=y
|
||||||
|
CONFIG_DM_PCI=y
|
||||||
|
CONFIG_DM_PCI_COMPAT=y
|
||||||
|
CONFIG_PCIE_LAYERSCAPE_RC=y
|
||||||
|
CONFIG_DM_SCSI=y
|
||||||
|
CONFIG_DM_SERIAL=y
|
||||||
|
CONFIG_SPI=y
|
||||||
|
CONFIG_DM_SPI=y
|
||||||
|
CONFIG_FSL_DSPI=y
|
||||||
|
CONFIG_NXP_FSPI=y
|
||||||
|
CONFIG_USB=y
|
||||||
|
CONFIG_DM_USB=y
|
||||||
|
CONFIG_USB_XHCI_HCD=y
|
||||||
|
CONFIG_USB_XHCI_DWC3=y
|
||||||
|
CONFIG_WDT=y
|
||||||
|
CONFIG_WDT_SBSA=y
|
||||||
|
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||||
|
CONFIG_GIC_V3_ITS=y
|
||||||
|
CONFIG_DM_I2C=y
|
||||||
|
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
|
||||||
|
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
|
||||||
|
CONFIG_DM_RTC=y
|
||||||
|
CONFIG_DM_GPIO=y
|
||||||
|
CONFIG_CMD_DATE=y
|
||||||
|
CONFIG_RTC_PCF2127=y
|
||||||
|
CONFIG_I2C_MUX=y
|
||||||
|
CONFIG_I2C_MUX_PCA954x=y
|
||||||
|
CONFIG_TEE=y
|
||||||
|
CONFIG_OPTEE=y
|
||||||
|
CONFIG_CMD_OPTEE_RPMB=y
|
||||||
|
CONFIG_OPTEE_TA_AVB=y
|
||||||
|
CONFIG_SUPPORT_EMMC_RPMB=y
|
||||||
|
CONFIG_MPC8XXX_GPIO=y
|
@ -47,6 +47,7 @@ config SYS_NUM_DDR_CTLRS
|
|||||||
ARCH_P5020 || \
|
ARCH_P5020 || \
|
||||||
ARCH_P5040 || \
|
ARCH_P5040 || \
|
||||||
ARCH_LX2160A || \
|
ARCH_LX2160A || \
|
||||||
|
ARCH_LX2162A || \
|
||||||
ARCH_T4160
|
ARCH_T4160
|
||||||
default 1
|
default 1
|
||||||
|
|
||||||
|
@ -4,7 +4,7 @@
|
|||||||
|
|
||||||
menuconfig FSL_MC_ENET
|
menuconfig FSL_MC_ENET
|
||||||
bool "NXP Management Complex"
|
bool "NXP Management Complex"
|
||||||
depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
|
depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A || ARCH_LX2162A
|
||||||
default y
|
default y
|
||||||
select RESV_RAM
|
select RESV_RAM
|
||||||
help
|
help
|
||||||
@ -17,7 +17,7 @@ if FSL_MC_ENET
|
|||||||
config SYS_MC_RSV_MEM_ALIGN
|
config SYS_MC_RSV_MEM_ALIGN
|
||||||
hex "Management Complex reserved memory alignment"
|
hex "Management Complex reserved memory alignment"
|
||||||
depends on RESV_RAM
|
depends on RESV_RAM
|
||||||
default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
|
default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A || ARCH_LX2162A
|
||||||
help
|
help
|
||||||
Reserved memory needs to be aligned for MC to use. Default value
|
Reserved memory needs to be aligned for MC to use. Default value
|
||||||
is 512MB.
|
is 512MB.
|
||||||
|
@ -7,3 +7,4 @@ obj-y += ldpaa_eth.o
|
|||||||
obj-$(CONFIG_ARCH_LS2080A) += ls2080a.o
|
obj-$(CONFIG_ARCH_LS2080A) += ls2080a.o
|
||||||
obj-$(CONFIG_ARCH_LS1088A) += ls1088a.o
|
obj-$(CONFIG_ARCH_LS1088A) += ls1088a.o
|
||||||
obj-$(CONFIG_ARCH_LX2160A) += lx2160a.o
|
obj-$(CONFIG_ARCH_LX2160A) += lx2160a.o
|
||||||
|
obj-$(CONFIG_ARCH_LX2162A) += lx2160a.o
|
||||||
|
@ -10,6 +10,8 @@
|
|||||||
* files.
|
* files.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#include <dm.h>
|
||||||
|
#include <dm/device-internal.h>
|
||||||
#include <image.h>
|
#include <image.h>
|
||||||
#include <log.h>
|
#include <log.h>
|
||||||
#include <malloc.h>
|
#include <malloc.h>
|
||||||
@ -24,6 +26,9 @@
|
|||||||
#define PFE_FIRMWARE_FIT_CNF_NAME "config@1"
|
#define PFE_FIRMWARE_FIT_CNF_NAME "config@1"
|
||||||
|
|
||||||
static const void *pfe_fit_addr;
|
static const void *pfe_fit_addr;
|
||||||
|
#ifdef CONFIG_CHAIN_OF_TRUST
|
||||||
|
static const void *pfe_esbc_hdr_addr;
|
||||||
|
#endif
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* PFE elf firmware loader.
|
* PFE elf firmware loader.
|
||||||
@ -169,7 +174,7 @@ int pfe_spi_flash_init(void)
|
|||||||
struct spi_flash *pfe_flash;
|
struct spi_flash *pfe_flash;
|
||||||
struct udevice *new;
|
struct udevice *new;
|
||||||
int ret = 0;
|
int ret = 0;
|
||||||
void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
|
void *addr = malloc(CONFIG_SYS_LS_PFE_FW_LENGTH);
|
||||||
|
|
||||||
if (!addr)
|
if (!addr)
|
||||||
return -ENOMEM;
|
return -ENOMEM;
|
||||||
@ -179,21 +184,56 @@ int pfe_spi_flash_init(void)
|
|||||||
CONFIG_ENV_SPI_MAX_HZ,
|
CONFIG_ENV_SPI_MAX_HZ,
|
||||||
CONFIG_ENV_SPI_MODE,
|
CONFIG_ENV_SPI_MODE,
|
||||||
&new);
|
&new);
|
||||||
|
if (ret) {
|
||||||
|
printf("SF: failed to probe spi\n");
|
||||||
|
free(addr);
|
||||||
|
device_remove(new, DM_REMOVE_NORMAL);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
pfe_flash = dev_get_uclass_priv(new);
|
pfe_flash = dev_get_uclass_priv(new);
|
||||||
if (!pfe_flash) {
|
if (!pfe_flash) {
|
||||||
printf("SF: probe for pfe failed\n");
|
printf("SF: probe for pfe failed\n");
|
||||||
free(addr);
|
free(addr);
|
||||||
|
device_remove(new, DM_REMOVE_NORMAL);
|
||||||
return -ENODEV;
|
return -ENODEV;
|
||||||
}
|
}
|
||||||
|
|
||||||
ret = spi_flash_read(pfe_flash,
|
ret = spi_flash_read(pfe_flash,
|
||||||
CONFIG_SYS_LS_PFE_FW_ADDR,
|
CONFIG_SYS_LS_PFE_FW_ADDR,
|
||||||
CONFIG_SYS_QE_FMAN_FW_LENGTH,
|
CONFIG_SYS_LS_PFE_FW_LENGTH,
|
||||||
addr);
|
addr);
|
||||||
if (ret)
|
if (ret) {
|
||||||
printf("SF: read for pfe failed\n");
|
printf("SF: read for pfe failed\n");
|
||||||
|
free(addr);
|
||||||
|
spi_flash_free(pfe_flash);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef CONFIG_CHAIN_OF_TRUST
|
||||||
|
void *hdr_addr = malloc(CONFIG_SYS_LS_PFE_ESBC_LENGTH);
|
||||||
|
|
||||||
|
if (!hdr_addr) {
|
||||||
|
free(addr);
|
||||||
|
spi_flash_free(pfe_flash);
|
||||||
|
return -ENOMEM;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = spi_flash_read(pfe_flash,
|
||||||
|
CONFIG_SYS_LS_PFE_ESBC_ADDR,
|
||||||
|
CONFIG_SYS_LS_PFE_ESBC_LENGTH,
|
||||||
|
hdr_addr);
|
||||||
|
if (ret) {
|
||||||
|
printf("SF: failed to read pfe esbc header\n");
|
||||||
|
free(addr);
|
||||||
|
free(hdr_addr);
|
||||||
|
spi_flash_free(pfe_flash);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
pfe_esbc_hdr_addr = hdr_addr;
|
||||||
|
#endif
|
||||||
pfe_fit_addr = addr;
|
pfe_fit_addr = addr;
|
||||||
spi_flash_free(pfe_flash);
|
spi_flash_free(pfe_flash);
|
||||||
|
|
||||||
@ -233,7 +273,7 @@ int pfe_firmware_init(void)
|
|||||||
goto err;
|
goto err;
|
||||||
|
|
||||||
#ifdef CONFIG_CHAIN_OF_TRUST
|
#ifdef CONFIG_CHAIN_OF_TRUST
|
||||||
pfe_esbc_hdr = CONFIG_SYS_LS_PFE_ESBC_ADDR;
|
pfe_esbc_hdr = (uintptr_t)pfe_esbc_hdr_addr;
|
||||||
pfe_img_addr = (uintptr_t)pfe_fit_addr;
|
pfe_img_addr = (uintptr_t)pfe_fit_addr;
|
||||||
if (fsl_check_boot_mode_secure() != 0) {
|
if (fsl_check_boot_mode_secure() != 0) {
|
||||||
/*
|
/*
|
||||||
|
@ -100,6 +100,15 @@ config PHY_BROADCOM
|
|||||||
config PHY_CORTINA
|
config PHY_CORTINA
|
||||||
bool "Cortina Ethernet PHYs support"
|
bool "Cortina Ethernet PHYs support"
|
||||||
|
|
||||||
|
config SYS_CORTINA_NO_FW_UPLOAD
|
||||||
|
bool "Cortina firmware loading support"
|
||||||
|
default n
|
||||||
|
depends on PHY_CORTINA
|
||||||
|
help
|
||||||
|
Cortina phy has provision to store phy firmware in attached dedicated
|
||||||
|
EEPROM. And boards designed with such EEPROM does not require firmware
|
||||||
|
upload.
|
||||||
|
|
||||||
choice
|
choice
|
||||||
prompt "Location of the Cortina firmware"
|
prompt "Location of the Cortina firmware"
|
||||||
default SYS_CORTINA_FW_IN_NOR
|
default SYS_CORTINA_FW_IN_NOR
|
||||||
|
@ -3,7 +3,7 @@
|
|||||||
* Cortina CS4315/CS4340 10G PHY drivers
|
* Cortina CS4315/CS4340 10G PHY drivers
|
||||||
*
|
*
|
||||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||||
* Copyright 2018 NXP
|
* Copyright 2018, 2020 NXP
|
||||||
*
|
*
|
||||||
*/
|
*/
|
||||||
|
|
||||||
@ -29,7 +29,7 @@
|
|||||||
#error The Cortina PHY needs 10G support
|
#error The Cortina PHY needs 10G support
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifndef CORTINA_NO_FW_UPLOAD
|
#ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD
|
||||||
struct cortina_reg_config cortina_reg_cfg[] = {
|
struct cortina_reg_config cortina_reg_cfg[] = {
|
||||||
/* CS4315_enable_sr_mode */
|
/* CS4315_enable_sr_mode */
|
||||||
{VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
|
{VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
|
||||||
@ -227,7 +227,7 @@ void cs4340_upload_firmware(struct phy_device *phydev)
|
|||||||
|
|
||||||
int cs4340_phy_init(struct phy_device *phydev)
|
int cs4340_phy_init(struct phy_device *phydev)
|
||||||
{
|
{
|
||||||
#ifndef CORTINA_NO_FW_UPLOAD
|
#ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD
|
||||||
int timeout = 100; /* 100ms */
|
int timeout = 100; /* 100ms */
|
||||||
#endif
|
#endif
|
||||||
int reg_value;
|
int reg_value;
|
||||||
@ -238,7 +238,7 @@ int cs4340_phy_init(struct phy_device *phydev)
|
|||||||
* Boards designed with EEPROM attached to Cortina
|
* Boards designed with EEPROM attached to Cortina
|
||||||
* does not require FW upload.
|
* does not require FW upload.
|
||||||
*/
|
*/
|
||||||
#ifndef CORTINA_NO_FW_UPLOAD
|
#ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD
|
||||||
/* step1: BIST test */
|
/* step1: BIST test */
|
||||||
phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL, 0x0004);
|
phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL, 0x0004);
|
||||||
phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000);
|
phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000);
|
||||||
|
@ -219,7 +219,7 @@ config FSL_PCIE_COMPAT
|
|||||||
default "fsl,ls1046a-pcie" if ARCH_LS1046A
|
default "fsl,ls1046a-pcie" if ARCH_LS1046A
|
||||||
default "fsl,ls2080a-pcie" if ARCH_LS2080A
|
default "fsl,ls2080a-pcie" if ARCH_LS2080A
|
||||||
default "fsl,ls1088a-pcie" if ARCH_LS1088A
|
default "fsl,ls1088a-pcie" if ARCH_LS1088A
|
||||||
default "fsl,lx2160a-pcie" if ARCH_LX2160A
|
default "fsl,lx2160a-pcie" if ARCH_LX2160A || ARCH_LX2162A
|
||||||
default "fsl,ls1021a-pcie" if ARCH_LS1021A
|
default "fsl,ls1021a-pcie" if ARCH_LS1021A
|
||||||
help
|
help
|
||||||
This compatible is used to find pci controller node in Kernel DT
|
This compatible is used to find pci controller node in Kernel DT
|
||||||
@ -228,7 +228,7 @@ config FSL_PCIE_COMPAT
|
|||||||
config FSL_PCIE_EP_COMPAT
|
config FSL_PCIE_EP_COMPAT
|
||||||
string "PCIe EP compatible of Kernel DT"
|
string "PCIe EP compatible of Kernel DT"
|
||||||
depends on PCIE_LAYERSCAPE_RC || PCIE_LAYERSCAPE_GEN4
|
depends on PCIE_LAYERSCAPE_RC || PCIE_LAYERSCAPE_GEN4
|
||||||
default "fsl,lx2160a-pcie-ep" if ARCH_LX2160A
|
default "fsl,lx2160a-pcie-ep" if ARCH_LX2160A || ARCH_LX2162A
|
||||||
default "fsl,ls-pcie-ep"
|
default "fsl,ls-pcie-ep"
|
||||||
help
|
help
|
||||||
This compatible is used to find pci controller ep node in Kernel DT
|
This compatible is used to find pci controller ep node in Kernel DT
|
||||||
|
@ -5,6 +5,7 @@
|
|||||||
*/
|
*/
|
||||||
|
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
|
#include <asm/arch/fsl_serdes.h>
|
||||||
#include <dm.h>
|
#include <dm.h>
|
||||||
#include <dm/devres.h>
|
#include <dm/devres.h>
|
||||||
#include <errno.h>
|
#include <errno.h>
|
||||||
@ -272,7 +273,9 @@ static int ls_pcie_ep_probe(struct udevice *dev)
|
|||||||
|
|
||||||
svr = SVR_SOC_VER(get_svr());
|
svr = SVR_SOC_VER(get_svr());
|
||||||
|
|
||||||
if (svr == SVR_LX2160A)
|
if (svr == SVR_LX2160A || svr == SVR_LX2162A ||
|
||||||
|
svr == SVR_LX2120A || svr == SVR_LX2080A ||
|
||||||
|
svr == SVR_LX2122A || svr == SVR_LX2082A)
|
||||||
pcie_ep->pf1_offset = LX2160_PCIE_PF1_OFFSET;
|
pcie_ep->pf1_offset = LX2160_PCIE_PF1_OFFSET;
|
||||||
else
|
else
|
||||||
pcie_ep->pf1_offset = LS_PCIE_PF1_OFFSET;
|
pcie_ep->pf1_offset = LS_PCIE_PF1_OFFSET;
|
||||||
@ -294,7 +297,8 @@ static int ls_pcie_ep_probe(struct udevice *dev)
|
|||||||
pcie_ep->num_ob_wins = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
|
pcie_ep->num_ob_wins = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
|
||||||
"num-ob-windows", 8);
|
"num-ob-windows", 8);
|
||||||
|
|
||||||
printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
|
printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
|
||||||
|
"Endpoint");
|
||||||
ls_pcie_setup_ep(pcie_ep);
|
ls_pcie_setup_ep(pcie_ep);
|
||||||
|
|
||||||
if (!ls_pcie_link_up(pcie)) {
|
if (!ls_pcie_link_up(pcie)) {
|
||||||
|
@ -99,6 +99,8 @@ int lx2_board_fix_fdt(void *fdt)
|
|||||||
if (!prop) {
|
if (!prop) {
|
||||||
printf("%s: Failed to fixup PCIe EP node @0x%x\n",
|
printf("%s: Failed to fixup PCIe EP node @0x%x\n",
|
||||||
__func__, off);
|
__func__, off);
|
||||||
|
off = fdt_node_offset_by_compatible(fdt, off,
|
||||||
|
"fsl,lx2160a-pcie-ep");
|
||||||
continue;
|
continue;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -121,13 +123,16 @@ int pcie_board_fix_fdt(void *fdt)
|
|||||||
|
|
||||||
svr = SVR_SOC_VER(get_svr());
|
svr = SVR_SOC_VER(get_svr());
|
||||||
|
|
||||||
if (svr == SVR_LX2160A && IS_SVR_REV(get_svr(), 2, 0))
|
if ((svr == SVR_LX2160A || svr == SVR_LX2162A ||
|
||||||
|
svr == SVR_LX2120A || svr == SVR_LX2080A ||
|
||||||
|
svr == SVR_LX2122A || svr == SVR_LX2082A) &&
|
||||||
|
IS_SVR_REV(get_svr(), 2, 0))
|
||||||
return lx2_board_fix_fdt(fdt);
|
return lx2_board_fix_fdt(fdt);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_LX2160A
|
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
|
||||||
/* returns the next available streamid for pcie, -errno if failed */
|
/* returns the next available streamid for pcie, -errno if failed */
|
||||||
int pcie_next_streamid(int currentid, int idx)
|
int pcie_next_streamid(int currentid, int idx)
|
||||||
{
|
{
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||||
/*
|
/*
|
||||||
* Copyright 2018-2019 NXP
|
* Copyright 2018-2020 NXP
|
||||||
*
|
*
|
||||||
* PCIe Gen4 driver for NXP Layerscape SoCs
|
* PCIe Gen4 driver for NXP Layerscape SoCs
|
||||||
* Author: Hou Zhiqiang <Minder.Hou@gmail.com>
|
* Author: Hou Zhiqiang <Minder.Hou@gmail.com>
|
||||||
@ -455,6 +455,7 @@ static int ls_pcie_g4_probe(struct udevice *dev)
|
|||||||
u32 link_ctrl_sta;
|
u32 link_ctrl_sta;
|
||||||
u32 val;
|
u32 val;
|
||||||
int ret;
|
int ret;
|
||||||
|
fdt_size_t cfg_size;
|
||||||
|
|
||||||
pcie->bus = dev;
|
pcie->bus = dev;
|
||||||
|
|
||||||
@ -472,7 +473,8 @@ static int ls_pcie_g4_probe(struct udevice *dev)
|
|||||||
|
|
||||||
pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
|
pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
|
||||||
if (!pcie->enabled) {
|
if (!pcie->enabled) {
|
||||||
printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
|
printf("PCIe%d: %s disabled\n", PCIE_SRDS_PRTCL(pcie->idx),
|
||||||
|
dev->name);
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -487,6 +489,13 @@ static int ls_pcie_g4_probe(struct udevice *dev)
|
|||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
cfg_size = fdt_resource_size(&pcie->cfg_res);
|
||||||
|
if (cfg_size < SZ_4K) {
|
||||||
|
printf("PCIe%d: %s Invalid size(0x%llx) for resource \"config\",expected minimum 0x%x\n",
|
||||||
|
PCIE_SRDS_PRTCL(pcie->idx), dev->name, cfg_size, SZ_4K);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
pcie->cfg = map_physmem(pcie->cfg_res.start,
|
pcie->cfg = map_physmem(pcie->cfg_res.start,
|
||||||
fdt_resource_size(&pcie->cfg_res),
|
fdt_resource_size(&pcie->cfg_res),
|
||||||
MAP_NOCACHE);
|
MAP_NOCACHE);
|
||||||
@ -522,10 +531,12 @@ static int ls_pcie_g4_probe(struct udevice *dev)
|
|||||||
pcie->mode = readb(pcie->ccsr + PCI_HEADER_TYPE) & 0x7f;
|
pcie->mode = readb(pcie->ccsr + PCI_HEADER_TYPE) & 0x7f;
|
||||||
|
|
||||||
if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
|
if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
|
||||||
printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
|
printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
|
||||||
|
"Endpoint");
|
||||||
ls_pcie_g4_setup_ep(pcie);
|
ls_pcie_g4_setup_ep(pcie);
|
||||||
} else {
|
} else {
|
||||||
printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
|
printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
|
||||||
|
"Root Complex");
|
||||||
ls_pcie_g4_setup_ctrl(pcie);
|
ls_pcie_g4_setup_ctrl(pcie);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -273,7 +273,8 @@ static int ls_pcie_probe(struct udevice *dev)
|
|||||||
|
|
||||||
pcie_rc->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
|
pcie_rc->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
|
||||||
if (!pcie_rc->enabled) {
|
if (!pcie_rc->enabled) {
|
||||||
printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
|
printf("PCIe%d: %s disabled\n", PCIE_SRDS_PRTCL(pcie->idx),
|
||||||
|
dev->name);
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -313,6 +314,13 @@ static int ls_pcie_probe(struct udevice *dev)
|
|||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
cfg_size = fdt_resource_size(&pcie_rc->cfg_res);
|
||||||
|
if (cfg_size < SZ_8K) {
|
||||||
|
printf("PCIe%d: %s Invalid size(0x%llx) for resource \"config\",expected minimum 0x%x\n",
|
||||||
|
PCIE_SRDS_PRTCL(pcie->idx), dev->name, (u64)cfg_size, SZ_8K);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Fix the pcie memory map address and PF control registers address
|
* Fix the pcie memory map address and PF control registers address
|
||||||
* for LS2088A series SoCs
|
* for LS2088A series SoCs
|
||||||
@ -322,7 +330,6 @@ static int ls_pcie_probe(struct udevice *dev)
|
|||||||
if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
|
if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
|
||||||
svr == SVR_LS2048A || svr == SVR_LS2044A ||
|
svr == SVR_LS2048A || svr == SVR_LS2044A ||
|
||||||
svr == SVR_LS2081A || svr == SVR_LS2041A) {
|
svr == SVR_LS2081A || svr == SVR_LS2041A) {
|
||||||
cfg_size = fdt_resource_size(&pcie_rc->cfg_res);
|
|
||||||
pcie_rc->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
|
pcie_rc->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
|
||||||
LS2088A_PCIE_PHYS_SIZE * pcie->idx;
|
LS2088A_PCIE_PHYS_SIZE * pcie->idx;
|
||||||
pcie_rc->cfg_res.end = pcie_rc->cfg_res.start + cfg_size;
|
pcie_rc->cfg_res.end = pcie_rc->cfg_res.start + cfg_size;
|
||||||
@ -342,7 +349,8 @@ static int ls_pcie_probe(struct udevice *dev)
|
|||||||
(unsigned long)pcie->ctrl, (unsigned long)pcie_rc->cfg0,
|
(unsigned long)pcie->ctrl, (unsigned long)pcie_rc->cfg0,
|
||||||
pcie->big_endian);
|
pcie->big_endian);
|
||||||
|
|
||||||
printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
|
printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
|
||||||
|
"Root Complex");
|
||||||
ls_pcie_setup_ctrl(pcie_rc);
|
ls_pcie_setup_ctrl(pcie_rc);
|
||||||
|
|
||||||
if (!ls_pcie_link_up(pcie)) {
|
if (!ls_pcie_link_up(pcie)) {
|
||||||
|
@ -102,5 +102,67 @@
|
|||||||
|
|
||||||
#define CONFIG_PCI_SCAN_SHOW
|
#define CONFIG_PCI_SCAN_SHOW
|
||||||
|
|
||||||
|
#undef CONFIG_EXTRA_ENV_SETTINGS
|
||||||
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||||
|
"verify=no\0" \
|
||||||
|
"fdt_addr=0x00f00000\0" \
|
||||||
|
"kernel_addr=0x01000000\0" \
|
||||||
|
"kernelheader_addr=0x600000\0" \
|
||||||
|
"scriptaddr=0x80000000\0" \
|
||||||
|
"scripthdraddr=0x80080000\0" \
|
||||||
|
"fdtheader_addr_r=0x80100000\0" \
|
||||||
|
"kernelheader_addr_r=0x80200000\0" \
|
||||||
|
"kernel_addr_r=0x96000000\0" \
|
||||||
|
"fdt_addr_r=0x90000000\0" \
|
||||||
|
"load_addr=0xa0000000\0" \
|
||||||
|
"kernel_size=0x2800000\0" \
|
||||||
|
"kernelheader_size=0x40000\0" \
|
||||||
|
"console=ttyS0,115200\0" \
|
||||||
|
BOOTENV \
|
||||||
|
"boot_scripts=ls1012aqds_boot.scr\0" \
|
||||||
|
"boot_script_hdr=hdr_ls1012aqds_bs.out\0" \
|
||||||
|
"scan_dev_for_boot_part=" \
|
||||||
|
"part list ${devtype} ${devnum} devplist; " \
|
||||||
|
"env exists devplist || setenv devplist 1; " \
|
||||||
|
"for distro_bootpart in ${devplist}; do " \
|
||||||
|
"if fstype ${devtype} " \
|
||||||
|
"${devnum}:${distro_bootpart} " \
|
||||||
|
"bootfstype; then " \
|
||||||
|
"run scan_dev_for_boot; " \
|
||||||
|
"fi; " \
|
||||||
|
"done\0" \
|
||||||
|
"scan_dev_for_boot=" \
|
||||||
|
"echo Scanning ${devtype} " \
|
||||||
|
"${devnum}:${distro_bootpart}...; " \
|
||||||
|
"for prefix in ${boot_prefixes}; do " \
|
||||||
|
"run scan_dev_for_scripts; " \
|
||||||
|
"done;" \
|
||||||
|
"\0" \
|
||||||
|
"boot_a_script=" \
|
||||||
|
"load ${devtype} ${devnum}:${distro_bootpart} " \
|
||||||
|
"${scriptaddr} ${prefix}${script}; " \
|
||||||
|
"env exists secureboot && load ${devtype} " \
|
||||||
|
"${devnum}:${distro_bootpart} " \
|
||||||
|
"${scripthdraddr} ${prefix}${boot_script_hdr}; " \
|
||||||
|
"env exists secureboot " \
|
||||||
|
"&& esbc_validate ${scripthdraddr};" \
|
||||||
|
"source ${scriptaddr}\0" \
|
||||||
|
"qspi_bootcmd=pfe stop; echo Trying load from qspi..;" \
|
||||||
|
"sf probe 0:0 && sf read $load_addr " \
|
||||||
|
"$kernel_addr $kernel_size; env exists secureboot " \
|
||||||
|
"&& sf read $kernelheader_addr_r $kernelheader_addr " \
|
||||||
|
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
|
||||||
|
"bootm $load_addr#$board\0"
|
||||||
|
|
||||||
|
#undef CONFIG_BOOTCOMMAND
|
||||||
|
#ifdef CONFIG_TFABOOT
|
||||||
|
#undef QSPI_NOR_BOOTCOMMAND
|
||||||
|
#define QSPI_NOR_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\
|
||||||
|
"env exists secureboot && esbc_halt;"
|
||||||
|
#else
|
||||||
|
#define CONFIG_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\
|
||||||
|
"env exists secureboot && esbc_halt;"
|
||||||
|
#endif
|
||||||
|
|
||||||
#include <asm/fsl_secure_boot.h>
|
#include <asm/fsl_secure_boot.h>
|
||||||
#endif /* __LS1012AQDS_H__ */
|
#endif /* __LS1012AQDS_H__ */
|
||||||
|
@ -247,12 +247,12 @@
|
|||||||
"kernelheader_start=0x800000\0" \
|
"kernelheader_start=0x800000\0" \
|
||||||
"fdt_addr_r=0x90000000\0" \
|
"fdt_addr_r=0x90000000\0" \
|
||||||
"load_addr=0xa0000000\0" \
|
"load_addr=0xa0000000\0" \
|
||||||
"kernelheader_addr=0x60800000\0" \
|
"kernelheader_addr=0x60600000\0" \
|
||||||
"kernel_size=0x2800000\0" \
|
"kernel_size=0x2800000\0" \
|
||||||
"kernelheader_size=0x40000\0" \
|
"kernelheader_size=0x40000\0" \
|
||||||
"kernel_addr_sd=0x8000\0" \
|
"kernel_addr_sd=0x8000\0" \
|
||||||
"kernel_size_sd=0x14000\0" \
|
"kernel_size_sd=0x14000\0" \
|
||||||
"kernelhdr_addr_sd=0x4000\0" \
|
"kernelhdr_addr_sd=0x3000\0" \
|
||||||
"kernelhdr_size_sd=0x10\0" \
|
"kernelhdr_size_sd=0x10\0" \
|
||||||
"console=ttyS0,115200\0" \
|
"console=ttyS0,115200\0" \
|
||||||
"boot_os=y\0" \
|
"boot_os=y\0" \
|
||||||
|
@ -149,8 +149,10 @@
|
|||||||
/* USB */
|
/* USB */
|
||||||
#ifdef CONFIG_USB
|
#ifdef CONFIG_USB
|
||||||
#define CONFIG_HAS_FSL_XHCI_USB
|
#define CONFIG_HAS_FSL_XHCI_USB
|
||||||
|
#ifndef CONFIG_TARGET_LX2162AQDS
|
||||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
||||||
#endif
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
/* FlexSPI */
|
/* FlexSPI */
|
||||||
#ifdef CONFIG_NXP_FSPI
|
#ifdef CONFIG_NXP_FSPI
|
||||||
@ -230,7 +232,7 @@ unsigned long get_board_ddr_clk(void);
|
|||||||
"kernel_size=0x2800000\0" \
|
"kernel_size=0x2800000\0" \
|
||||||
"kernel_addr_sd=0x8000\0" \
|
"kernel_addr_sd=0x8000\0" \
|
||||||
"kernelhdr_addr_sd=0x3000\0" \
|
"kernelhdr_addr_sd=0x3000\0" \
|
||||||
"kernel_size_sd=0x1d000\0" \
|
"kernel_size_sd=0x14000\0" \
|
||||||
"kernelhdr_size_sd=0x20\0" \
|
"kernelhdr_size_sd=0x20\0" \
|
||||||
"console=ttyAMA0,38400n8\0" \
|
"console=ttyAMA0,38400n8\0" \
|
||||||
BOOTENV \
|
BOOTENV \
|
||||||
|
@ -8,70 +8,14 @@
|
|||||||
|
|
||||||
#include "lx2160a_common.h"
|
#include "lx2160a_common.h"
|
||||||
|
|
||||||
/* Qixis */
|
|
||||||
#define QIXIS_XMAP_MASK 0x07
|
|
||||||
#define QIXIS_XMAP_SHIFT 5
|
|
||||||
#define QIXIS_RST_CTL_RESET_EN 0x30
|
|
||||||
#define QIXIS_LBMAP_DFLTBANK 0x00
|
|
||||||
#define QIXIS_LBMAP_ALTBANK 0x20
|
|
||||||
#define QIXIS_LBMAP_QSPI 0x00
|
|
||||||
#define QIXIS_RCW_SRC_QSPI 0xff
|
|
||||||
#define QIXIS_RST_CTL_RESET 0x31
|
|
||||||
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
|
|
||||||
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
|
|
||||||
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
|
|
||||||
#define QIXIS_LBMAP_MASK 0x0f
|
|
||||||
#define QIXIS_LBMAP_SD
|
|
||||||
#define QIXIS_LBMAP_EMMC
|
|
||||||
#define QIXIS_RCW_SRC_SD 0x08
|
|
||||||
#define QIXIS_RCW_SRC_EMMC 0x09
|
|
||||||
#define NON_EXTENDED_DUTCFG
|
|
||||||
#define QIXIS_SDID_MASK 0x07
|
|
||||||
#define QIXIS_ESDHC_NO_ADAPTER 0x7
|
|
||||||
|
|
||||||
/* SYSCLK */
|
|
||||||
#define QIXIS_SYSCLK_100 0x0
|
|
||||||
#define QIXIS_SYSCLK_125 0x1
|
|
||||||
#define QIXIS_SYSCLK_133 0x2
|
|
||||||
|
|
||||||
/* DDRCLK */
|
|
||||||
#define QIXIS_DDRCLK_100 0x0
|
|
||||||
#define QIXIS_DDRCLK_125 0x1
|
|
||||||
#define QIXIS_DDRCLK_133 0x2
|
|
||||||
|
|
||||||
#define BRDCFG4_EMI1SEL_MASK 0xF8
|
|
||||||
#define BRDCFG4_EMI1SEL_SHIFT 3
|
|
||||||
#define BRDCFG4_EMI2SEL_MASK 0x07
|
|
||||||
#define BRDCFG4_EMI2SEL_SHIFT 0
|
|
||||||
|
|
||||||
/* VID */
|
/* VID */
|
||||||
|
|
||||||
#define I2C_MUX_CH_VOL_MONITOR 0xA
|
|
||||||
/* Voltage monitor on channel 2*/
|
|
||||||
#define I2C_VOL_MONITOR_ADDR 0x63
|
|
||||||
#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
|
|
||||||
#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
|
|
||||||
#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
|
|
||||||
#define CONFIG_VID_FLS_ENV "lx2160aqds_vdd_mv"
|
#define CONFIG_VID_FLS_ENV "lx2160aqds_vdd_mv"
|
||||||
#define CONFIG_VID
|
#define CONFIG_VID
|
||||||
|
|
||||||
/* The lowest and highest voltage allowed*/
|
|
||||||
#define VDD_MV_MIN 775
|
|
||||||
#define VDD_MV_MAX 925
|
|
||||||
|
|
||||||
/* PM Bus commands code for LTC3882*/
|
|
||||||
#define PMBUS_CMD_PAGE 0x0
|
|
||||||
#define PMBUS_CMD_READ_VOUT 0x8B
|
|
||||||
#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
|
|
||||||
#define PMBUS_CMD_VOUT_COMMAND 0x21
|
|
||||||
#define PWM_CHANNEL0 0x0
|
|
||||||
|
|
||||||
#define CONFIG_VOL_MONITOR_LTC3882_SET
|
#define CONFIG_VOL_MONITOR_LTC3882_SET
|
||||||
#define CONFIG_VOL_MONITOR_LTC3882_READ
|
#define CONFIG_VOL_MONITOR_LTC3882_READ
|
||||||
|
|
||||||
/* RTC */
|
/* RTC */
|
||||||
#define CONFIG_SYS_RTC_BUS_NUM 0
|
#define CONFIG_SYS_RTC_BUS_NUM 0
|
||||||
#define I2C_MUX_CH_RTC 0xB
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MMC
|
* MMC
|
||||||
@ -87,26 +31,6 @@ u8 qixis_esdhc_detect_quirk(void);
|
|||||||
#if defined(CONFIG_FSL_MC_ENET)
|
#if defined(CONFIG_FSL_MC_ENET)
|
||||||
#define CONFIG_MII
|
#define CONFIG_MII
|
||||||
#define CONFIG_ETHPRIME "DPMAC17@rgmii-id"
|
#define CONFIG_ETHPRIME "DPMAC17@rgmii-id"
|
||||||
|
|
||||||
#define AQ_PHY_ADDR1 0x00
|
|
||||||
#define AQ_PHY_ADDR2 0x01
|
|
||||||
#define AQ_PHY_ADDR3 0x02
|
|
||||||
#define AQ_PHY_ADDR4 0x03
|
|
||||||
|
|
||||||
#define CORTINA_NO_FW_UPLOAD
|
|
||||||
#define CORTINA_PHY_ADDR1 0x0
|
|
||||||
|
|
||||||
#define INPHI_PHY_ADDR1 0x0
|
|
||||||
#define INPHI_PHY_ADDR2 0x1
|
|
||||||
|
|
||||||
#define RGMII_PHY_ADDR1 0x01
|
|
||||||
#define RGMII_PHY_ADDR2 0x02
|
|
||||||
|
|
||||||
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
|
|
||||||
#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
|
|
||||||
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
|
|
||||||
#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* EEPROM */
|
/* EEPROM */
|
||||||
|
@ -8,47 +8,9 @@
|
|||||||
|
|
||||||
#include "lx2160a_common.h"
|
#include "lx2160a_common.h"
|
||||||
|
|
||||||
/* Qixis */
|
|
||||||
#define QIXIS_XMAP_MASK 0x07
|
|
||||||
#define QIXIS_XMAP_SHIFT 5
|
|
||||||
#define QIXIS_RST_CTL_RESET_EN 0x30
|
|
||||||
#define QIXIS_LBMAP_DFLTBANK 0x00
|
|
||||||
#define QIXIS_LBMAP_ALTBANK 0x20
|
|
||||||
#define QIXIS_LBMAP_QSPI 0x00
|
|
||||||
#define QIXIS_RCW_SRC_QSPI 0xff
|
|
||||||
#define QIXIS_RST_CTL_RESET 0x31
|
|
||||||
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
|
|
||||||
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
|
|
||||||
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
|
|
||||||
#define QIXIS_LBMAP_MASK 0x0f
|
|
||||||
#define QIXIS_LBMAP_SD
|
|
||||||
#define QIXIS_LBMAP_EMMC
|
|
||||||
#define QIXIS_RCW_SRC_SD 0x08
|
|
||||||
#define QIXIS_RCW_SRC_EMMC 0x09
|
|
||||||
#define NON_EXTENDED_DUTCFG
|
|
||||||
|
|
||||||
/* VID */
|
/* VID */
|
||||||
|
|
||||||
#define I2C_MUX_CH_VOL_MONITOR 0xA
|
|
||||||
/* Voltage monitor on channel 2*/
|
|
||||||
#define I2C_VOL_MONITOR_ADDR 0x63
|
|
||||||
#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
|
|
||||||
#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
|
|
||||||
#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
|
|
||||||
#define CONFIG_VID_FLS_ENV "lx2160ardb_vdd_mv"
|
#define CONFIG_VID_FLS_ENV "lx2160ardb_vdd_mv"
|
||||||
#define CONFIG_VID
|
#define CONFIG_VID
|
||||||
|
|
||||||
/* The lowest and highest voltage allowed*/
|
|
||||||
#define VDD_MV_MIN 775
|
|
||||||
#define VDD_MV_MAX 855
|
|
||||||
|
|
||||||
/* PM Bus commands code for LTC3882*/
|
|
||||||
#define PMBUS_CMD_PAGE 0x0
|
|
||||||
#define PMBUS_CMD_READ_VOUT 0x8B
|
|
||||||
#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
|
|
||||||
#define PMBUS_CMD_VOUT_COMMAND 0x21
|
|
||||||
#define PWM_CHANNEL0 0x0
|
|
||||||
|
|
||||||
#define CONFIG_VOL_MONITOR_LTC3882_SET
|
#define CONFIG_VOL_MONITOR_LTC3882_SET
|
||||||
#define CONFIG_VOL_MONITOR_LTC3882_READ
|
#define CONFIG_VOL_MONITOR_LTC3882_READ
|
||||||
|
|
||||||
@ -59,18 +21,6 @@
|
|||||||
#if defined(CONFIG_FSL_MC_ENET)
|
#if defined(CONFIG_FSL_MC_ENET)
|
||||||
#define CONFIG_MII
|
#define CONFIG_MII
|
||||||
#define CONFIG_ETHPRIME "DPMAC1@xgmii"
|
#define CONFIG_ETHPRIME "DPMAC1@xgmii"
|
||||||
|
|
||||||
#define AQR107_PHY_ADDR1 0x04
|
|
||||||
#define AQR107_PHY_ADDR2 0x05
|
|
||||||
#define AQR107_IRQ_MASK 0x0C
|
|
||||||
|
|
||||||
#define CORTINA_NO_FW_UPLOAD
|
|
||||||
#define CORTINA_PHY_ADDR1 0x0
|
|
||||||
#define INPHI_PHY_ADDR1 0x0
|
|
||||||
|
|
||||||
#define RGMII_PHY_ADDR1 0x01
|
|
||||||
#define RGMII_PHY_ADDR2 0x02
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* EMC2305 */
|
/* EMC2305 */
|
||||||
|
78
include/configs/lx2162aqds.h
Normal file
78
include/configs/lx2162aqds.h
Normal file
@ -0,0 +1,78 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
|
/*
|
||||||
|
* Copyright 2020 NXP
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __LX2162_QDS_H
|
||||||
|
#define __LX2162_QDS_H
|
||||||
|
|
||||||
|
#include "lx2160a_common.h"
|
||||||
|
|
||||||
|
/* USB */
|
||||||
|
#undef CONFIG_USB_MAX_CONTROLLER_COUNT
|
||||||
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||||
|
|
||||||
|
/* Voltage monitor on channel 2*/
|
||||||
|
#define CONFIG_VID_FLS_ENV "lx2162aqds_vdd_mv"
|
||||||
|
#define CONFIG_VID
|
||||||
|
#define CONFIG_VOL_MONITOR_LTC3882_SET
|
||||||
|
#define CONFIG_VOL_MONITOR_LTC3882_READ
|
||||||
|
|
||||||
|
/* RTC */
|
||||||
|
#define CONFIG_SYS_RTC_BUS_NUM 0
|
||||||
|
|
||||||
|
/*
|
||||||
|
* MMC
|
||||||
|
*/
|
||||||
|
#ifdef CONFIG_MMC
|
||||||
|
#ifndef __ASSEMBLY__
|
||||||
|
u8 qixis_esdhc_detect_quirk(void);
|
||||||
|
#endif
|
||||||
|
#define CONFIG_ESDHC_DETECT_QUIRK qixis_esdhc_detect_quirk()
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* MAC/PHY configuration */
|
||||||
|
#if defined(CONFIG_FSL_MC_ENET)
|
||||||
|
#define CONFIG_MII
|
||||||
|
#define CONFIG_ETHPRIME "DPMAC17@rgmii-id"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* EEPROM */
|
||||||
|
#define CONFIG_ID_EEPROM
|
||||||
|
#define CONFIG_SYS_I2C_EEPROM_NXID
|
||||||
|
#define CONFIG_SYS_EEPROM_BUS_NUM 0
|
||||||
|
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
|
||||||
|
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||||
|
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
|
||||||
|
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
|
||||||
|
|
||||||
|
/* Initial environment variables */
|
||||||
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||||
|
EXTRA_ENV_SETTINGS \
|
||||||
|
"boot_scripts=lx2162aqds_boot.scr\0" \
|
||||||
|
"boot_script_hdr=hdr_lx2162aqds_bs.out\0" \
|
||||||
|
"BOARD=lx2162aqds\0" \
|
||||||
|
"xspi_bootcmd=echo Trying load from flexspi..;" \
|
||||||
|
"sf probe 0:0 && sf read $load_addr " \
|
||||||
|
"$kernel_start $kernel_size ; env exists secureboot &&" \
|
||||||
|
"sf read $kernelheader_addr_r $kernelheader_start " \
|
||||||
|
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
|
||||||
|
" bootm $load_addr#$BOARD\0" \
|
||||||
|
"sd_bootcmd=echo Trying load from sd card..;" \
|
||||||
|
"mmc dev 0; mmcinfo; mmc read $load_addr " \
|
||||||
|
"$kernel_addr_sd $kernel_size_sd ;" \
|
||||||
|
"env exists secureboot && mmc read $kernelheader_addr_r "\
|
||||||
|
"$kernelhdr_addr_sd $kernelhdr_size_sd " \
|
||||||
|
" && esbc_validate ${kernelheader_addr_r};" \
|
||||||
|
"bootm $load_addr#$BOARD\0" \
|
||||||
|
"emmc_bootcmd=echo Trying load from emmc card..;" \
|
||||||
|
"mmc dev 1; mmcinfo; mmc read $load_addr " \
|
||||||
|
"$kernel_addr_sd $kernel_size_sd ;" \
|
||||||
|
"env exists secureboot && mmc read $kernelheader_addr_r "\
|
||||||
|
"$kernelhdr_addr_sd $kernelhdr_size_sd " \
|
||||||
|
" && esbc_validate ${kernelheader_addr_r};" \
|
||||||
|
"bootm $load_addr#$BOARD\0"
|
||||||
|
|
||||||
|
#include <asm/fsl_secure_boot.h>
|
||||||
|
|
||||||
|
#endif /* __LX2162_QDS_H */
|
@ -52,6 +52,8 @@
|
|||||||
/* Machine Select */
|
/* Machine Select */
|
||||||
#define CSPR_MSEL 0x00000006
|
#define CSPR_MSEL 0x00000006
|
||||||
#define CSPR_MSEL_SHIFT 1
|
#define CSPR_MSEL_SHIFT 1
|
||||||
|
/* External Transceiver Enable */
|
||||||
|
#define CSPR_TE 0x00000010
|
||||||
/* NOR */
|
/* NOR */
|
||||||
#define CSPR_MSEL_NOR 0x00000000
|
#define CSPR_MSEL_NOR 0x00000000
|
||||||
/* NAND */
|
/* NAND */
|
||||||
|
Loading…
Reference in New Issue
Block a user