mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-10-01 09:00:45 +09:00
pcm052: board: Remove in-board setup code (it is now replaced by DM setup)
This commit cleans up the pcm052.c file to remove dead code after moving to DTS and DM. Signed-off-by: Lukasz Majewski <lukma@denx.de>
This commit is contained in:
Lukasz Majewski
Stefano Babic
parent
6f854c6655
commit
27e15e533c
@ -13,79 +13,9 @@
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#include <asm/arch/ddrmc-vf610.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/clock.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <i2c.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Default DDR pad settings in arch/arm/include/asm/arch-vf610/iomux-vf610.h
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* do not match our settings. Let us (re)define our own settings here.
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*/
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#define PCM052_VF610_DDR_PAD_CTRL PAD_CTL_DSE_20ohm
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#define PCM052_VF610_DDR_PAD_CTRL_1 (PAD_CTL_DSE_20ohm | \
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PAD_CTL_INPUT_DIFFERENTIAL)
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#define PCM052_VF610_DDR_RESET_PAD_CTL (PAD_CTL_DSE_150ohm | \
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PAD_CTL_PUS_100K_UP | \
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PAD_CTL_INPUT_DIFFERENTIAL)
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enum {
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PCM052_VF610_PAD_DDR_RESETB = IOMUX_PAD(0x021c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_RESET_PAD_CTL),
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PCM052_VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_A12__DDR_A_12 = IOMUX_PAD(0x022c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_A11__DDR_A_11 = IOMUX_PAD(0x0230, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_A10__DDR_A_10 = IOMUX_PAD(0x0234, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_A9__DDR_A_9 = IOMUX_PAD(0x0238, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_A8__DDR_A_8 = IOMUX_PAD(0x023c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_A7__DDR_A_7 = IOMUX_PAD(0x0240, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_A6__DDR_A_6 = IOMUX_PAD(0x0244, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_A5__DDR_A_5 = IOMUX_PAD(0x0248, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_A4__DDR_A_4 = IOMUX_PAD(0x024c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_A3__DDR_A_3 = IOMUX_PAD(0x0250, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_A2__DDR_A_2 = IOMUX_PAD(0x0254, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_A1__DDR_A_1 = IOMUX_PAD(0x0258, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_A0__DDR_A_0 = IOMUX_PAD(0x025c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_BA2__DDR_BA_2 = IOMUX_PAD(0x0260, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_BA1__DDR_BA_1 = IOMUX_PAD(0x0264, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_BA0__DDR_BA_0 = IOMUX_PAD(0x0268, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_CAS__DDR_CAS_B = IOMUX_PAD(0x026c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_CKE__DDR_CKE_0 = IOMUX_PAD(0x0270, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_CLK__DDR_CLK_0 = IOMUX_PAD(0x0274, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1),
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PCM052_VF610_PAD_DDR_CS__DDR_CS_B_0 = IOMUX_PAD(0x0278, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1),
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PCM052_VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1),
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PCM052_VF610_PAD_DDR_RAS__DDR_RAS_B = IOMUX_PAD(0x02cc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_ODT0__DDR_ODT_1 = IOMUX_PAD(0x02d8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 = IOMUX_PAD(0x02dc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0 = IOMUX_PAD(0x02e0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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};
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static struct ddrmc_cr_setting pcm052_cr_settings[] = {
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/* not in the datasheets, but in the original code */
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{ 0x00002000, 105 },
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@ -154,59 +84,6 @@ static struct ddrmc_phy_setting pcm052_phy_settings[] = {
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int dram_init(void)
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{
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static const iomux_v3_cfg_t pcm052_pads[] = {
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PCM052_VF610_PAD_DDR_A15__DDR_A_15,
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PCM052_VF610_PAD_DDR_A14__DDR_A_14,
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PCM052_VF610_PAD_DDR_A13__DDR_A_13,
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PCM052_VF610_PAD_DDR_A12__DDR_A_12,
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PCM052_VF610_PAD_DDR_A11__DDR_A_11,
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PCM052_VF610_PAD_DDR_A10__DDR_A_10,
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PCM052_VF610_PAD_DDR_A9__DDR_A_9,
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PCM052_VF610_PAD_DDR_A8__DDR_A_8,
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PCM052_VF610_PAD_DDR_A7__DDR_A_7,
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PCM052_VF610_PAD_DDR_A6__DDR_A_6,
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PCM052_VF610_PAD_DDR_A5__DDR_A_5,
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PCM052_VF610_PAD_DDR_A4__DDR_A_4,
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PCM052_VF610_PAD_DDR_A3__DDR_A_3,
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PCM052_VF610_PAD_DDR_A2__DDR_A_2,
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PCM052_VF610_PAD_DDR_A1__DDR_A_1,
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PCM052_VF610_PAD_DDR_A0__DDR_A_0,
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PCM052_VF610_PAD_DDR_BA2__DDR_BA_2,
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PCM052_VF610_PAD_DDR_BA1__DDR_BA_1,
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PCM052_VF610_PAD_DDR_BA0__DDR_BA_0,
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PCM052_VF610_PAD_DDR_CAS__DDR_CAS_B,
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PCM052_VF610_PAD_DDR_CKE__DDR_CKE_0,
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PCM052_VF610_PAD_DDR_CLK__DDR_CLK_0,
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PCM052_VF610_PAD_DDR_CS__DDR_CS_B_0,
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PCM052_VF610_PAD_DDR_D15__DDR_D_15,
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PCM052_VF610_PAD_DDR_D14__DDR_D_14,
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PCM052_VF610_PAD_DDR_D13__DDR_D_13,
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PCM052_VF610_PAD_DDR_D12__DDR_D_12,
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PCM052_VF610_PAD_DDR_D11__DDR_D_11,
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PCM052_VF610_PAD_DDR_D10__DDR_D_10,
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PCM052_VF610_PAD_DDR_D9__DDR_D_9,
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PCM052_VF610_PAD_DDR_D8__DDR_D_8,
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PCM052_VF610_PAD_DDR_D7__DDR_D_7,
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PCM052_VF610_PAD_DDR_D6__DDR_D_6,
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PCM052_VF610_PAD_DDR_D5__DDR_D_5,
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PCM052_VF610_PAD_DDR_D4__DDR_D_4,
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PCM052_VF610_PAD_DDR_D3__DDR_D_3,
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PCM052_VF610_PAD_DDR_D2__DDR_D_2,
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PCM052_VF610_PAD_DDR_D1__DDR_D_1,
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PCM052_VF610_PAD_DDR_D0__DDR_D_0,
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PCM052_VF610_PAD_DDR_DQM1__DDR_DQM_1,
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PCM052_VF610_PAD_DDR_DQM0__DDR_DQM_0,
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PCM052_VF610_PAD_DDR_DQS1__DDR_DQS_1,
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PCM052_VF610_PAD_DDR_DQS0__DDR_DQS_0,
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PCM052_VF610_PAD_DDR_RAS__DDR_RAS_B,
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PCM052_VF610_PAD_DDR_WE__DDR_WE_B,
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PCM052_VF610_PAD_DDR_ODT1__DDR_ODT_0,
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PCM052_VF610_PAD_DDR_ODT0__DDR_ODT_1,
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PCM052_VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1,
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PCM052_VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0,
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PCM052_VF610_PAD_DDR_RESETB,
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};
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#if defined(CONFIG_TARGET_PCM052)
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static const struct ddr3_jedec_timings pcm052_ddr_timings = {
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@ -323,8 +200,6 @@ int dram_init(void)
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#endif
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imx_iomux_v3_setup_multiple_pads(pcm052_pads, ARRAY_SIZE(pcm052_pads));
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ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings,
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pcm052_phy_settings, 1, row_diff);
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@ -333,135 +208,6 @@ int dram_init(void)
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return 0;
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}
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static void setup_iomux_uart(void)
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{
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static const iomux_v3_cfg_t uart1_pads[] = {
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NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, VF610_UART_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, VF610_UART_PAD_CTRL),
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};
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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}
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#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
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PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
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static void setup_iomux_enet(void)
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{
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static const iomux_v3_cfg_t enet0_pads[] = {
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NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL),
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};
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imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
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}
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/*
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* I2C2 is the only I2C used, on pads PTA22/PTA23.
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*/
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static void setup_iomux_i2c(void)
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{
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static const iomux_v3_cfg_t i2c_pads[] = {
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VF610_PAD_PTA22__I2C2_SCL,
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VF610_PAD_PTA23__I2C2_SDA,
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};
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imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
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}
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#ifdef CONFIG_NAND_VF610_NFC
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static void setup_iomux_nfc(void)
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{
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static const iomux_v3_cfg_t nfc_pads[] = {
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VF610_PAD_PTD31__NF_IO15,
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VF610_PAD_PTD30__NF_IO14,
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VF610_PAD_PTD29__NF_IO13,
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VF610_PAD_PTD28__NF_IO12,
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VF610_PAD_PTD27__NF_IO11,
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VF610_PAD_PTD26__NF_IO10,
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VF610_PAD_PTD25__NF_IO9,
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VF610_PAD_PTD24__NF_IO8,
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VF610_PAD_PTD23__NF_IO7,
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VF610_PAD_PTD22__NF_IO6,
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VF610_PAD_PTD21__NF_IO5,
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VF610_PAD_PTD20__NF_IO4,
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VF610_PAD_PTD19__NF_IO3,
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VF610_PAD_PTD18__NF_IO2,
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VF610_PAD_PTD17__NF_IO1,
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VF610_PAD_PTD16__NF_IO0,
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VF610_PAD_PTB24__NF_WE_B,
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VF610_PAD_PTB25__NF_CE0_B,
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VF610_PAD_PTB27__NF_RE_B,
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VF610_PAD_PTC26__NF_RB_B,
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VF610_PAD_PTC27__NF_ALE,
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VF610_PAD_PTC28__NF_CLE
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};
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imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
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}
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#endif
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static void setup_iomux_qspi(void)
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{
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static const iomux_v3_cfg_t qspi0_pads[] = {
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VF610_PAD_PTD0__QSPI0_A_QSCK,
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VF610_PAD_PTD1__QSPI0_A_CS0,
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VF610_PAD_PTD2__QSPI0_A_DATA3,
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VF610_PAD_PTD3__QSPI0_A_DATA2,
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VF610_PAD_PTD4__QSPI0_A_DATA1,
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VF610_PAD_PTD5__QSPI0_A_DATA0,
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VF610_PAD_PTD7__QSPI0_B_QSCK,
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VF610_PAD_PTD8__QSPI0_B_CS0,
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VF610_PAD_PTD9__QSPI0_B_DATA3,
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VF610_PAD_PTD10__QSPI0_B_DATA2,
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VF610_PAD_PTD11__QSPI0_B_DATA1,
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VF610_PAD_PTD12__QSPI0_B_DATA0,
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};
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imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads));
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}
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#define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
|
||||
PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
|
||||
|
||||
struct fsl_esdhc_cfg esdhc_cfg[1] = {
|
||||
{ESDHC1_BASE_ADDR},
|
||||
};
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
/* eSDHC1 is always present */
|
||||
return 1;
|
||||
}
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
static const iomux_v3_cfg_t esdhc1_pads[] = {
|
||||
NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
|
||||
NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
|
||||
NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
|
||||
NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
|
||||
NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
|
||||
NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
|
||||
};
|
||||
|
||||
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
|
||||
|
||||
return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
|
||||
}
|
||||
|
||||
static void clock_init(void)
|
||||
{
|
||||
struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
|
||||
@ -534,23 +280,10 @@ static void mscm_init(void)
|
||||
writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
|
||||
}
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
if (phydev->drv->config)
|
||||
phydev->drv->config(phydev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
clock_init();
|
||||
mscm_init();
|
||||
setup_iomux_uart();
|
||||
setup_iomux_enet();
|
||||
setup_iomux_i2c();
|
||||
setup_iomux_qspi();
|
||||
setup_iomux_nfc();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user