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https://github.com/brain-hackers/u-boot-brain
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ppc4xx: Fix problem in PLL clock calculation
This patch was originall provided by David Mitchell <dmitchell@amcc.com> and fixes a bug in the PLL clock calculation. Signed-off-by: Stefan Roese <sr@denx.de>
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35d22f957a
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@ -448,12 +448,17 @@ static void serial_divs (int baudrate, unsigned long *pudiv,
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unsigned long i;
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unsigned long i;
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unsigned long est; /* current estimate */
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unsigned long est; /* current estimate */
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unsigned long plloutb;
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unsigned long plloutb;
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unsigned long cpr_pllc;
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u32 reg;
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u32 reg;
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/* check the pll feedback source */
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mfcpr(cprpllc, cpr_pllc);
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get_sys_info(&sysinfo);
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get_sys_info(&sysinfo);
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plloutb = ((CONFIG_SYS_CLK_FREQ * sysinfo.pllFwdDiv * sysinfo.pllFbkDiv)
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plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ?
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/ sysinfo.pllFwdDivB);
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sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) * sysinfo.pllFbkDiv) /
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sysinfo.pllFwdDivB);
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udiv = 256; /* Assume lowest possible serial clk */
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udiv = 256; /* Assume lowest possible serial clk */
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div = plloutb / (16 * baudrate); /* total divisor */
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div = plloutb / (16 * baudrate); /* total divisor */
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umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */
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umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */
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@ -771,6 +771,7 @@ ulong get_PCI_freq (void)
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void get_sys_info (PPC405_SYS_INFO * sysInfo)
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void get_sys_info (PPC405_SYS_INFO * sysInfo)
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{
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{
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unsigned long cpr_plld;
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unsigned long cpr_plld;
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unsigned long cpr_pllc;
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unsigned long cpr_primad;
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unsigned long cpr_primad;
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unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ/1000);
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unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ/1000);
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unsigned long primad_cpudv;
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unsigned long primad_cpudv;
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@ -780,6 +781,7 @@ void get_sys_info (PPC405_SYS_INFO * sysInfo)
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* Read PLL Mode registers
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* Read PLL Mode registers
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*/
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*/
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mfcpr(cprplld, cpr_plld);
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mfcpr(cprplld, cpr_plld);
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mfcpr(cprpllc, cpr_pllc);
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/*
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/*
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* Determine forward divider A
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* Determine forward divider A
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@ -787,20 +789,18 @@ void get_sys_info (PPC405_SYS_INFO * sysInfo)
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sysInfo->pllFwdDiv = ((cpr_plld & PLLD_FWDVA_MASK) >> 16);
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sysInfo->pllFwdDiv = ((cpr_plld & PLLD_FWDVA_MASK) >> 16);
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/*
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/*
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* Determine forward divider B (should be equal to A)
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* Determine forward divider B
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*/
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*/
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sysInfo->pllFwdDivB = ((cpr_plld & PLLD_FWDVB_MASK) >> 8);
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sysInfo->pllFwdDivB = ((cpr_plld & PLLD_FWDVB_MASK) >> 8);
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if (sysInfo->pllFwdDivB == 0) {
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if (sysInfo->pllFwdDivB == 0)
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sysInfo->pllFwdDivB = 8;
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sysInfo->pllFwdDivB = 8;
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}
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/*
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/*
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* Determine FBK_DIV.
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* Determine FBK_DIV.
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*/
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*/
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sysInfo->pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
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sysInfo->pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
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if (sysInfo->pllFbkDiv == 0) {
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if (sysInfo->pllFbkDiv == 0)
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sysInfo->pllFbkDiv = 256;
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sysInfo->pllFbkDiv = 256;
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}
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/*
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/*
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* Read CPR_PRIMAD register
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* Read CPR_PRIMAD register
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@ -810,30 +810,30 @@ void get_sys_info (PPC405_SYS_INFO * sysInfo)
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* Determine PLB_DIV.
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* Determine PLB_DIV.
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*/
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*/
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sysInfo->pllPlbDiv = ((cpr_primad & PRIMAD_PLBDV_MASK) >> 16);
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sysInfo->pllPlbDiv = ((cpr_primad & PRIMAD_PLBDV_MASK) >> 16);
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if (sysInfo->pllPlbDiv == 0) {
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if (sysInfo->pllPlbDiv == 0)
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sysInfo->pllPlbDiv = 16;
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sysInfo->pllPlbDiv = 16;
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}
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/*
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/*
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* Determine EXTBUS_DIV.
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* Determine EXTBUS_DIV.
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*/
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*/
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sysInfo->pllExtBusDiv = (cpr_primad & PRIMAD_EBCDV_MASK);
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sysInfo->pllExtBusDiv = (cpr_primad & PRIMAD_EBCDV_MASK);
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if (sysInfo->pllExtBusDiv == 0) {
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if (sysInfo->pllExtBusDiv == 0)
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sysInfo->pllExtBusDiv = 16;
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sysInfo->pllExtBusDiv = 16;
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}
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/*
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/*
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* Determine OPB_DIV.
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* Determine OPB_DIV.
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*/
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*/
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sysInfo->pllOpbDiv = ((cpr_primad & PRIMAD_OPBDV_MASK) >> 8);
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sysInfo->pllOpbDiv = ((cpr_primad & PRIMAD_OPBDV_MASK) >> 8);
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if (sysInfo->pllOpbDiv == 0) {
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if (sysInfo->pllOpbDiv == 0)
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sysInfo->pllOpbDiv = 16;
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sysInfo->pllOpbDiv = 16;
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}
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/*
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/*
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* Determine the M factor
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* Determine the M factor
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*/
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*/
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m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB;
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if (cpr_pllc & PLLC_SRC_MASK)
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m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB;
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else
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m = sysInfo->pllFbkDiv * sysInfo->pllFwdDiv;
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/*
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/*
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* Determine VCO clock frequency
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* Determine VCO clock frequency
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@ -845,16 +845,17 @@ void get_sys_info (PPC405_SYS_INFO * sysInfo)
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* Determine CPU clock frequency
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* Determine CPU clock frequency
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*/
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*/
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primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24);
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primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24);
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if (primad_cpudv == 0) {
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if (primad_cpudv == 0)
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primad_cpudv = 16;
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primad_cpudv = 16;
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}
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sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / primad_cpudv;
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sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * m) /
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sysInfo->pllFwdDiv / primad_cpudv;
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/*
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/*
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* Determine PLB clock frequency
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* Determine PLB clock frequency
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*/
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*/
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sysInfo->freqPLB = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / sysInfo->pllPlbDiv;
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sysInfo->freqPLB = (CONFIG_SYS_CLK_FREQ * m) /
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sysInfo->pllFwdDiv / sysInfo->pllPlbDiv;
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}
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}
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/********************************************
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/********************************************
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@ -617,6 +617,8 @@
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#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */
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#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */
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#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
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#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
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#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
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#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
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#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
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#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */
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#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */
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#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */
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#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */
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