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gpio: mpc8xxx: Support controller register physical address beyond 32-bit
dev_read_addr_size_index() returns fdt_addr_t which might be a 64-bit physical address. This might be true for some 85xx SoCs whose CCSBAR is mapped beyond 4 GiB. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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@ -18,7 +18,7 @@
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#endif
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#endif
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struct mpc8xxx_gpio_plat {
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struct mpc8xxx_gpio_plat {
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ulong addr;
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phys_addr_t addr;
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unsigned long size;
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unsigned long size;
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uint ngpios;
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uint ngpios;
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};
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};
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@ -20,7 +20,7 @@ struct mpc8xxx_gpio_data {
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/* The bank's register base in memory */
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/* The bank's register base in memory */
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struct ccsr_gpio __iomem *base;
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struct ccsr_gpio __iomem *base;
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/* The address of the registers; used to identify the bank */
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/* The address of the registers; used to identify the bank */
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ulong addr;
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phys_addr_t addr;
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/* The GPIO count of the bank */
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/* The GPIO count of the bank */
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uint gpio_count;
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uint gpio_count;
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/* The GPDAT register cannot be used to determine the value of output
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/* The GPDAT register cannot be used to determine the value of output
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@ -181,7 +181,7 @@ static int mpc8xxx_gpio_of_to_plat(struct udevice *dev)
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if (dev_read_bool(dev, "little-endian"))
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if (dev_read_bool(dev, "little-endian"))
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data->little_endian = true;
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data->little_endian = true;
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plat->addr = (ulong)dev_read_addr_size_index(dev, 0, (fdt_size_t *)&plat->size);
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plat->addr = dev_read_addr_size_index(dev, 0, (fdt_size_t *)&plat->size);
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plat->ngpios = dev_read_u32_default(dev, "ngpios", 32);
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plat->ngpios = dev_read_u32_default(dev, "ngpios", 32);
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return 0;
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return 0;
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@ -220,7 +220,8 @@ static int mpc8xxx_gpio_probe(struct udevice *dev)
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mpc8xxx_gpio_plat_to_priv(dev);
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mpc8xxx_gpio_plat_to_priv(dev);
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snprintf(name, sizeof(name), "MPC@%lx_", data->addr);
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snprintf(name, sizeof(name), "MPC@%.8llx",
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(unsigned long long)data->addr);
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str = strdup(name);
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str = strdup(name);
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if (!str)
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if (!str)
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