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net: zynq_gem: Modify the nwcfg bit definitions
Modify the nwcfg bit definitions to have 32-bit by removing the extra nibble. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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@ -53,16 +53,16 @@ DECLARE_GLOBAL_DATA_PTR;
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#define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
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#define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
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#define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
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#define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
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#define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */
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#define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */
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#define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */
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#define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */
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#define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */
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#define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */
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#define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */
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#define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */
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#define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x080000000 /* SGMII Enable */
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#define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x80000000 /* SGMII Enable */
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#define ZYNQ_GEM_NWCFG_PCS_SEL 0x000000800 /* PCS select */
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#define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */
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#ifdef CONFIG_ARM64
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#ifdef CONFIG_ARM64
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#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000100000 /* Div pclk by 64, max 160MHz */
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#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */
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#else
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#else
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#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x0000c0000 /* Div pclk by 48, max 120MHz */
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#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */
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#endif
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#endif
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#ifdef CONFIG_ARM64
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#ifdef CONFIG_ARM64
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