mips: jz47xx: Add Creator CI20 platform
Add support for the Creator CI20 platform based on the JZ4780 SoC. Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Reviewed-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Paul Burton
Daniel Schwierzeck
parent
cd71b1d5d2
commit
25c7de2255
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@ -16,6 +16,7 @@ dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
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dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
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dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb
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dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
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dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
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targets += $(dtb-y)
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@ -0,0 +1,122 @@
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// SPDX-License-Identifier: GPL-2.0+
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/dts-v1/;
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#include "jz4780.dtsi"
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/ {
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compatible = "img,ci20", "ingenic,jz4780";
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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serial3 = &uart3;
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serial4 = &uart4;
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};
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chosen {
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stdout-path = "serial4:115200n8";
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x10000000
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0x30000000 0x30000000>;
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};
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};
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&ext {
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clock-frequency = <48000000>;
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};
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&uart0 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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&uart3 {
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status = "okay";
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};
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&uart4 {
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status = "okay";
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};
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&nemc {
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status = "okay";
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nandc: nand-controller@1 {
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compatible = "ingenic,jz4780-nand";
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reg = <1 0 0x1000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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ingenic,bch-controller = <&bch>;
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ingenic,nemc-tAS = <10>;
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ingenic,nemc-tAH = <5>;
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ingenic,nemc-tBP = <10>;
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ingenic,nemc-tAW = <15>;
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ingenic,nemc-tSTRV = <100>;
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nand@1 {
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reg = <1>;
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nand-ecc-step-size = <1024>;
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nand-ecc-strength = <24>;
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nand-ecc-mode = "hw";
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nand-on-flash-bbt;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <2>;
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#size-cells = <2>;
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partition@0 {
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label = "u-boot-spl";
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reg = <0x0 0x0 0x0 0x800000>;
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};
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partition@0x800000 {
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label = "u-boot";
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reg = <0x0 0x800000 0x0 0x200000>;
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};
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partition@0xa00000 {
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label = "u-boot-env";
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reg = <0x0 0xa00000 0x0 0x200000>;
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};
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partition@0xc00000 {
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label = "boot";
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reg = <0x0 0xc00000 0x0 0x4000000>;
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};
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partition@0x8c00000 {
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label = "system";
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reg = <0x0 0x4c00000 0x1 0xfb400000>;
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};
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};
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};
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};
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};
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&bch {
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status = "okay";
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};
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&mmc0 {
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bus-width = <4>;
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max-frequency = <50000000>;
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status = "okay";
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};
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&mmc1 {
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bus-width = <4>;
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max-frequency = <50000000>;
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status = "okay";
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};
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@ -12,4 +12,15 @@ config SOC_JZ4780
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help
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Support for Ingenic JZ4780 family SoCs.
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choice
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prompt "Board select"
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config TARGET_JZ4780_CI20
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bool "Creator CI20 Reference Board"
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select SOC_JZ4780
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endchoice
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source "board/imgtec/ci20/Kconfig"
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endmenu
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@ -0,0 +1,15 @@
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if TARGET_JZ4780_CI20
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config SYS_BOARD
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default "ci20"
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config SYS_VENDOR
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default "imgtec"
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config SYS_CONFIG_NAME
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default "ci20"
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config SYS_TEXT_BASE
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default 0x80000000
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endif
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@ -0,0 +1,6 @@
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Creator CI20 BOARD
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M: Ezequiel Garcia <ezequiel@collabora.com>
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S: Maintained
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F: board/imgtec/ci20/
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F: include/configs/ci20.h
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F: configs/ci20_mmc_defconfig
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@ -0,0 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0+
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obj-y := ci20.o
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@ -0,0 +1,10 @@
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CI20 U-Boot
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Installation to an SD card:
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Repartition your card with an MBR such that the first partition starts at an
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offset of no less than 270KB. Then install U-Boot SPL & the full U-Boot image
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to the card like so:
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dd if=spl/u-boot-spl.bin of=/dev/sdX obs=512 seek=1
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dd if=u-boot-dtb.img of=/dev/sdX obs=1K seek=14
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sync
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@ -0,0 +1,362 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* CI20 setup code
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*
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* Copyright (c) 2013 Imagination Technologies
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* Author: Paul Burton <paul.burton@imgtec.com>
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*/
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#include <common.h>
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#include <environment.h>
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#include <net.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <mach/jz4780.h>
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#include <mach/jz4780_dram.h>
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#include <mach/jz4780_gpio.h>
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struct ci20_otp {
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u32 serial_number;
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u32 date;
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u8 manufacturer[2];
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u8 mac[6];
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} __packed;
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static void ci20_mux_mmc(void)
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{
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void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
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/* setup MSC1 pins */
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writel(0x30f00000, gpio_regs + GPIO_PXINTC(4));
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writel(0x30f00000, gpio_regs + GPIO_PXMASKC(4));
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writel(0x30f00000, gpio_regs + GPIO_PXPAT1C(4));
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writel(0x30f00000, gpio_regs + GPIO_PXPAT0C(4));
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writel(0x30f00000, gpio_regs + GPIO_PXPENC(4));
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jz4780_clk_ungate_mmc();
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}
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#ifndef CONFIG_SPL_BUILD
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static void ci20_mux_eth(void)
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{
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void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
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#ifdef CONFIG_NAND
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/* setup pins (some already setup for NAND) */
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writel(0x04030000, gpio_regs + GPIO_PXINTC(0));
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writel(0x04030000, gpio_regs + GPIO_PXMASKC(0));
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writel(0x04030000, gpio_regs + GPIO_PXPAT1C(0));
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writel(0x04030000, gpio_regs + GPIO_PXPAT0C(0));
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writel(0x04030000, gpio_regs + GPIO_PXPENS(0));
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#else
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/* setup pins (as above +NAND CS +RD/WE +SDx +SAx) */
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writel(0x0dff00ff, gpio_regs + GPIO_PXINTC(0));
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writel(0x0dff00ff, gpio_regs + GPIO_PXMASKC(0));
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writel(0x0dff00ff, gpio_regs + GPIO_PXPAT1C(0));
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writel(0x0dff00ff, gpio_regs + GPIO_PXPAT0C(0));
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writel(0x0dff00ff, gpio_regs + GPIO_PXPENS(0));
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writel(0x00000003, gpio_regs + GPIO_PXINTC(1));
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writel(0x00000003, gpio_regs + GPIO_PXMASKC(1));
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writel(0x00000003, gpio_regs + GPIO_PXPAT1C(1));
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writel(0x00000003, gpio_regs + GPIO_PXPAT0C(1));
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writel(0x00000003, gpio_regs + GPIO_PXPENS(1));
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#endif
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}
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static void ci20_mux_jtag(void)
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{
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#ifdef CONFIG_JTAG
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void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
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/* enable JTAG */
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writel(3 << 30, gpio_regs + GPIO_PXINTC(0));
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writel(3 << 30, gpio_regs + GPIO_PXMASKC(0));
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writel(3 << 30, gpio_regs + GPIO_PXPAT1C(0));
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writel(3 << 30, gpio_regs + GPIO_PXPAT0C(0));
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#endif
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}
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static void ci20_mux_nand(void)
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{
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void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
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/* setup pins */
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writel(0x002c00ff, gpio_regs + GPIO_PXINTC(0));
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writel(0x002c00ff, gpio_regs + GPIO_PXMASKC(0));
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writel(0x002c00ff, gpio_regs + GPIO_PXPAT1C(0));
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writel(0x002c00ff, gpio_regs + GPIO_PXPAT0C(0));
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writel(0x002c00ff, gpio_regs + GPIO_PXPENS(0));
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writel(0x00000003, gpio_regs + GPIO_PXINTC(1));
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writel(0x00000003, gpio_regs + GPIO_PXMASKC(1));
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writel(0x00000003, gpio_regs + GPIO_PXPAT1C(1));
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writel(0x00000003, gpio_regs + GPIO_PXPAT0C(1));
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writel(0x00000003, gpio_regs + GPIO_PXPENS(1));
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/* FRB0_N */
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jz47xx_gpio_direction_input(JZ_GPIO(0, 20));
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writel(20, gpio_regs + GPIO_PXPENS(0));
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/* disable write protect */
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jz47xx_gpio_direction_output(JZ_GPIO(5, 22), 1);
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}
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static void ci20_mux_uart(void)
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{
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void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
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/* UART0 */
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writel(0x9, gpio_regs + GPIO_PXINTC(5));
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writel(0x9, gpio_regs + GPIO_PXMASKC(5));
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writel(0x9, gpio_regs + GPIO_PXPAT1C(5));
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writel(0x9, gpio_regs + GPIO_PXPAT0C(5));
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writel(0x9, gpio_regs + GPIO_PXPENC(5));
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jz4780_clk_ungate_uart(0);
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/* UART 1 and 2 */
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jz4780_clk_ungate_uart(1);
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jz4780_clk_ungate_uart(2);
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#ifndef CONFIG_JTAG
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/* UART3 */
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writel(1 << 12, gpio_regs + GPIO_PXINTC(3));
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writel(1 << 12, gpio_regs + GPIO_PXMASKS(3));
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writel(1 << 12, gpio_regs + GPIO_PXPAT1S(3));
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writel(1 << 12, gpio_regs + GPIO_PXPAT0C(3));
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writel(3 << 30, gpio_regs + GPIO_PXINTC(0));
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writel(3 << 30, gpio_regs + GPIO_PXMASKC(0));
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writel(3 << 30, gpio_regs + GPIO_PXPAT1C(0));
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writel(1 << 30, gpio_regs + GPIO_PXPAT0C(0));
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writel(1 << 31, gpio_regs + GPIO_PXPAT0S(0));
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jz4780_clk_ungate_uart(3);
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#endif
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/* UART4 */
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writel(0x100400, gpio_regs + GPIO_PXINTC(2));
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writel(0x100400, gpio_regs + GPIO_PXMASKC(2));
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writel(0x100400, gpio_regs + GPIO_PXPAT1S(2));
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writel(0x100400, gpio_regs + GPIO_PXPAT0C(2));
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writel(0x100400, gpio_regs + GPIO_PXPENC(2));
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jz4780_clk_ungate_uart(4);
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}
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int board_early_init_f(void)
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{
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ci20_mux_jtag();
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ci20_mux_uart();
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ci20_mux_eth();
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ci20_mux_mmc();
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ci20_mux_nand();
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/* SYS_POWER_IND high (LED blue, VBUS off) */
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jz47xx_gpio_direction_output(JZ_GPIO(5, 15), 0);
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/* LEDs off */
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jz47xx_gpio_direction_output(JZ_GPIO(2, 0), 0);
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jz47xx_gpio_direction_output(JZ_GPIO(2, 1), 0);
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jz47xx_gpio_direction_output(JZ_GPIO(2, 2), 0);
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jz47xx_gpio_direction_output(JZ_GPIO(2, 3), 0);
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return 0;
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}
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int misc_init_r(void)
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{
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const u32 efuse_clk = jz4780_clk_get_efuse_clk();
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struct ci20_otp otp;
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char manufacturer[3];
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/* Read the board OTP data */
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jz4780_efuse_init(efuse_clk);
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jz4780_efuse_read(0x18, 16, (u8 *)&otp);
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/* Set MAC address */
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if (!is_valid_ethaddr(otp.mac)) {
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/* no MAC assigned, generate one from the unique chip ID */
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jz4780_efuse_read(0x8, 4, &otp.mac[0]);
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jz4780_efuse_read(0x12, 2, &otp.mac[4]);
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otp.mac[0] = (otp.mac[0] | 0x02) & ~0x01;
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}
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eth_env_set_enetaddr("ethaddr", otp.mac);
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/* Put other board information into the environment */
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env_set_ulong("serial#", otp.serial_number);
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env_set_ulong("board_date", otp.date);
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manufacturer[0] = otp.manufacturer[0];
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manufacturer[1] = otp.manufacturer[1];
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manufacturer[2] = 0;
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env_set("board_mfr", manufacturer);
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return 0;
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}
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#ifdef CONFIG_DRIVER_DM9000
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int board_eth_init(bd_t *bis)
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{
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/* Enable clock */
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jz4780_clk_ungate_ethernet();
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/* Enable power (PB25) */
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jz47xx_gpio_direction_output(JZ_GPIO(1, 25), 1);
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/* Reset (PF12) */
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mdelay(10);
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jz47xx_gpio_direction_output(JZ_GPIO(5, 12), 0);
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mdelay(10);
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jz47xx_gpio_direction_output(JZ_GPIO(5, 12), 1);
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mdelay(10);
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return dm9000_initialize(bis);
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}
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#endif /* CONFIG_DRIVER_DM9000 */
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#endif
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static u8 ci20_revision(void)
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{
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void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
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int val;
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jz47xx_gpio_direction_input(JZ_GPIO(2, 18));
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jz47xx_gpio_direction_input(JZ_GPIO(2, 19));
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/* Enable pullups */
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writel(BIT(18) | BIT(19), gpio_regs + GPIO_PXPENC(2));
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/* Read PC18/19 for version */
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val = (!!jz47xx_gpio_get_value(JZ_GPIO(2, 18))) |
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((!!jz47xx_gpio_get_value(JZ_GPIO(2, 19))) << 1);
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if (val == 3) /* Rev 1 boards had no pulldowns - giving 3 */
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return 1;
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if (val == 1) /* Rev 2 boards pulldown port C bit 18 giving 1 */
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return 2;
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = sdram_size(0) + sdram_size(1);
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return 0;
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}
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/* U-Boot common routines */
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int checkboard(void)
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{
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printf("Board: Creator CI20 (rev.%d)\n", ci20_revision());
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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#if defined(CONFIG_SPL_MMC_SUPPORT)
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int board_mmc_init(bd_t *bd)
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{
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ci20_mux_mmc();
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return jz_mmc_init((void __iomem *)MSC0_BASE);
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}
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#endif
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static const struct jz4780_ddr_config K4B2G0846Q_48_config = {
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.timing = {
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(4 << DDRC_TIMING1_TRTP_BIT) | (13 << DDRC_TIMING1_TWTR_BIT) |
|
||||
(6 << DDRC_TIMING1_TWR_BIT) | (5 << DDRC_TIMING1_TWL_BIT),
|
||||
|
||||
(4 << DDRC_TIMING2_TCCD_BIT) | (15 << DDRC_TIMING2_TRAS_BIT) |
|
||||
(6 << DDRC_TIMING2_TRCD_BIT) | (6 << DDRC_TIMING2_TRL_BIT),
|
||||
|
||||
(4 << DDRC_TIMING3_ONUM) | (7 << DDRC_TIMING3_TCKSRE_BIT) |
|
||||
(6 << DDRC_TIMING3_TRP_BIT) | (4 << DDRC_TIMING3_TRRD_BIT) |
|
||||
(21 << DDRC_TIMING3_TRC_BIT),
|
||||
|
||||
(31 << DDRC_TIMING4_TRFC_BIT) | (1 << DDRC_TIMING4_TRWCOV_BIT) |
|
||||
(4 << DDRC_TIMING4_TCKE_BIT) | (9 << DDRC_TIMING4_TMINSR_BIT) |
|
||||
(8 << DDRC_TIMING4_TXP_BIT) | (3 << DDRC_TIMING4_TMRD_BIT),
|
||||
|
||||
(8 << DDRC_TIMING5_TRTW_BIT) | (4 << DDRC_TIMING5_TRDLAT_BIT) |
|
||||
(4 << DDRC_TIMING5_TWDLAT_BIT),
|
||||
|
||||
(25 << DDRC_TIMING6_TXSRD_BIT) | (12 << DDRC_TIMING6_TFAW_BIT) |
|
||||
(2 << DDRC_TIMING6_TCFGW_BIT) | (2 << DDRC_TIMING6_TCFGR_BIT),
|
||||
},
|
||||
|
||||
/* PHY */
|
||||
/* Mode Register 0 */
|
||||
.mr0 = 0x420,
|
||||
#ifdef SDRAM_DISABLE_DLL
|
||||
.mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
|
||||
#else
|
||||
.mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
|
||||
#endif
|
||||
|
||||
.ptr0 = 0x002000d4,
|
||||
.ptr1 = 0x02230d40,
|
||||
.ptr2 = 0x04013880,
|
||||
|
||||
.dtpr0 = 0x2a8f6690,
|
||||
.dtpr1 = 0x00400860,
|
||||
.dtpr2 = 0x10042a00,
|
||||
|
||||
.pullup = 0x0b,
|
||||
.pulldn = 0x0b,
|
||||
};
|
||||
|
||||
static const struct jz4780_ddr_config H5TQ2G83CFR_48_config = {
|
||||
.timing = {
|
||||
(4 << DDRC_TIMING1_TRTP_BIT) | (13 << DDRC_TIMING1_TWTR_BIT) |
|
||||
(6 << DDRC_TIMING1_TWR_BIT) | (5 << DDRC_TIMING1_TWL_BIT),
|
||||
|
||||
(4 << DDRC_TIMING2_TCCD_BIT) | (16 << DDRC_TIMING2_TRAS_BIT) |
|
||||
(6 << DDRC_TIMING2_TRCD_BIT) | (6 << DDRC_TIMING2_TRL_BIT),
|
||||
|
||||
(4 << DDRC_TIMING3_ONUM) | (7 << DDRC_TIMING3_TCKSRE_BIT) |
|
||||
(6 << DDRC_TIMING3_TRP_BIT) | (4 << DDRC_TIMING3_TRRD_BIT) |
|
||||
(22 << DDRC_TIMING3_TRC_BIT),
|
||||
|
||||
(42 << DDRC_TIMING4_TRFC_BIT) | (1 << DDRC_TIMING4_TRWCOV_BIT) |
|
||||
(4 << DDRC_TIMING4_TCKE_BIT) | (7 << DDRC_TIMING4_TMINSR_BIT) |
|
||||
(3 << DDRC_TIMING4_TXP_BIT) | (3 << DDRC_TIMING4_TMRD_BIT),
|
||||
|
||||
(8 << DDRC_TIMING5_TRTW_BIT) | (4 << DDRC_TIMING5_TRDLAT_BIT) |
|
||||
(4 << DDRC_TIMING5_TWDLAT_BIT),
|
||||
|
||||
(25 << DDRC_TIMING6_TXSRD_BIT) | (20 << DDRC_TIMING6_TFAW_BIT) |
|
||||
(2 << DDRC_TIMING6_TCFGW_BIT) | (2 << DDRC_TIMING6_TCFGR_BIT),
|
||||
},
|
||||
|
||||
/* PHY */
|
||||
/* Mode Register 0 */
|
||||
.mr0 = 0x420,
|
||||
#ifdef SDRAM_DISABLE_DLL
|
||||
.mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
|
||||
#else
|
||||
.mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
|
||||
#endif
|
||||
|
||||
.ptr0 = 0x002000d4,
|
||||
.ptr1 = 0x02d30d40,
|
||||
.ptr2 = 0x04013880,
|
||||
|
||||
.dtpr0 = 0x2c906690,
|
||||
.dtpr1 = 0x005608a0,
|
||||
.dtpr2 = 0x10042a00,
|
||||
|
||||
.pullup = 0x0e,
|
||||
.pulldn = 0x0e,
|
||||
};
|
||||
|
||||
#if (CONFIG_SYS_MHZ != 1200)
|
||||
#error No DDR configuration for CPU speed
|
||||
#endif
|
||||
|
||||
const struct jz4780_ddr_config *jz4780_get_ddr_config(void)
|
||||
{
|
||||
const int board_revision = ci20_revision();
|
||||
|
||||
if (board_revision == 2)
|
||||
return &K4B2G0846Q_48_config;
|
||||
else /* Fall back to H5TQ2G83CFR RAM */
|
||||
return &H5TQ2G83CFR_48_config;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
CONFIG_MIPS=y
|
||||
CONFIG_SPL_LDSCRIPT="arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds"
|
||||
CONFIG_SYS_TEXT_BASE=0x80010000
|
||||
CONFIG_SPL_GPIO_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_SPL_MMC_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_ARCH_JZ47XX=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_FIT=y
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_BOOTARGS="console=ttyS4,115200 rw rootwait root=/dev/mmcblk0p1"
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="ext4load mmc 0:1 0x88000000 /boot/uImage; bootm 0x88000000"
|
||||
CONFIG_MISC_INIT_R=y
|
||||
CONFIG_DISPLAY_CPUINFO=y
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
# CONFIG_SPL_BANNER_PRINT is not set
|
||||
# CONFIG_TPL_BANNER_PRINT is not set
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_DM=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_FAT=y
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
CONFIG_DEFAULT_DEVICE_TREE="ci20"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
# CONFIG_DM_WARN is not set
|
||||
# CONFIG_DM_DEVICE_REMOVE is not set
|
||||
CONFIG_JZ4780_EFUSE=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_BROKEN_CD=y
|
||||
CONFIG_DM_MMC=y
|
||||
# CONFIG_MMC_HW_PARTITIONING is not set
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS400_SUPPORT=y
|
||||
# CONFIG_MMC_VERBOSE is not set
|
||||
CONFIG_SPL_MMC_TINY=y
|
||||
CONFIG_JZ47XX_MMC=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_USE_TINY_PRINTF=y
|
||||
CONFIG_SPL_TINY_MEMSET=y
|
||||
CONFIG_LZO=y
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* CI20 configuration
|
||||
*
|
||||
* Copyright (c) 2013 Imagination Technologies
|
||||
* Author: Paul Burton <paul.burton@imgtec.com>
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_CI20_H__
|
||||
#define __CONFIG_CI20_H__
|
||||
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
|
||||
/* Ingenic JZ4780 clock configuration. */
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
#define CONFIG_SYS_MHZ 1200
|
||||
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
|
||||
|
||||
/* Memory configuration */
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
|
||||
#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
|
||||
#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x81000000
|
||||
#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x88000000
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
|
||||
/* NS16550-ish UARTs */
|
||||
#define CONFIG_SYS_NS16550_CLK 48000000
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
|
||||
|
||||
/* Ethernet: davicom DM9000 */
|
||||
#define CONFIG_DRIVER_DM9000 1
|
||||
#define CONFIG_DM9000_BASE 0xb6000000
|
||||
#define DM9000_IO CONFIG_DM9000_BASE
|
||||
#define DM9000_DATA (CONFIG_DM9000_BASE + 2)
|
||||
|
||||
/* Environment */
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
#define CONFIG_ENV_SIZE (32 << 10)
|
||||
#define CONFIG_ENV_OFFSET ((14 + 512) << 10)
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/* Command line configuration. */
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
|
||||
#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
/* Boot argument buffer size */
|
||||
#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
|
||||
|
||||
/* Miscellaneous configuration options */
|
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20)
|
||||
|
||||
/* SPL */
|
||||
#define CONFIG_SPL_STACK 0xf4008000 /* only max. 2KB spare! */
|
||||
|
||||
#define CONFIG_SPL_TEXT_BASE 0xf4000a00
|
||||
#define CONFIG_SPL_MAX_SIZE ((14 * 1024) - 0xa00)
|
||||
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0xf4004000
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x00002000 /* 512KB, arbitrary */
|
||||
|
||||
#define CONFIG_SPL_START_S_PATH "arch/mips/mach-jz47xx"
|
||||
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1c /* 14 KiB offset */
|
||||
|
||||
#endif /* __CONFIG_CI20_H__ */
|
||||
Loading…
Reference in New Issue