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arm: Move SYS_FSL_IFC_BANK_COUNT to Kconfig

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Move this option to Kconfig and clean up existing uses.
This option is also used by PowerPC SoCs.

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
York Sun 2016-10-04 14:45:54 -07:00
parent b4b60d06c6
commit 25af7dc193
3 changed files with 12 additions and 3 deletions
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5
arch/arm/cpu/armv7/ls102xa/Kconfig
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@ -23,4 +23,9 @@ config MAX_CPUS
config SYS_FSL_ERRATUM_A010315 config SYS_FSL_ERRATUM_A010315
bool "Workaround for PCIe erratum A010315" bool "Workaround for PCIe erratum A010315"
config SYS_FSL_IFC_BANK_COUNT
int "Maximum banks of Integrated flash controller"
depends on ARCH_LS1021A
default 8
endmenu endmenu

7
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View File

@ -50,4 +50,11 @@ config MAX_CPUS
cores, count the reserved ports. This will allocate enough memory cores, count the reserved ports. This will allocate enough memory
in spin table to properly handle all cores. in spin table to properly handle all cores.
config SYS_FSL_IFC_BANK_COUNT
int "Maximum banks of Integrated flash controller"
depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
default 4 if ARCH_LS1043A
default 4 if ARCH_LS1046A
default 8 if ARCH_LS2080A
endmenu endmenu

3
arch/arm/include/asm/arch-fsl-layerscape/config.h
View File

@ -30,7 +30,6 @@
#define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */ #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */
#ifdef CONFIG_LS2080A #ifdef CONFIG_LS2080A
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_NUM_DDR_CONTROLLERS 3 #define CONFIG_NUM_DDR_CONTROLLERS 3
#define CONFIG_SYS_FSL_HAS_DP_DDR /* Runtime check to confirm */ #define CONFIG_SYS_FSL_HAS_DP_DDR /* Runtime check to confirm */
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
@ -174,7 +173,6 @@
#define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 7 #define CONFIG_SYS_NUM_FM1_DTSEC 7
#define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_SYS_FSL_DDR_BE #define CONFIG_SYS_FSL_DDR_BE
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
@ -213,7 +211,6 @@
#define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 8 #define CONFIG_SYS_NUM_FM1_DTSEC 8
#define CONFIG_SYS_NUM_FM1_10GEC 2 #define CONFIG_SYS_NUM_FM1_10GEC 2
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_SYS_FSL_DDR_BE #define CONFIG_SYS_FSL_DDR_BE
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE