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mips: bmips: add bcm6345-gpio driver support for BCM6358
This SoC has one gpio bank divided into two 32 bit registers, with a total of 40 GPIOs. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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@ -73,6 +73,25 @@
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mask = <0x1>;
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};
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gpio1: gpio-controller@fffe0080 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0xfffe0080 0x4>, <0xfffe0088 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <8>;
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status = "disabled";
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};
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gpio0: gpio-controller@fffe0084 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0xfffe0084 0x4>, <0xfffe008c 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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uart0: serial@fffe0100 {
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compatible = "brcm,bcm6345-uart";
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reg = <0xfffe0100 0x18>;
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