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powerpc/corenet: CPC1 speculation disable
In PBL RAMBOOT(SPI/SD/NAND boot) mode, CPC1 used as SRAM, should disable CPC1 speculation and keep it till relocation. Otherwise, speculation transactions will go to DDR controller, it will cause problem. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
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@ -886,7 +886,11 @@ delete_ccsr_l2_tlb:
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erratum_set_dcsr 0xb0008 0x00900000
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erratum_set_dcsr 0xb0e40 0xe00a0000
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erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
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#ifdef CONFIG_RAMBOOT_PBL
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erratum_set_ccsr 0x10f00 0x495e5000
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#else
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erratum_set_ccsr 0x10f00 0x415e5000
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#endif
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erratum_set_ccsr 0x11f00 0x415e5000
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/* Make temp mapping uncacheable again, if it was initially */
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