brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-06-09 23:36:03 +09:00
Code Issues Projects Releases Wiki Activity

x86: Add a common function to set CPU thermal target

Browse Source 
This code appears in a few places, so move it to a common file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass 2019-09-25 08:56:36 -06:00 committed by Bin Meng
parent e2493a7f5a
commit 246ac08b03
4 changed files with 37 additions and 41 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
arch/x86/cpu/broadwell/cpu_full.c
View File

@ -495,24 +495,6 @@ static void configure_misc(void)
msr_write(MSR_IA32_PACKAGE_THERM_INTERRUPT, msr);
}
static void configure_thermal_target(struct udevice *dev)
{
int tcc_offset;
msr_t msr;
tcc_offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"intel,tcc-offset", 0);
/* Set TCC activaiton offset if supported */
msr = msr_read(MSR_PLATFORM_INFO);
if ((msr.lo & (1 << 30)) && tcc_offset) {
msr = msr_read(MSR_TEMPERATURE_TARGET);
msr.lo &= ~(0xf << 24); /* Bits 27:24 */
msr.lo |= (tcc_offset & 0xf) << 24;
msr_write(MSR_TEMPERATURE_TARGET, msr);
}
}
static void configure_dca_cap(void)
{
struct cpuid_result cpuid_regs;
@ -562,7 +544,7 @@ static void cpu_core_init(struct udevice *dev)
configure_misc();
/* Thermal throttle activation offset */
configure_thermal_target(dev);
cpu_configure_thermal_target(dev);
/* Enable Direct Cache Access */
configure_dca_cap();

22
arch/x86/cpu/intel_common/cpu.c
View File

@ -123,3 +123,25 @@ int cpu_intel_get_info(struct cpu_info *info, int bclk)
return 0;
}
int cpu_configure_thermal_target(struct udevice *dev)
{
u32 tcc_offset;
msr_t msr;
int ret;
ret = dev_read_u32(dev, "tcc-offset", &tcc_offset);
if (!ret)
return -ENOENT;
/* Set TCC activaiton offset if supported */
msr = msr_read(MSR_PLATFORM_INFO);
if (msr.lo & (1 << 30)) {
msr = msr_read(MSR_TEMPERATURE_TARGET);
msr.lo &= ~(0xf << 24); /* Bits 27:24 */
msr.lo |= (tcc_offset & 0xf) << 24;
msr_write(MSR_TEMPERATURE_TARGET, msr);
}
return 0;
}

25
arch/x86/cpu/ivybridge/model_206ax.c
View File

@ -283,26 +283,6 @@ static void configure_c_states(void)
msr_write(MSR_PP1_CURRENT_CONFIG, msr);
}
static int configure_thermal_target(struct udevice *dev)
{
int tcc_offset;
msr_t msr;
tcc_offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"tcc-offset", 0);
/* Set TCC activaiton offset if supported */
msr = msr_read(MSR_PLATFORM_INFO);
if ((msr.lo & (1 << 30)) && tcc_offset) {
msr = msr_read(MSR_TEMPERATURE_TARGET);
msr.lo &= ~(0xf << 24); /* Bits 27:24 */
msr.lo |= (tcc_offset & 0xf) << 24;
msr_write(MSR_TEMPERATURE_TARGET, msr);
}
return 0;
}
static void configure_misc(void)
{
msr_t msr;
@ -414,10 +394,11 @@ static int model_206ax_init(struct udevice *dev)
configure_misc();
/* Thermal throttle activation offset */
ret = configure_thermal_target(dev);
ret = cpu_configure_thermal_target(dev);
if (ret) {
debug("Cannot set thermal target\n");
return ret;
if (ret != -ENOENT)
return ret;
}
/* Enable Direct Cache Access */

11
arch/x86/include/asm/cpu_common.h
View File

@ -45,4 +45,15 @@ int cpu_set_flex_ratio_to_tdp_nominal(void);
*/
int cpu_intel_get_info(struct cpu_info *info, int bclk_mz);
/**
* cpu_configure_thermal_target() - Set the thermal target for a CPU
*
* This looks up the tcc-offset property and uses it to set the
* MSR_TEMPERATURE_TARGET value.
*
* @dev: CPU device
* @return 0 if OK, -ENOENT if no target is given in device tree
*/
int cpu_configure_thermal_target(struct udevice *dev);
#endif