From 186879cdb22fd7569dae7f425711bed82a707bb4 Mon Sep 17 00:00:00 2001 From: Trac Hoang Date: Thu, 20 Aug 2020 20:41:04 +0530 Subject: [PATCH 01/12] cmd: broadcom: add bnxt boot command Chimp is a core in Broadcom netxtream controller (bnxt). Add command to load binary to chimp and boot bnxt. Signed-off-by: Trac Hoang Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- cmd/broadcom/Makefile | 4 ++++ cmd/broadcom/chimp_boot.c | 37 +++++++++++++++++++++++++++++++++++++ include/broadcom/chimp.h | 6 ++++++ 3 files changed, 47 insertions(+) create mode 100644 cmd/broadcom/Makefile create mode 100644 cmd/broadcom/chimp_boot.c diff --git a/cmd/broadcom/Makefile b/cmd/broadcom/Makefile new file mode 100644 index 0000000000..22ccf2f334 --- /dev/null +++ b/cmd/broadcom/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright 2020 Broadcom + +obj-y += chimp_boot.o diff --git a/cmd/broadcom/chimp_boot.c b/cmd/broadcom/chimp_boot.c new file mode 100644 index 0000000000..16f2b612c4 --- /dev/null +++ b/cmd/broadcom/chimp_boot.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 Broadcom + */ + +#include +#include +#include + +static int do_chimp_fastboot_secure(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + u32 health = 0; + + if (chimp_health_status_optee(&health)) { + pr_err("Chimp health command fail\n"); + return CMD_RET_FAILURE; + } + + if (health == BCM_CHIMP_RUNNIG_GOOD) { + printf("skip fastboot...\n"); + return CMD_RET_SUCCESS; + } + + if (chimp_fastboot_optee()) { + pr_err("Failed to load secure ChiMP image\n"); + return CMD_RET_FAILURE; + } + + return CMD_RET_SUCCESS; +} + +U_BOOT_CMD + (chimp_ld_secure, 1, 0, do_chimp_fastboot_secure, + "Invoke chimp fw load via optee", + "chimp_ld_secure\n" +); diff --git a/include/broadcom/chimp.h b/include/broadcom/chimp.h index 7f64152913..73bb1c21e9 100644 --- a/include/broadcom/chimp.h +++ b/include/broadcom/chimp.h @@ -9,6 +9,12 @@ #include +/* + * Chimp binary has health status like initialization complete, + * crash or running fine + */ +#define BCM_CHIMP_RUNNIG_GOOD 0x8000 + /** * chimp_fastboot_optee() - api to load bnxt firmware * From 70bf26332f3d07382730a9cae93219a3efa0fbe2 Mon Sep 17 00:00:00 2001 From: Vikas Gupta Date: Thu, 20 Aug 2020 20:41:05 +0530 Subject: [PATCH 02/12] cmd: broadcom: add cmd to update bnxt image env variables Add command to update the environmental variables which are used to read the data from QSPI offsets and load the binaries to bnxt. Signed-off-by: Vikas Gupta Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- cmd/broadcom/Makefile | 1 + cmd/broadcom/nitro_image_load.c | 125 ++++++++++++++++++++++++++++++++ 2 files changed, 126 insertions(+) create mode 100644 cmd/broadcom/nitro_image_load.c diff --git a/cmd/broadcom/Makefile b/cmd/broadcom/Makefile index 22ccf2f334..6cdece1a3a 100644 --- a/cmd/broadcom/Makefile +++ b/cmd/broadcom/Makefile @@ -2,3 +2,4 @@ # Copyright 2020 Broadcom obj-y += chimp_boot.o +obj-y += nitro_image_load.o diff --git a/cmd/broadcom/nitro_image_load.c b/cmd/broadcom/nitro_image_load.c new file mode 100644 index 0000000000..4a36b300c4 --- /dev/null +++ b/cmd/broadcom/nitro_image_load.c @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 Broadcom + */ + +#include +#include + +#define FW_IMAGE_SIG 0xff123456 +#define CFG_IMAGE_SIG 0xcf54321a + +/* + * structure for bin file + * signature: fw itb file + * size: fw itb file + * signature: NS3 config file + * size: NS3 config file + * Data: fw itb file + * ............................ + * ............................ + * Data: NS3 config file + * ............................ + * ............................ + */ + +static struct img_header { + u32 bin_sig; + u32 bin_size; + u32 cfg1_sig; + u32 cfg1_size; +} *img_header; + +static int env_set_val(const char *varname, ulong val) +{ + int ret; + + ret = env_set_hex(varname, val); + if (ret) + pr_err("Failed to %s env var\n", varname); + + return ret; +} + +static int do_spi_images_addr(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + uintptr_t images_load_addr; + uintptr_t spi_load_addr; + u32 len; + u32 spi_data_offset = sizeof(struct img_header); + + if (argc != 3) + return CMD_RET_USAGE; + + /* convert command parameter to fastboot address (base 16), i.e. hex */ + images_load_addr = simple_strtoul(argv[1], NULL, 16); + if (!images_load_addr) { + pr_err("Invalid load address\n"); + return CMD_RET_USAGE; + } + + spi_load_addr = simple_strtoul(argv[2], NULL, 16); + if (!spi_load_addr) { + pr_err("Invalid spi load address\n"); + return CMD_RET_USAGE; + } + + img_header = (struct img_header *)images_load_addr; + + if (img_header->bin_sig != FW_IMAGE_SIG) { + pr_err("Invalid Nitro bin file\n"); + goto error; + } + + if (env_set_val("spi_nitro_fw_itb_start_addr", 0)) + goto error; + + if (env_set_val("spi_nitro_fw_itb_len", 0)) + goto error; + + if (env_set_val("spi_nitro_fw_ns3_cfg_start_addr", 0)) + goto error; + + if (env_set_val("spi_nitro_fw_ns3_cfg_len", 0)) + goto error; + + len = img_header->bin_size; + + if (env_set_val("spi_nitro_fw_itb_start_addr", + (spi_load_addr + spi_data_offset))) + goto error; + + if (env_set_val("spi_nitro_fw_itb_len", img_header->bin_size)) + goto error; + + spi_data_offset += len; + + if (img_header->cfg1_sig == CFG_IMAGE_SIG) { + len = img_header->cfg1_size; + + if (env_set_val("spi_nitro_fw_ns3_cfg_start_addr", + (spi_load_addr + spi_data_offset))) + goto error; + + if (env_set_val("spi_nitro_fw_ns3_cfg_len", len)) + goto error; + + spi_data_offset += len; + } + + /* disable secure boot */ + if (env_set_val("nitro_fastboot_secure", 0)) + goto error; + + return CMD_RET_SUCCESS; + +error: + return CMD_RET_FAILURE; +} + +U_BOOT_CMD + (spi_nitro_images_addr, 3, 1, do_spi_images_addr, + "Load the bnxt bin header and sets envs ", + "spi_nitro_images_addr \n" +); From a09ca687e7719ef0767f3febb8980725da800eb8 Mon Sep 17 00:00:00 2001 From: Bharat Kumar Reddy Gooty Date: Thu, 20 Aug 2020 20:41:06 +0530 Subject: [PATCH 03/12] cmd: broadcom: add command for chimp handshake Add command for chimp handshake. Handshake is used to know chimp is loaded and booted successfully. Signed-off-by: Bharat Kumar Reddy Gooty Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- cmd/broadcom/Makefile | 1 + cmd/broadcom/chimp_handshake.c | 33 +++++++++++++++++++++++++++++++++ include/broadcom/chimp.h | 6 ++++++ 3 files changed, 40 insertions(+) create mode 100644 cmd/broadcom/chimp_handshake.c diff --git a/cmd/broadcom/Makefile b/cmd/broadcom/Makefile index 6cdece1a3a..62268d98d0 100644 --- a/cmd/broadcom/Makefile +++ b/cmd/broadcom/Makefile @@ -3,3 +3,4 @@ obj-y += chimp_boot.o obj-y += nitro_image_load.o +obj-y += chimp_handshake.o diff --git a/cmd/broadcom/chimp_handshake.c b/cmd/broadcom/chimp_handshake.c new file mode 100644 index 0000000000..a90a73a6d7 --- /dev/null +++ b/cmd/broadcom/chimp_handshake.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 Broadcom + */ + +#include +#include +#include + +/* This command should be called after loading the nitro binaries */ +static int do_chimp_hs(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + int ret = CMD_RET_USAGE; + u32 hstatus; + + /* Returns 1, if handshake call is success */ + if (chimp_handshake_status_optee(0, &hstatus)) + ret = CMD_RET_SUCCESS; + + if (hstatus == CHIMP_HANDSHAKE_SUCCESS) + printf("ChiMP Handshake successful\n"); + else + printf("ERROR: ChiMP Handshake status 0x%x\n", hstatus); + + return ret; +} + +U_BOOT_CMD + (chimp_hs, 1, 1, do_chimp_hs, + "Verify the Chimp handshake", + "chimp_hs\n" +); diff --git a/include/broadcom/chimp.h b/include/broadcom/chimp.h index 73bb1c21e9..738f73eefd 100644 --- a/include/broadcom/chimp.h +++ b/include/broadcom/chimp.h @@ -15,6 +15,12 @@ */ #define BCM_CHIMP_RUNNIG_GOOD 0x8000 +enum { + CHIMP_HANDSHAKE_SUCCESS = 0, + CHIMP_HANDSHAKE_WAIT_ERROR, + CHIMP_HANDSHAKE_WAIT_TIMEOUT, +}; + /** * chimp_fastboot_optee() - api to load bnxt firmware * From ff6a87560e06ba03653fe682fbad3a48b4b664d4 Mon Sep 17 00:00:00 2001 From: Vladimir Olovyannikov Date: Thu, 20 Aug 2020 20:41:07 +0530 Subject: [PATCH 04/12] board: ns3: kconfig: extend board kconfig with specific commands Extend Kconfig for the board with board-specific commands selection. Signed-off-by: Vladimir Olovyannikov Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- board/broadcom/bcmns3/Kconfig | 7 +++++++ cmd/Makefile | 2 ++ 2 files changed, 9 insertions(+) diff --git a/board/broadcom/bcmns3/Kconfig b/board/broadcom/bcmns3/Kconfig index 8ce21f980d..cb73f98eae 100644 --- a/board/broadcom/bcmns3/Kconfig +++ b/board/broadcom/bcmns3/Kconfig @@ -12,4 +12,11 @@ config SYS_SOC config SYS_CONFIG_NAME default "bcm_ns3" +config CMD_BCM_EXT_UTILS + bool "Enable Broadcom-specific U-Boot commands" + default y + help + Enable Broadcom specific U-Boot commands such as error log setup + command or any other commands specific to NS3 platform. + endif diff --git a/cmd/Makefile b/cmd/Makefile index 3a9c9747c9..c7a08ed109 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -197,6 +197,8 @@ obj-$(CONFIG_$(SPL_)CMD_TLV_EEPROM) += tlv_eeprom.o # core command obj-y += nvedit.o +obj-$(CONFIG_CMD_BCM_EXT_UTILS) += broadcom/ + obj-$(CONFIG_TI_COMMON_CMD_OPTIONS) += ti/ filechk_data_gz = (echo "static const char data_gz[] ="; cat $< | scripts/bin2c; echo ";") From 975d2a6980ac12ca28c97328a6d900241f0e87dc Mon Sep 17 00:00:00 2001 From: Rayagonda Kokatanur Date: Thu, 20 Aug 2020 20:41:08 +0530 Subject: [PATCH 05/12] MAINTAINERS: update maintainers file for new files Update MAINTAINERS file for new files. Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- MAINTAINERS | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 332112f6fd..73e728871b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1005,6 +1005,10 @@ F: arch/arm/dts/ns3-board.dts F: arch/arm/dts/ns3.dtsi F: arch/arm/cpu/armv8/bcmns3 F: arch/arm/include/asm/arch-bcmns3/ +F: cmd/broadcom/Makefile +F: cmd/broadcom/chimp_boot.c +F: cmd/broadcom/nitro_image_load.c +F: cmd/broadcom/chimp_handshake.c TDA19988 HDMI ENCODER M: Liviu Dudau From af071935d2c354f2250542f35e3178dd2660bfe1 Mon Sep 17 00:00:00 2001 From: Rayagonda Kokatanur Date: Tue, 25 Aug 2020 23:16:37 +0530 Subject: [PATCH 06/12] board: ns3: check bnxt chimp handshake status Chimp is a core in Broadcom netxtream controller (bnxt). Add support to check bnxt's chimp component status. Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- board/broadcom/bcmns3/ns3.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c index 0357cd0e32..10ae344a06 100644 --- a/board/broadcom/bcmns3/ns3.c +++ b/board/broadcom/bcmns3/ns3.c @@ -12,6 +12,7 @@ #include #include #include +#include /* Default reset-level = 3 and strap-val = 0 */ #define L3_RESET 30 @@ -210,8 +211,24 @@ void reset_cpu(ulong level) #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *fdt, struct bd_info *bd) { + u32 chimp_hs = CHIMP_HANDSHAKE_WAIT_TIMEOUT; + gic_lpi_tables_init(); + /* + * Check for chimp handshake status. + * Zero timeout value will actually fall to default timeout. + * + * System boot is independent of chimp handshake. + * chimp handshake failure is not a catastrophic error. + * Hence continue booting if chimp handshake fails. + */ + chimp_handshake_status_optee(0, &chimp_hs); + if (chimp_hs == CHIMP_HANDSHAKE_SUCCESS) + printf("ChiMP handshake successful\n"); + else + printf("ERROR: ChiMP handshake status 0x%x\n", chimp_hs); + return mem_info_parse_fixup(fdt); } #endif /* CONFIG_OF_BOARD_SETUP */ From 15b87feb2b7923ef679e9da3f956e7a836fbaa40 Mon Sep 17 00:00:00 2001 From: Ryan Chen Date: Mon, 31 Aug 2020 14:03:03 +0800 Subject: [PATCH 07/12] cosmetic: aspeed: ast2500: Rename clock header MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename the ast2500-scu.h to aspeed-clock.h. Signed-off-by: Ryan Chen Reviewed-by: Chia-Wei, Wang Reviewed-by: Cédric Le Goater --- arch/arm/dts/ast2500-u-boot.dtsi | 2 +- arch/arm/mach-aspeed/ast2500/sdram_ast2500.c | 2 +- drivers/clk/aspeed/clk_ast2500.c | 2 +- include/dt-bindings/clock/{ast2500-scu.h => aspeed-clock.h} | 0 4 files changed, 3 insertions(+), 3 deletions(-) rename include/dt-bindings/clock/{ast2500-scu.h => aspeed-clock.h} (100%) diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi index 8ac4215745..3b119e4ace 100644 --- a/arch/arm/dts/ast2500-u-boot.dtsi +++ b/arch/arm/dts/ast2500-u-boot.dtsi @@ -1,4 +1,4 @@ -#include +#include #include #include "ast2500.dtsi" diff --git a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c index a3adaa8a99..8536a70a19 100644 --- a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c +++ b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include /* These configuration parameters are taken from Aspeed SDK */ #define DDR4_MR46_MODE 0x08000000 diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c index d1940f1884..392fe76b27 100644 --- a/drivers/clk/aspeed/clk_ast2500.c +++ b/drivers/clk/aspeed/clk_ast2500.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include #include diff --git a/include/dt-bindings/clock/ast2500-scu.h b/include/dt-bindings/clock/aspeed-clock.h similarity index 100% rename from include/dt-bindings/clock/ast2500-scu.h rename to include/dt-bindings/clock/aspeed-clock.h From c39c9a94cba01d9fbbe359a8922d2ae85061a4e1 Mon Sep 17 00:00:00 2001 From: Ryan Chen Date: Mon, 31 Aug 2020 14:03:04 +0800 Subject: [PATCH 08/12] clock:aspeed: Sync with Linux kernel clock header define v2: modify title description aspeed:clock -> clock:aspeed Use kernel include/dt-bindings/clock/aspeed-clock.h define for clock driver. Signed-off-by: Ryan Chen Reviewed-by: Chia-Wei, Wang --- arch/arm/dts/ast2500-u-boot.dtsi | 20 +++---- drivers/clk/aspeed/clk_ast2500.c | 38 +++++++------ include/dt-bindings/clock/aspeed-clock.h | 68 ++++++++++++++---------- 3 files changed, 68 insertions(+), 58 deletions(-) diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi index 3b119e4ace..29b08f16ac 100644 --- a/arch/arm/dts/ast2500-u-boot.dtsi +++ b/arch/arm/dts/ast2500-u-boot.dtsi @@ -25,7 +25,7 @@ reg = <0x1e6e0000 0x174 0x1e6e0200 0x1d4 >; #reset-cells = <1>; - clocks = <&scu PLL_MPLL>; + clocks = <&scu ASPEED_CLK_MPLL>; resets = <&rst AST_RESET_SDRAM>; }; @@ -39,7 +39,7 @@ compatible = "aspeed,ast2500-sdhci"; reg = <0x1e740100>; #reset-cells = <1>; - clocks = <&scu BCLK_SDCLK>; + clocks = <&scu ASPEED_CLK_SDIO>; resets = <&rst AST_RESET_SDIO>; }; @@ -47,7 +47,7 @@ compatible = "aspeed,ast2500-sdhci"; reg = <0x1e740200>; #reset-cells = <1>; - clocks = <&scu BCLK_SDCLK>; + clocks = <&scu ASPEED_CLK_SDIO>; resets = <&rst AST_RESET_SDIO>; }; }; @@ -56,23 +56,23 @@ }; &uart1 { - clocks = <&scu PCLK_UART1>; + clocks = <&scu ASPEED_CLK_GATE_UART1CLK>; }; &uart2 { - clocks = <&scu PCLK_UART2>; + clocks = <&scu ASPEED_CLK_GATE_UART2CLK>; }; &uart3 { - clocks = <&scu PCLK_UART3>; + clocks = <&scu ASPEED_CLK_GATE_UART3CLK>; }; &uart4 { - clocks = <&scu PCLK_UART4>; + clocks = <&scu ASPEED_CLK_GATE_UART4CLK>; }; &uart5 { - clocks = <&scu PCLK_UART5>; + clocks = <&scu ASPEED_CLK_GATE_UART5CLK>; }; &timer { @@ -80,9 +80,9 @@ }; &mac0 { - clocks = <&scu PCLK_MAC1>, <&scu PLL_D2PLL>; + clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>; }; &mac1 { - clocks = <&scu PCLK_MAC2>, <&scu PLL_D2PLL>; + clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>; }; diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c index 392fe76b27..aab7d14deb 100644 --- a/drivers/clk/aspeed/clk_ast2500.c +++ b/drivers/clk/aspeed/clk_ast2500.c @@ -122,8 +122,7 @@ static ulong ast2500_clk_get_rate(struct clk *clk) ulong rate; switch (clk->id) { - case PLL_HPLL: - case ARMCLK: + case ASPEED_CLK_HPLL: /* * This ignores dynamic/static slowdown of ARMCLK and may * be inaccurate. @@ -131,11 +130,11 @@ static ulong ast2500_clk_get_rate(struct clk *clk) rate = ast2500_get_hpll_rate(clkin, readl(&priv->scu->h_pll_param)); break; - case MCLK_DDR: + case ASPEED_CLK_MPLL: rate = ast2500_get_mpll_rate(clkin, readl(&priv->scu->m_pll_param)); break; - case BCLK_PCLK: + case ASPEED_CLK_APB: { ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1) & SCU_PCLK_DIV_MASK) @@ -146,7 +145,7 @@ static ulong ast2500_clk_get_rate(struct clk *clk) rate = rate / apb_div; } break; - case BCLK_SDCLK: + case ASPEED_CLK_SDIO: { ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1) & SCU_SDCLK_DIV_MASK) @@ -157,19 +156,19 @@ static ulong ast2500_clk_get_rate(struct clk *clk) rate = rate / apb_div; } break; - case PCLK_UART1: + case ASPEED_CLK_GATE_UART1CLK: rate = ast2500_get_uart_clk_rate(priv->scu, 1); break; - case PCLK_UART2: + case ASPEED_CLK_GATE_UART2CLK: rate = ast2500_get_uart_clk_rate(priv->scu, 2); break; - case PCLK_UART3: + case ASPEED_CLK_GATE_UART3CLK: rate = ast2500_get_uart_clk_rate(priv->scu, 3); break; - case PCLK_UART4: + case ASPEED_CLK_GATE_UART4CLK: rate = ast2500_get_uart_clk_rate(priv->scu, 4); break; - case PCLK_UART5: + case ASPEED_CLK_GATE_UART5CLK: rate = ast2500_get_uart_clk_rate(priv->scu, 5); break; default: @@ -431,11 +430,10 @@ static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate) ulong new_rate; switch (clk->id) { - case PLL_MPLL: - case MCLK_DDR: + case ASPEED_CLK_MPLL: new_rate = ast2500_configure_ddr(priv->scu, rate); break; - case PLL_D2PLL: + case ASPEED_CLK_D2PLL: new_rate = ast2500_configure_d2pll(priv->scu, rate); break; default: @@ -450,7 +448,7 @@ static int ast2500_clk_enable(struct clk *clk) struct ast2500_clk_priv *priv = dev_get_priv(clk->dev); switch (clk->id) { - case BCLK_SDCLK: + case ASPEED_CLK_SDIO: if (readl(&priv->scu->clk_stop_ctrl1) & SCU_CLKSTOP_SDCLK) { ast_scu_unlock(priv->scu); @@ -471,13 +469,13 @@ static int ast2500_clk_enable(struct clk *clk) * configured based on whether RGMII or RMII mode has been selected * through hardware strapping. */ - case PCLK_MAC1: + case ASPEED_CLK_GATE_MAC1CLK: ast2500_configure_mac(priv->scu, 1); break; - case PCLK_MAC2: + case ASPEED_CLK_GATE_MAC2CLK: ast2500_configure_mac(priv->scu, 2); break; - case PLL_D2PLL: + case ASPEED_CLK_D2PLL: ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE); break; default: @@ -497,9 +495,9 @@ static int ast2500_clk_ofdata_to_platdata(struct udevice *dev) { struct ast2500_clk_priv *priv = dev_get_priv(dev); - priv->scu = dev_read_addr_ptr(dev); - if (!priv->scu) - return -EINVAL; + priv->scu = devfdt_get_addr_ptr(dev); + if (IS_ERR(priv->scu)) + return PTR_ERR(priv->scu); return 0; } diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h index 4803abe9f6..e6599deeb9 100644 --- a/include/dt-bindings/clock/aspeed-clock.h +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -1,30 +1,42 @@ /* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 Google Inc. - */ -/* Core Clocks */ -#define PLL_HPLL 1 -#define PLL_DPLL 2 -#define PLL_D2PLL 3 -#define PLL_MPLL 4 -#define ARMCLK 5 - - -/* Bus Clocks, derived from core clocks */ -#define BCLK_PCLK 101 -#define BCLK_LHCLK 102 -#define BCLK_MACCLK 103 -#define BCLK_SDCLK 104 -#define BCLK_ARMCLK 105 - -#define MCLK_DDR 201 - -/* Special clocks */ -#define PCLK_UART1 501 -#define PCLK_UART2 502 -#define PCLK_UART3 503 -#define PCLK_UART4 504 -#define PCLK_UART5 505 -#define PCLK_MAC1 506 -#define PCLK_MAC2 507 +#define ASPEED_CLK_GATE_ECLK 0 +#define ASPEED_CLK_GATE_GCLK 1 +#define ASPEED_CLK_GATE_MCLK 2 +#define ASPEED_CLK_GATE_VCLK 3 +#define ASPEED_CLK_GATE_BCLK 4 +#define ASPEED_CLK_GATE_DCLK 5 +#define ASPEED_CLK_GATE_REFCLK 6 +#define ASPEED_CLK_GATE_USBPORT2CLK 7 +#define ASPEED_CLK_GATE_LCLK 8 +#define ASPEED_CLK_GATE_USBUHCICLK 9 +#define ASPEED_CLK_GATE_D1CLK 10 +#define ASPEED_CLK_GATE_YCLK 11 +#define ASPEED_CLK_GATE_USBPORT1CLK 12 +#define ASPEED_CLK_GATE_UART1CLK 13 +#define ASPEED_CLK_GATE_UART2CLK 14 +#define ASPEED_CLK_GATE_UART5CLK 15 +#define ASPEED_CLK_GATE_ESPICLK 16 +#define ASPEED_CLK_GATE_MAC1CLK 17 +#define ASPEED_CLK_GATE_MAC2CLK 18 +#define ASPEED_CLK_GATE_RSACLK 19 +#define ASPEED_CLK_GATE_UART3CLK 20 +#define ASPEED_CLK_GATE_UART4CLK 21 +#define ASPEED_CLK_GATE_SDCLK 22 +#define ASPEED_CLK_GATE_LHCCLK 23 +#define ASPEED_CLK_HPLL 24 +#define ASPEED_CLK_AHB 25 +#define ASPEED_CLK_APB 26 +#define ASPEED_CLK_UART 27 +#define ASPEED_CLK_SDIO 28 +#define ASPEED_CLK_ECLK 29 +#define ASPEED_CLK_ECLK_MUX 30 +#define ASPEED_CLK_LHCLK 31 +#define ASPEED_CLK_MAC 32 +#define ASPEED_CLK_BCLK 33 +#define ASPEED_CLK_MPLL 34 +#define ASPEED_CLK_24M 35 +#define ASPEED_CLK_MAC1RCLK 36 +#define ASPEED_CLK_MAC2RCLK 37 +#define ASPEED_CLK_DPLL 38 +#define ASPEED_CLK_D2PLL 39 From 654ae299ec509084c22e646ae269e1baa2583793 Mon Sep 17 00:00:00 2001 From: Ryan Chen Date: Mon, 31 Aug 2020 14:03:05 +0800 Subject: [PATCH 09/12] cosmetic: aspeed: Modify for SPDX-License Modify SPDX-License for furture patch warning Signed-off-by: Ryan Chen Reviewed-by: Chia-Wei, Wang --- arch/arm/dts/ast2500-u-boot.dtsi | 1 + include/dt-bindings/clock/aspeed-clock.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi index 29b08f16ac..51a5244766 100644 --- a/arch/arm/dts/ast2500-u-boot.dtsi +++ b/arch/arm/dts/ast2500-u-boot.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 #include #include diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h index e6599deeb9..a1aa8c07ce 100644 --- a/include/dt-bindings/clock/aspeed-clock.h +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +// SPDX-License-Identifier: GPL-2.0 #define ASPEED_CLK_GATE_ECLK 0 #define ASPEED_CLK_GATE_GCLK 1 From a5fc58734fbc8b6f61b7716df3367d4607c168c4 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 1 Sep 2020 19:22:54 +0200 Subject: [PATCH 10/12] dt-bindings: clock: import Qualcomm IPQ4019 bindings Import Qualcomm IPQ4019 GCC bindings from Linux. This will enable using bindings instead of raw clock numbers both in the driver and DTS like Linux does. Signed-off-by: Robert Marko Cc: Luka Perkov --- MAINTAINERS | 1 + include/dt-bindings/clock/qcom,ipq4019-gcc.h | 96 ++++++++++++++++++++ 2 files changed, 97 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,ipq4019-gcc.h diff --git a/MAINTAINERS b/MAINTAINERS index 73e728871b..80e6e54e25 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -237,6 +237,7 @@ M: Luka Kovacic M: Luka Perkov S: Maintained F: arch/arm/mach-ipq40xx/ +F: include/dt-bindings/clock/qcom,ipq4019-gcc.h ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K M: Stefan Roese diff --git a/include/dt-bindings/clock/qcom,ipq4019-gcc.h b/include/dt-bindings/clock/qcom,ipq4019-gcc.h new file mode 100644 index 0000000000..7130e222e4 --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq4019-gcc.h @@ -0,0 +1,96 @@ +/* Copyright (c) 2015 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ +#ifndef __QCOM_CLK_IPQ4019_H__ +#define __QCOM_CLK_IPQ4019_H__ + +#define GCC_DUMMY_CLK 0 +#define AUDIO_CLK_SRC 1 +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 2 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 3 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 4 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 5 +#define BLSP1_UART1_APPS_CLK_SRC 6 +#define BLSP1_UART2_APPS_CLK_SRC 7 +#define GCC_USB3_MOCK_UTMI_CLK_SRC 8 +#define GCC_APPS_CLK_SRC 9 +#define GCC_APPS_AHB_CLK_SRC 10 +#define GP1_CLK_SRC 11 +#define GP2_CLK_SRC 12 +#define GP3_CLK_SRC 13 +#define SDCC1_APPS_CLK_SRC 14 +#define FEPHY_125M_DLY_CLK_SRC 15 +#define WCSS2G_CLK_SRC 16 +#define WCSS5G_CLK_SRC 17 +#define GCC_APSS_AHB_CLK 18 +#define GCC_AUDIO_AHB_CLK 19 +#define GCC_AUDIO_PWM_CLK 20 +#define GCC_BLSP1_AHB_CLK 21 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 22 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 23 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 24 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 25 +#define GCC_BLSP1_UART1_APPS_CLK 26 +#define GCC_BLSP1_UART2_APPS_CLK 27 +#define GCC_DCD_XO_CLK 28 +#define GCC_GP1_CLK 29 +#define GCC_GP2_CLK 30 +#define GCC_GP3_CLK 31 +#define GCC_BOOT_ROM_AHB_CLK 32 +#define GCC_CRYPTO_AHB_CLK 33 +#define GCC_CRYPTO_AXI_CLK 34 +#define GCC_CRYPTO_CLK 35 +#define GCC_ESS_CLK 36 +#define GCC_IMEM_AXI_CLK 37 +#define GCC_IMEM_CFG_AHB_CLK 38 +#define GCC_PCIE_AHB_CLK 39 +#define GCC_PCIE_AXI_M_CLK 40 +#define GCC_PCIE_AXI_S_CLK 41 +#define GCC_PCNOC_AHB_CLK 42 +#define GCC_PRNG_AHB_CLK 43 +#define GCC_QPIC_AHB_CLK 44 +#define GCC_QPIC_CLK 45 +#define GCC_SDCC1_AHB_CLK 46 +#define GCC_SDCC1_APPS_CLK 47 +#define GCC_SNOC_PCNOC_AHB_CLK 48 +#define GCC_SYS_NOC_125M_CLK 49 +#define GCC_SYS_NOC_AXI_CLK 50 +#define GCC_TCSR_AHB_CLK 51 +#define GCC_TLMM_AHB_CLK 52 +#define GCC_USB2_MASTER_CLK 53 +#define GCC_USB2_SLEEP_CLK 54 +#define GCC_USB2_MOCK_UTMI_CLK 55 +#define GCC_USB3_MASTER_CLK 56 +#define GCC_USB3_SLEEP_CLK 57 +#define GCC_USB3_MOCK_UTMI_CLK 58 +#define GCC_WCSS2G_CLK 59 +#define GCC_WCSS2G_REF_CLK 60 +#define GCC_WCSS2G_RTC_CLK 61 +#define GCC_WCSS5G_CLK 62 +#define GCC_WCSS5G_REF_CLK 63 +#define GCC_WCSS5G_RTC_CLK 64 +#define GCC_APSS_DDRPLL_VCO 65 +#define GCC_SDCC_PLLDIV_CLK 66 +#define GCC_FEPLL_VCO 67 +#define GCC_FEPLL125_CLK 68 +#define GCC_FEPLL125DLY_CLK 69 +#define GCC_FEPLL200_CLK 70 +#define GCC_FEPLL500_CLK 71 +#define GCC_FEPLL_WCSS2G_CLK 72 +#define GCC_FEPLL_WCSS5G_CLK 73 +#define GCC_APSS_CPU_PLLDIV_CLK 74 +#define GCC_PCNOC_AHB_CLK_SRC 75 + +#endif From df85e9576c18e868c7d42c224a0967cd31f489c0 Mon Sep 17 00:00:00 2001 From: Chuanjia Liu Date: Mon, 31 Aug 2020 15:53:12 +0800 Subject: [PATCH 11/12] PCI: mediatek: Release the resource when PCIe enable port fail On the mt7623 platform, if one port enable fail and other port enable succeed. It will hang on when using pci enum because the resource was not released correctly. Signed-off-by: Chuanjia Liu Tested-by: Frank Wunderlich --- drivers/pci/pcie_mediatek.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/pci/pcie_mediatek.c b/drivers/pci/pcie_mediatek.c index ad34f7c597..55b6a40f25 100644 --- a/drivers/pci/pcie_mediatek.c +++ b/drivers/pci/pcie_mediatek.c @@ -443,29 +443,36 @@ static void mtk_pcie_enable_port(struct mtk_pcie_port *port) err = clk_enable(&port->sys_ck); if (err) - goto exit; + goto err_sys_clk; err = reset_assert(&port->reset); if (err) - goto exit; + goto err_reset; err = reset_deassert(&port->reset); if (err) - goto exit; + goto err_reset; err = generic_phy_init(&port->phy); if (err) - goto exit; + goto err_phy_init; err = generic_phy_power_on(&port->phy); if (err) - goto exit; + goto err_phy_on; if (!mtk_pcie_startup_port(port)) return; pr_err("Port%d link down\n", port->slot); -exit: + + generic_phy_power_off(&port->phy); +err_phy_on: + generic_phy_exit(&port->phy); +err_phy_init: +err_reset: + clk_disable(&port->sys_ck); +err_sys_clk: mtk_pcie_port_free(port); } From 0b65e494e98d645a500c0e378957e6dafbd3ab8f Mon Sep 17 00:00:00 2001 From: Thirupathaiah Annapureddy Date: Tue, 1 Sep 2020 13:42:45 -0700 Subject: [PATCH 12/12] arm: dts: fix ast2500-evb inclusion for the correct soc family Include ast2500-evb.dtb for CONFIG_ASPEED_AST2500 instead of for all aspeed targets. ast2400 is based on ARM926EJ-S processor (ARMv5-architecture). ast2500 is based on ARM1176JZS processor (ARMv6-architecture). ast2600 is based on Cortex A7 processor (ARMv7-A architecture). Each of the above SOC is using a different ARM CPU(s) with different ARM architecture revision. It is not possible to support all 3 of these families in a single binary. So there is no need to build ast2500-evb.dtb for other SOC families. Signed-off-by: Thirupathaiah Annapureddy --- arch/arm/dts/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f8f529435b..72b6fe1a3e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -938,7 +938,7 @@ dtb-$(CONFIG_ARCH_BCM6858) += \ dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb -dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb +dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb