mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-22 02:49:44 +09:00
Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx
This commit is contained in:
commit
23b5b1d3e1
@ -25,8 +25,10 @@ include $(TOPDIR)/config.mk
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|||||||
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||||||
LIB = $(obj)lib$(BOARD).a
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LIB = $(obj)lib$(BOARD).a
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||||||
|
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||||||
COBJS := $(BOARD).o pci.o
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COBJS-y += $(BOARD).o
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||||||
|
COBJS-$(CONFIG_PCI) += pci.o
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||||||
|
|
||||||
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COBJS := $(COBJS-y)
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||||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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||||||
OBJS := $(addprefix $(obj),$(COBJS))
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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@ -1,5 +1,5 @@
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/*
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/*
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||||||
* Copyright (C) 2006 Freescale Semiconductor, Inc.
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* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
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*
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*
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||||||
* See file CREDITS for list of people who contributed to this
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* See file CREDITS for list of people who contributed to this
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||||||
* project.
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* project.
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||||||
@ -16,62 +16,78 @@
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|||||||
#include <asm/mmu.h>
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#include <asm/mmu.h>
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||||||
#include <asm/io.h>
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#include <asm/io.h>
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#include <common.h>
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#include <common.h>
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||||||
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#include <mpc83xx.h>
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||||||
#include <pci.h>
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#include <pci.h>
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||||||
#include <i2c.h>
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#include <i2c.h>
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||||||
#if defined(CONFIG_OF_LIBFDT)
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|
||||||
#include <libfdt.h>
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|
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#include <fdt_support.h>
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#endif
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|
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||||||
#include <asm/fsl_i2c.h>
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#include <asm/fsl_i2c.h>
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||||||
|
#include "../common/pq-mds-pib.h"
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|
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DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
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||||||
|
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||||||
#if defined(CONFIG_PCI)
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static struct pci_region pci1_regions[] = {
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#define PCI_FUNCTION_CONFIG 0x44
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#define PCI_FUNCTION_CFG_LOCK 0x20
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||||||
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||||||
/*
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|
||||||
* Initialize PCI Devices, report devices found
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|
||||||
*/
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|
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#ifndef CONFIG_PCI_PNP
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|
||||||
static struct pci_config_table pci_mpc83xxemds_config_table[] = {
|
|
||||||
{
|
{
|
||||||
PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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bus_start: CONFIG_SYS_PCI1_MEM_BASE,
|
||||||
pci_cfgfunc_config_device,
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phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
|
||||||
{PCI_ENET0_IOADDR,
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size: CONFIG_SYS_PCI1_MEM_SIZE,
|
||||||
PCI_ENET0_MEMADDR,
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flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
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||||||
PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
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|
||||||
},
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},
|
||||||
{}
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|
||||||
}
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|
||||||
#endif
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|
||||||
static struct pci_controller hose[] = {
|
|
||||||
{
|
{
|
||||||
#ifndef CONFIG_PCI_PNP
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bus_start: CONFIG_SYS_PCI1_IO_BASE,
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config_table:pci_mpc83xxemds_config_table,
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phys_start: CONFIG_SYS_PCI1_IO_PHYS,
|
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#endif
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size: CONFIG_SYS_PCI1_IO_SIZE,
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|
flags: PCI_REGION_IO
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||||||
|
},
|
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|
{
|
||||||
|
bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
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||||||
|
phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
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||||||
|
size: CONFIG_SYS_PCI1_MMIO_SIZE,
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||||||
|
flags: PCI_REGION_MEM
|
||||||
},
|
},
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||||||
};
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};
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||||||
|
|
||||||
/**********************************************************************
|
#ifdef CONFIG_MPC83XX_PCI2
|
||||||
* pci_init_board()
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static struct pci_region pci2_regions[] = {
|
||||||
*********************************************************************/
|
{
|
||||||
|
bus_start: CONFIG_SYS_PCI2_MEM_BASE,
|
||||||
|
phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
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||||||
|
size: CONFIG_SYS_PCI2_MEM_SIZE,
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||||||
|
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
|
||||||
|
},
|
||||||
|
{
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||||||
|
bus_start: CONFIG_SYS_PCI2_IO_BASE,
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||||||
|
phys_start: CONFIG_SYS_PCI2_IO_PHYS,
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||||||
|
size: CONFIG_SYS_PCI2_IO_SIZE,
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flags: PCI_REGION_IO
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||||||
|
},
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|
{
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||||||
|
bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
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phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
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size: CONFIG_SYS_PCI2_MMIO_SIZE,
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flags: PCI_REGION_MEM
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||||||
|
},
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|
};
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#endif
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||||||
|
DECLARE_GLOBAL_DATA_PTR;
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|
|
||||||
|
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||||||
void pci_init_board(void)
|
void pci_init_board(void)
|
||||||
#ifdef CONFIG_PCISLAVE
|
#ifdef CONFIG_PCISLAVE
|
||||||
{
|
{
|
||||||
u16 reg16;
|
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
|
||||||
volatile immap_t *immr;
|
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
|
||||||
volatile law83xx_t *pci_law;
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volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
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||||||
volatile pot83xx_t *pci_pot;
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struct pci_region *reg[] = { pci1_regions };
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volatile pcictrl83xx_t *pci_ctrl;
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|
||||||
volatile pciconf83xx_t *pci_conf;
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/* Configure PCI Local Access Windows */
|
||||||
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pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
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pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
|
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|
||||||
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pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
|
||||||
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pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
|
||||||
|
|
||||||
|
mpc83xx_pci_init(1, reg, 0);
|
||||||
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|
||||||
immr = (immap_t *) CONFIG_SYS_IMMR;
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|
||||||
pci_law = immr->sysconf.pcilaw;
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|
||||||
pci_pot = immr->ios.pot;
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|
||||||
pci_ctrl = immr->pci_ctrl;
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|
||||||
pci_conf = immr->pci_conf;
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|
||||||
/*
|
/*
|
||||||
* Configure PCI Inbound Translation Windows
|
* Configure PCI Inbound Translation Windows
|
||||||
*/
|
*/
|
||||||
@ -90,61 +106,24 @@ void pci_init_board(void)
|
|||||||
pci_ctrl[0].piebar2 = 0x0;
|
pci_ctrl[0].piebar2 = 0x0;
|
||||||
pci_ctrl[0].piwar2 &= ~PIWAR_EN;
|
pci_ctrl[0].piwar2 &= ~PIWAR_EN;
|
||||||
|
|
||||||
hose[0].first_busno = 0;
|
/* Unlock the configuration bit */
|
||||||
hose[0].last_busno = 0xff;
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mpc83xx_pcislave_unlock(0);
|
||||||
pci_setup_indirect(&hose[0],
|
printf("PCI: Agent mode enabled\n");
|
||||||
(CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304));
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|
||||||
reg16 = 0xff;
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|
||||||
|
|
||||||
pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
|
|
||||||
PCI_COMMAND, ®16);
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|
||||||
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY;
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|
||||||
pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
|
|
||||||
PCI_COMMAND, reg16);
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|
||||||
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|
||||||
/*
|
|
||||||
* Clear non-reserved bits in status register.
|
|
||||||
*/
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|
||||||
pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
|
|
||||||
PCI_STATUS, 0xffff);
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|
||||||
pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0),
|
|
||||||
PCI_LATENCY_TIMER, 0x80);
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|
||||||
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|
||||||
/*
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|
||||||
* Unlock configuration lock in PCI function configuration register.
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|
||||||
*/
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|
||||||
pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
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|
||||||
PCI_FUNCTION_CONFIG, ®16);
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||||||
reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
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|
||||||
pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
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|
||||||
PCI_FUNCTION_CONFIG, reg16);
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|
||||||
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|
||||||
printf("Enabled PCI 32bit Agent Mode\n");
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|
||||||
}
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}
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||||||
#else
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#else
|
||||||
{
|
{
|
||||||
volatile immap_t *immr;
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volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
|
||||||
volatile clk83xx_t *clk;
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volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
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||||||
volatile law83xx_t *pci_law;
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volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
|
||||||
volatile pot83xx_t *pci_pot;
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#ifndef CONFIG_MPC83XX_PCI2
|
||||||
volatile pcictrl83xx_t *pci_ctrl;
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struct pci_region *reg[] = { pci1_regions };
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||||||
volatile pciconf83xx_t *pci_conf;
|
#else
|
||||||
|
struct pci_region *reg[] = { pci1_regions, pci2_regions };
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||||||
|
#endif
|
||||||
|
|
||||||
u16 reg16;
|
/* initialize the PCA9555PW IO expander on the PIB board */
|
||||||
u32 val32;
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pib_init();
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u32 dev;
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|
||||||
|
|
||||||
immr = (immap_t *) CONFIG_SYS_IMMR;
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|
||||||
clk = (clk83xx_t *) & immr->clk;
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|
||||||
pci_law = immr->sysconf.pcilaw;
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|
||||||
pci_pot = immr->ios.pot;
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|
||||||
pci_ctrl = immr->pci_ctrl;
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|
||||||
pci_conf = immr->pci_conf;
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|
||||||
/*
|
|
||||||
* Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
|
|
||||||
*/
|
|
||||||
val32 = clk->occr;
|
|
||||||
udelay(2000);
|
|
||||||
#if defined(PCI_66M)
|
#if defined(PCI_66M)
|
||||||
clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
|
clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
|
||||||
printf("PCI clock is 66MHz\n");
|
printf("PCI clock is 66MHz\n");
|
||||||
@ -158,129 +137,19 @@ void pci_init_board(void)
|
|||||||
#endif
|
#endif
|
||||||
udelay(2000);
|
udelay(2000);
|
||||||
|
|
||||||
/*
|
/* Configure PCI Local Access Windows */
|
||||||
* Configure PCI Local Access Windows
|
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
|
||||||
*/
|
|
||||||
pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
|
|
||||||
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
|
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
|
||||||
|
|
||||||
pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
|
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
|
||||||
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
|
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
|
||||||
|
|
||||||
/*
|
|
||||||
* Configure PCI Outbound Translation Windows
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* PCI mem space - prefetch */
|
|
||||||
pci_pot[0].potar = (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
|
|
||||||
pci_pot[0].pobar = (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
|
|
||||||
pci_pot[0].pocmr =
|
|
||||||
POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK);
|
|
||||||
|
|
||||||
/* PCI mmio - non-prefetch mem space */
|
|
||||||
pci_pot[1].potar = (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
|
|
||||||
pci_pot[1].pobar = (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
|
|
||||||
pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
|
|
||||||
|
|
||||||
/* PCI IO space */
|
|
||||||
pci_pot[2].potar = (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
|
|
||||||
pci_pot[2].pobar = (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
|
|
||||||
pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Configure PCI Inbound Translation Windows
|
|
||||||
*/
|
|
||||||
pci_ctrl[0].pitar1 = (CONFIG_SYS_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK;
|
|
||||||
pci_ctrl[0].pibar1 = (CONFIG_SYS_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK;
|
|
||||||
pci_ctrl[0].piebar1 = 0x0;
|
|
||||||
pci_ctrl[0].piwar1 =
|
|
||||||
PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
|
|
||||||
PIWAR_IWS_2G;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Release PCI RST Output signal
|
|
||||||
*/
|
|
||||||
udelay(2000);
|
|
||||||
pci_ctrl[0].gcr = 1;
|
|
||||||
udelay(2000);
|
udelay(2000);
|
||||||
|
|
||||||
hose[0].first_busno = 0;
|
#ifndef CONFIG_MPC83XX_PCI2
|
||||||
hose[0].last_busno = 0xff;
|
mpc83xx_pci_init(1, reg, 0);
|
||||||
|
#else
|
||||||
/* PCI memory prefetch space */
|
mpc83xx_pci_init(2, reg, 0);
|
||||||
pci_set_region(hose[0].regions + 0,
|
#endif
|
||||||
CONFIG_SYS_PCI_MEM_BASE,
|
|
||||||
CONFIG_SYS_PCI_MEM_PHYS,
|
|
||||||
CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
|
|
||||||
|
|
||||||
/* PCI memory space */
|
|
||||||
pci_set_region(hose[0].regions + 1,
|
|
||||||
CONFIG_SYS_PCI_MMIO_BASE,
|
|
||||||
CONFIG_SYS_PCI_MMIO_PHYS, CONFIG_SYS_PCI_MMIO_SIZE, PCI_REGION_MEM);
|
|
||||||
|
|
||||||
/* PCI IO space */
|
|
||||||
pci_set_region(hose[0].regions + 2,
|
|
||||||
CONFIG_SYS_PCI_IO_BASE,
|
|
||||||
CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
|
|
||||||
|
|
||||||
/* System memory space */
|
|
||||||
pci_set_region(hose[0].regions + 3,
|
|
||||||
CONFIG_SYS_PCI_SLV_MEM_LOCAL,
|
|
||||||
CONFIG_SYS_PCI_SLV_MEM_BUS,
|
|
||||||
CONFIG_SYS_PCI_SLV_MEM_SIZE,
|
|
||||||
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
|
|
||||||
|
|
||||||
hose[0].region_count = 4;
|
|
||||||
|
|
||||||
pci_setup_indirect(&hose[0],
|
|
||||||
(CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304));
|
|
||||||
|
|
||||||
pci_register_hose(hose);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Write command register
|
|
||||||
*/
|
|
||||||
reg16 = 0xff;
|
|
||||||
dev = PCI_BDF(0, 0, 0);
|
|
||||||
pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, ®16);
|
|
||||||
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
|
|
||||||
pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Clear non-reserved bits in status register.
|
|
||||||
*/
|
|
||||||
pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff);
|
|
||||||
pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80);
|
|
||||||
pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Hose scan.
|
|
||||||
*/
|
|
||||||
hose->last_busno = pci_hose_scan(hose);
|
|
||||||
}
|
}
|
||||||
#endif /* CONFIG_PCISLAVE */
|
#endif /* CONFIG_PCISLAVE */
|
||||||
|
|
||||||
#if defined(CONFIG_OF_LIBFDT)
|
|
||||||
void ft_pci_setup(void *blob, bd_t *bd)
|
|
||||||
{
|
|
||||||
int nodeoffset;
|
|
||||||
int tmp[2];
|
|
||||||
const char *path;
|
|
||||||
|
|
||||||
nodeoffset = fdt_path_offset(blob, "/aliases");
|
|
||||||
if (nodeoffset >= 0) {
|
|
||||||
path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
|
|
||||||
if (path) {
|
|
||||||
tmp[0] = cpu_to_be32(hose[0].first_busno);
|
|
||||||
tmp[1] = cpu_to_be32(hose[0].last_busno);
|
|
||||||
do_fixup_by_path(blob, path, "bus-range",
|
|
||||||
&tmp, sizeof(tmp), 1);
|
|
||||||
|
|
||||||
tmp[0] = cpu_to_be32(gd->pci_clk);
|
|
||||||
do_fixup_by_path(blob, path, "clock-frequency",
|
|
||||||
&tmp, sizeof(tmp[0]), 1);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
#endif /* CONFIG_OF_LIBFDT */
|
|
||||||
#endif /* CONFIG_PCI */
|
|
||||||
|
@ -25,8 +25,10 @@ include $(TOPDIR)/config.mk
|
|||||||
|
|
||||||
LIB = $(obj)lib$(BOARD).a
|
LIB = $(obj)lib$(BOARD).a
|
||||||
|
|
||||||
COBJS := $(BOARD).o pci.o
|
COBJS-y += $(BOARD).o
|
||||||
|
COBJS-$(CONFIG_PCI) += pci.o
|
||||||
|
|
||||||
|
COBJS := $(COBJS-y)
|
||||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||||
OBJS := $(addprefix $(obj),$(COBJS))
|
OBJS := $(addprefix $(obj),$(COBJS))
|
||||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||||
|
@ -1,4 +1,6 @@
|
|||||||
/*
|
/*
|
||||||
|
* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
|
||||||
|
*
|
||||||
* See file CREDITS for list of people who contributed to this
|
* See file CREDITS for list of people who contributed to this
|
||||||
* project.
|
* project.
|
||||||
*
|
*
|
||||||
@ -29,8 +31,6 @@
|
|||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
#ifdef CONFIG_PCI
|
|
||||||
|
|
||||||
static struct pci_region pci1_regions[] = {
|
static struct pci_region pci1_regions[] = {
|
||||||
{
|
{
|
||||||
bus_start: CONFIG_SYS_PCI1_MEM_BASE,
|
bus_start: CONFIG_SYS_PCI1_MEM_BASE,
|
||||||
@ -207,5 +207,3 @@ void pci_init_board(void)
|
|||||||
printf("PCI: Agent mode enabled\n");
|
printf("PCI: Agent mode enabled\n");
|
||||||
}
|
}
|
||||||
#endif /* CONFIG_PCISLAVE */
|
#endif /* CONFIG_PCISLAVE */
|
||||||
|
|
||||||
#endif /* CONFIG_PCI */
|
|
||||||
|
@ -24,8 +24,10 @@ include $(TOPDIR)/config.mk
|
|||||||
|
|
||||||
LIB = $(obj)lib$(BOARD).a
|
LIB = $(obj)lib$(BOARD).a
|
||||||
|
|
||||||
COBJS := $(BOARD).o pci.o
|
COBJS-y += $(BOARD).o
|
||||||
|
COBJS-$(CONFIG_PCI) += pci.o
|
||||||
|
|
||||||
|
COBJS := $(COBJS-y)
|
||||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||||
OBJS := $(addprefix $(obj),$(COBJS))
|
OBJS := $(addprefix $(obj),$(COBJS))
|
||||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
* Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
|
* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
|
||||||
*
|
*
|
||||||
* See file CREDITS for list of people who contributed to this
|
* See file CREDITS for list of people who contributed to this
|
||||||
* project.
|
* project.
|
||||||
@ -22,91 +22,70 @@
|
|||||||
|
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
|
|
||||||
#ifdef CONFIG_PCI
|
|
||||||
|
|
||||||
#include <asm/mmu.h>
|
#include <asm/mmu.h>
|
||||||
#include <asm/global_data.h>
|
#include <asm/io.h>
|
||||||
|
#include <mpc83xx.h>
|
||||||
#include <pci.h>
|
#include <pci.h>
|
||||||
#include <asm/mpc8349_pci.h>
|
|
||||||
#include <i2c.h>
|
#include <i2c.h>
|
||||||
#if defined(CONFIG_OF_LIBFDT)
|
#include <asm/fsl_i2c.h>
|
||||||
#include <libfdt.h>
|
|
||||||
#include <fdt_support.h>
|
|
||||||
#endif
|
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
/* System RAM mapped to PCI space */
|
static struct pci_region pci1_regions[] = {
|
||||||
#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
|
|
||||||
#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
|
|
||||||
|
|
||||||
#ifndef CONFIG_PCI_PNP
|
|
||||||
static struct pci_config_table pci_mpc8349itx_config_table[] = {
|
|
||||||
{
|
{
|
||||||
PCI_ANY_ID,
|
bus_start: CONFIG_SYS_PCI1_MEM_BASE,
|
||||||
PCI_ANY_ID,
|
phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
|
||||||
PCI_ANY_ID,
|
size: CONFIG_SYS_PCI1_MEM_SIZE,
|
||||||
PCI_ANY_ID,
|
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
|
||||||
PCI_IDSEL_NUMBER,
|
},
|
||||||
PCI_ANY_ID,
|
{
|
||||||
pci_cfgfunc_config_device,
|
bus_start: CONFIG_SYS_PCI1_IO_BASE,
|
||||||
{
|
phys_start: CONFIG_SYS_PCI1_IO_PHYS,
|
||||||
PCI_ENET0_IOADDR,
|
size: CONFIG_SYS_PCI1_IO_SIZE,
|
||||||
PCI_ENET0_MEMADDR,
|
flags: PCI_REGION_IO
|
||||||
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
|
},
|
||||||
},
|
{
|
||||||
{}
|
bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
|
||||||
|
phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
|
||||||
|
size: CONFIG_SYS_PCI1_MMIO_SIZE,
|
||||||
|
flags: PCI_REGION_MEM
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
#ifdef CONFIG_MPC83XX_PCI2
|
||||||
|
static struct pci_region pci2_regions[] = {
|
||||||
|
{
|
||||||
|
bus_start: CONFIG_SYS_PCI2_MEM_BASE,
|
||||||
|
phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
|
||||||
|
size: CONFIG_SYS_PCI2_MEM_SIZE,
|
||||||
|
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
|
||||||
|
},
|
||||||
|
{
|
||||||
|
bus_start: CONFIG_SYS_PCI2_IO_BASE,
|
||||||
|
phys_start: CONFIG_SYS_PCI2_IO_PHYS,
|
||||||
|
size: CONFIG_SYS_PCI2_IO_SIZE,
|
||||||
|
flags: PCI_REGION_IO
|
||||||
|
},
|
||||||
|
{
|
||||||
|
bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
|
||||||
|
phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
|
||||||
|
size: CONFIG_SYS_PCI2_MMIO_SIZE,
|
||||||
|
flags: PCI_REGION_MEM
|
||||||
|
},
|
||||||
};
|
};
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
static struct pci_controller pci_hose[] = {
|
|
||||||
{
|
|
||||||
#ifndef CONFIG_PCI_PNP
|
|
||||||
config_table:pci_mpc8349itx_config_table,
|
|
||||||
#endif
|
|
||||||
},
|
|
||||||
{
|
|
||||||
#ifndef CONFIG_PCI_PNP
|
|
||||||
config_table:pci_mpc8349itx_config_table,
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
};
|
|
||||||
|
|
||||||
/**************************************************************************
|
|
||||||
* pci_init_board()
|
|
||||||
*
|
|
||||||
* NOTICE: PCI2 is not currently supported
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
void pci_init_board(void)
|
void pci_init_board(void)
|
||||||
{
|
{
|
||||||
volatile immap_t *immr;
|
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
|
||||||
volatile clk83xx_t *clk;
|
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
|
||||||
volatile law83xx_t *pci_law;
|
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
|
||||||
volatile pot83xx_t *pci_pot;
|
#ifndef CONFIG_MPC83XX_PCI2
|
||||||
volatile pcictrl83xx_t *pci_ctrl;
|
struct pci_region *reg[] = { pci1_regions };
|
||||||
volatile pciconf83xx_t *pci_conf;
|
#else
|
||||||
|
struct pci_region *reg[] = { pci1_regions, pci2_regions };
|
||||||
|
#endif
|
||||||
u8 reg8;
|
u8 reg8;
|
||||||
u16 reg16;
|
|
||||||
u32 reg32;
|
|
||||||
u32 dev;
|
|
||||||
struct pci_controller *hose;
|
|
||||||
|
|
||||||
immr = (immap_t *) CONFIG_SYS_IMMR;
|
|
||||||
clk = (clk83xx_t *) & immr->clk;
|
|
||||||
pci_law = immr->sysconf.pcilaw;
|
|
||||||
pci_pot = immr->ios.pot;
|
|
||||||
pci_ctrl = immr->pci_ctrl;
|
|
||||||
pci_conf = immr->pci_conf;
|
|
||||||
|
|
||||||
hose = &pci_hose[0];
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
|
|
||||||
*/
|
|
||||||
|
|
||||||
reg32 = clk->occr;
|
|
||||||
udelay(2000);
|
|
||||||
|
|
||||||
#ifdef CONFIG_HARD_I2C
|
#ifdef CONFIG_HARD_I2C
|
||||||
i2c_set_bus_num(1);
|
i2c_set_bus_num(1);
|
||||||
@ -123,250 +102,20 @@ void pci_init_board(void)
|
|||||||
#else
|
#else
|
||||||
clk->occr = 0xff000000; /* 66 MHz PCI */
|
clk->occr = 0xff000000; /* 66 MHz PCI */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
udelay(2000);
|
udelay(2000);
|
||||||
|
|
||||||
/*
|
/* Configure PCI Local Access Windows */
|
||||||
* Release PCI RST Output signal
|
|
||||||
*/
|
|
||||||
pci_ctrl[0].gcr = 0;
|
|
||||||
udelay(2000);
|
|
||||||
pci_ctrl[0].gcr = 1;
|
|
||||||
|
|
||||||
#ifdef CONFIG_MPC83XX_PCI2
|
|
||||||
pci_ctrl[1].gcr = 0;
|
|
||||||
udelay(2000);
|
|
||||||
pci_ctrl[1].gcr = 1;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* We need to wait at least a 1sec based on PCI specs */
|
|
||||||
{
|
|
||||||
int i;
|
|
||||||
|
|
||||||
for (i = 0; i < 1000; i++)
|
|
||||||
udelay(1000);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Configure PCI Local Access Windows
|
|
||||||
*/
|
|
||||||
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
|
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
|
||||||
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
|
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
|
||||||
|
|
||||||
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
|
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
|
||||||
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
|
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
|
||||||
|
|
||||||
/*
|
udelay(2000);
|
||||||
* Configure PCI Outbound Translation Windows
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* PCI1 mem space - prefetch */
|
#ifndef CONFIG_MPC83XX_PCI2
|
||||||
pci_pot[0].potar = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
|
mpc83xx_pci_init(1, reg, 0);
|
||||||
pci_pot[0].pobar = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
|
#else
|
||||||
pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | POCMR_CM_256M;
|
mpc83xx_pci_init(2, reg, 0);
|
||||||
|
|
||||||
/* PCI1 IO space */
|
|
||||||
pci_pot[1].potar = (CONFIG_SYS_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
|
|
||||||
pci_pot[1].pobar = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
|
|
||||||
pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M;
|
|
||||||
|
|
||||||
/* PCI1 mmio - non-prefetch mem space */
|
|
||||||
pci_pot[2].potar = (CONFIG_SYS_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
|
|
||||||
pci_pot[2].pobar = (CONFIG_SYS_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
|
|
||||||
pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Configure PCI Inbound Translation Windows
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* we need RAM mapped to PCI space for the devices to
|
|
||||||
* access main memory */
|
|
||||||
pci_ctrl[0].pitar1 = 0x0;
|
|
||||||
pci_ctrl[0].pibar1 = 0x0;
|
|
||||||
pci_ctrl[0].piebar1 = 0x0;
|
|
||||||
pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
|
|
||||||
PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
|
|
||||||
|
|
||||||
hose->first_busno = 0;
|
|
||||||
hose->last_busno = 0xff;
|
|
||||||
|
|
||||||
/* PCI memory prefetch space */
|
|
||||||
pci_set_region(hose->regions + 0,
|
|
||||||
CONFIG_SYS_PCI1_MEM_BASE,
|
|
||||||
CONFIG_SYS_PCI1_MEM_PHYS,
|
|
||||||
CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
|
|
||||||
|
|
||||||
/* PCI memory space */
|
|
||||||
pci_set_region(hose->regions + 1,
|
|
||||||
CONFIG_SYS_PCI1_MMIO_BASE,
|
|
||||||
CONFIG_SYS_PCI1_MMIO_PHYS, CONFIG_SYS_PCI1_MMIO_SIZE, PCI_REGION_MEM);
|
|
||||||
|
|
||||||
/* PCI IO space */
|
|
||||||
pci_set_region(hose->regions + 2,
|
|
||||||
CONFIG_SYS_PCI1_IO_BASE,
|
|
||||||
CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
|
|
||||||
|
|
||||||
/* System memory space */
|
|
||||||
pci_set_region(hose->regions + 3,
|
|
||||||
CONFIG_PCI_SYS_MEM_BUS,
|
|
||||||
CONFIG_PCI_SYS_MEM_PHYS,
|
|
||||||
gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
|
|
||||||
|
|
||||||
hose->region_count = 4;
|
|
||||||
|
|
||||||
pci_setup_indirect(hose,
|
|
||||||
(CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304));
|
|
||||||
|
|
||||||
pci_register_hose(hose);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Write to Command register
|
|
||||||
*/
|
|
||||||
reg16 = 0xff;
|
|
||||||
dev = PCI_BDF(hose->first_busno, 0, 0);
|
|
||||||
pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16);
|
|
||||||
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
|
|
||||||
pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Clear non-reserved bits in status register.
|
|
||||||
*/
|
|
||||||
pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
|
|
||||||
pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
|
|
||||||
pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
|
|
||||||
|
|
||||||
#ifdef CONFIG_PCI_SCAN_SHOW
|
|
||||||
printf("PCI: Bus Dev VenId DevId Class Int\n");
|
|
||||||
#endif
|
|
||||||
/*
|
|
||||||
* Hose scan.
|
|
||||||
*/
|
|
||||||
hose->last_busno = pci_hose_scan(hose);
|
|
||||||
|
|
||||||
#ifdef CONFIG_MPC83XX_PCI2
|
|
||||||
hose = &pci_hose[1];
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Configure PCI Outbound Translation Windows
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* PCI2 mem space - prefetch */
|
|
||||||
pci_pot[3].potar = (CONFIG_SYS_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
|
|
||||||
pci_pot[3].pobar = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
|
|
||||||
pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | POCMR_CM_256M;
|
|
||||||
|
|
||||||
/* PCI2 IO space */
|
|
||||||
pci_pot[4].potar = (CONFIG_SYS_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
|
|
||||||
pci_pot[4].pobar = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
|
|
||||||
pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | POCMR_CM_16M;
|
|
||||||
|
|
||||||
/* PCI2 mmio - non-prefetch mem space */
|
|
||||||
pci_pot[5].potar = (CONFIG_SYS_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
|
|
||||||
pci_pot[5].pobar = (CONFIG_SYS_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
|
|
||||||
pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_CM_256M;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Configure PCI Inbound Translation Windows
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* we need RAM mapped to PCI space for the devices to
|
|
||||||
* access main memory */
|
|
||||||
pci_ctrl[1].pitar1 = 0x0;
|
|
||||||
pci_ctrl[1].pibar1 = 0x0;
|
|
||||||
pci_ctrl[1].piebar1 = 0x0;
|
|
||||||
pci_ctrl[1].piwar1 =
|
|
||||||
PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
|
|
||||||
(__ilog2(gd->ram_size) - 1);
|
|
||||||
|
|
||||||
hose->first_busno = pci_hose[0].last_busno + 1;
|
|
||||||
hose->last_busno = 0xff;
|
|
||||||
|
|
||||||
/* PCI memory prefetch space */
|
|
||||||
pci_set_region(hose->regions + 0,
|
|
||||||
CONFIG_SYS_PCI2_MEM_BASE,
|
|
||||||
CONFIG_SYS_PCI2_MEM_PHYS,
|
|
||||||
CONFIG_SYS_PCI2_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
|
|
||||||
|
|
||||||
/* PCI memory space */
|
|
||||||
pci_set_region(hose->regions + 1,
|
|
||||||
CONFIG_SYS_PCI2_MMIO_BASE,
|
|
||||||
CONFIG_SYS_PCI2_MMIO_PHYS, CONFIG_SYS_PCI2_MMIO_SIZE, PCI_REGION_MEM);
|
|
||||||
|
|
||||||
/* PCI IO space */
|
|
||||||
pci_set_region(hose->regions + 2,
|
|
||||||
CONFIG_SYS_PCI2_IO_BASE,
|
|
||||||
CONFIG_SYS_PCI2_IO_PHYS, CONFIG_SYS_PCI2_IO_SIZE, PCI_REGION_IO);
|
|
||||||
|
|
||||||
/* System memory space */
|
|
||||||
pci_set_region(hose->regions + 3,
|
|
||||||
CONFIG_PCI_SYS_MEM_BUS,
|
|
||||||
CONFIG_PCI_SYS_MEM_PHYS,
|
|
||||||
gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
|
|
||||||
|
|
||||||
hose->region_count = 4;
|
|
||||||
|
|
||||||
pci_setup_indirect(hose,
|
|
||||||
(CONFIG_SYS_IMMR + 0x8380), (CONFIG_SYS_IMMR + 0x8384));
|
|
||||||
|
|
||||||
pci_register_hose(hose);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Write to Command register
|
|
||||||
*/
|
|
||||||
reg16 = 0xff;
|
|
||||||
dev = PCI_BDF(hose->first_busno, 0, 0);
|
|
||||||
pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16);
|
|
||||||
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
|
|
||||||
pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Clear non-reserved bits in status register.
|
|
||||||
*/
|
|
||||||
pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
|
|
||||||
pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
|
|
||||||
pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Hose scan.
|
|
||||||
*/
|
|
||||||
hose->last_busno = pci_hose_scan(hose);
|
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
#if defined(CONFIG_OF_LIBFDT)
|
|
||||||
void ft_pci_setup(void *blob, bd_t *bd)
|
|
||||||
{
|
|
||||||
int nodeoffset;
|
|
||||||
int tmp[2];
|
|
||||||
const char *path;
|
|
||||||
|
|
||||||
nodeoffset = fdt_path_offset(blob, "/aliases");
|
|
||||||
if (nodeoffset >= 0) {
|
|
||||||
path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
|
|
||||||
if (path) {
|
|
||||||
tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
|
|
||||||
tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
|
|
||||||
do_fixup_by_path(blob, path, "bus-range",
|
|
||||||
&tmp, sizeof(tmp), 1);
|
|
||||||
|
|
||||||
tmp[0] = cpu_to_be32(gd->pci_clk);
|
|
||||||
do_fixup_by_path(blob, path, "clock-frequency",
|
|
||||||
&tmp, sizeof(tmp[0]), 1);
|
|
||||||
}
|
|
||||||
#ifdef CONFIG_MPC83XX_PCI2
|
|
||||||
path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
|
|
||||||
if (path) {
|
|
||||||
tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
|
|
||||||
tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
|
|
||||||
do_fixup_by_path(blob, path, "bus-range",
|
|
||||||
&tmp, sizeof(tmp), 1);
|
|
||||||
|
|
||||||
tmp[0] = cpu_to_be32(gd->pci_clk);
|
|
||||||
do_fixup_by_path(blob, path, "clock-frequency",
|
|
||||||
&tmp, sizeof(tmp[0]), 1);
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
}
|
|
||||||
#endif /* CONFIG_OF_LIBFDT */
|
|
||||||
#endif /* CONFIG_PCI */
|
|
||||||
|
@ -25,8 +25,10 @@ include $(TOPDIR)/config.mk
|
|||||||
|
|
||||||
LIB = $(obj)lib$(BOARD).a
|
LIB = $(obj)lib$(BOARD).a
|
||||||
|
|
||||||
COBJS := $(BOARD).o pci.o
|
COBJS-y += $(BOARD).o
|
||||||
|
COBJS-$(CONFIG_PCI) += pci.o
|
||||||
|
|
||||||
|
COBJS := $(COBJS-y)
|
||||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||||
OBJS := $(addprefix $(obj),$(COBJS))
|
OBJS := $(addprefix $(obj),$(COBJS))
|
||||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
* Copyright (C) 2006 Freescale Semiconductor, Inc.
|
* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
|
||||||
*
|
*
|
||||||
* See file CREDITS for list of people who contributed to this
|
* See file CREDITS for list of people who contributed to this
|
||||||
* project.
|
* project.
|
||||||
@ -13,65 +13,79 @@
|
|||||||
/*
|
/*
|
||||||
* PCI Configuration space access support for MPC83xx PCI Bridge
|
* PCI Configuration space access support for MPC83xx PCI Bridge
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <asm/mmu.h>
|
#include <asm/mmu.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
|
#include <mpc83xx.h>
|
||||||
#include <pci.h>
|
#include <pci.h>
|
||||||
#include <i2c.h>
|
#include <i2c.h>
|
||||||
#if defined(CONFIG_OF_LIBFDT)
|
|
||||||
#include <libfdt.h>
|
|
||||||
#include <fdt_support.h>
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#include <asm/fsl_i2c.h>
|
#include <asm/fsl_i2c.h>
|
||||||
|
#include "../common/pq-mds-pib.h"
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
#if defined(CONFIG_PCI)
|
static struct pci_region pci1_regions[] = {
|
||||||
#define PCI_FUNCTION_CONFIG 0x44
|
|
||||||
#define PCI_FUNCTION_CFG_LOCK 0x20
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Initialize PCI Devices, report devices found
|
|
||||||
*/
|
|
||||||
#ifndef CONFIG_PCI_PNP
|
|
||||||
static struct pci_config_table pci_mpc83xxemds_config_table[] = {
|
|
||||||
{
|
{
|
||||||
PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
|
bus_start: CONFIG_SYS_PCI1_MEM_BASE,
|
||||||
pci_cfgfunc_config_device,
|
phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
|
||||||
{PCI_ENET0_IOADDR,
|
size: CONFIG_SYS_PCI1_MEM_SIZE,
|
||||||
PCI_ENET0_MEMADDR,
|
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
|
||||||
PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
|
},
|
||||||
},
|
|
||||||
{}
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
static struct pci_controller hose[] = {
|
|
||||||
{
|
{
|
||||||
#ifndef CONFIG_PCI_PNP
|
bus_start: CONFIG_SYS_PCI1_IO_BASE,
|
||||||
config_table:pci_mpc83xxemds_config_table,
|
phys_start: CONFIG_SYS_PCI1_IO_PHYS,
|
||||||
#endif
|
size: CONFIG_SYS_PCI1_IO_SIZE,
|
||||||
},
|
flags: PCI_REGION_IO
|
||||||
|
},
|
||||||
|
{
|
||||||
|
bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
|
||||||
|
phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
|
||||||
|
size: CONFIG_SYS_PCI1_MMIO_SIZE,
|
||||||
|
flags: PCI_REGION_MEM
|
||||||
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
/**********************************************************************
|
#ifdef CONFIG_MPC83XX_PCI2
|
||||||
* pci_init_board()
|
static struct pci_region pci2_regions[] = {
|
||||||
*********************************************************************/
|
{
|
||||||
|
bus_start: CONFIG_SYS_PCI2_MEM_BASE,
|
||||||
|
phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
|
||||||
|
size: CONFIG_SYS_PCI2_MEM_SIZE,
|
||||||
|
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
|
||||||
|
},
|
||||||
|
{
|
||||||
|
bus_start: CONFIG_SYS_PCI2_IO_BASE,
|
||||||
|
phys_start: CONFIG_SYS_PCI2_IO_PHYS,
|
||||||
|
size: CONFIG_SYS_PCI2_IO_SIZE,
|
||||||
|
flags: PCI_REGION_IO
|
||||||
|
},
|
||||||
|
{
|
||||||
|
bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
|
||||||
|
phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
|
||||||
|
size: CONFIG_SYS_PCI2_MMIO_SIZE,
|
||||||
|
flags: PCI_REGION_MEM
|
||||||
|
},
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
void pci_init_board(void)
|
void pci_init_board(void)
|
||||||
#ifdef CONFIG_PCISLAVE
|
#ifdef CONFIG_PCISLAVE
|
||||||
{
|
{
|
||||||
u16 reg16;
|
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
|
||||||
volatile immap_t *immr;
|
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
|
||||||
volatile law83xx_t *pci_law;
|
volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
|
||||||
volatile pot83xx_t *pci_pot;
|
struct pci_region *reg[] = { pci1_regions };
|
||||||
volatile pcictrl83xx_t *pci_ctrl;
|
|
||||||
volatile pciconf83xx_t *pci_conf;
|
/* Configure PCI Local Access Windows */
|
||||||
|
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
|
||||||
|
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
|
||||||
|
|
||||||
|
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
|
||||||
|
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
|
||||||
|
|
||||||
|
mpc83xx_pci_init(1, reg, 0);
|
||||||
|
|
||||||
immr = (immap_t *) CONFIG_SYS_IMMR;
|
|
||||||
pci_law = immr->sysconf.pcilaw;
|
|
||||||
pci_pot = immr->ios.pot;
|
|
||||||
pci_ctrl = immr->pci_ctrl;
|
|
||||||
pci_conf = immr->pci_conf;
|
|
||||||
/*
|
/*
|
||||||
* Configure PCI Inbound Translation Windows
|
* Configure PCI Inbound Translation Windows
|
||||||
*/
|
*/
|
||||||
@ -90,61 +104,24 @@ void pci_init_board(void)
|
|||||||
pci_ctrl[0].piebar2 = 0x0;
|
pci_ctrl[0].piebar2 = 0x0;
|
||||||
pci_ctrl[0].piwar2 &= ~PIWAR_EN;
|
pci_ctrl[0].piwar2 &= ~PIWAR_EN;
|
||||||
|
|
||||||
hose[0].first_busno = 0;
|
/* Unlock the configuration bit */
|
||||||
hose[0].last_busno = 0xff;
|
mpc83xx_pcislave_unlock(0);
|
||||||
pci_setup_indirect(&hose[0],
|
printf("PCI: Agent mode enabled\n");
|
||||||
(CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304));
|
|
||||||
reg16 = 0xff;
|
|
||||||
|
|
||||||
pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
|
|
||||||
PCI_COMMAND, ®16);
|
|
||||||
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY;
|
|
||||||
pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
|
|
||||||
PCI_COMMAND, reg16);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Clear non-reserved bits in status register.
|
|
||||||
*/
|
|
||||||
pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
|
|
||||||
PCI_STATUS, 0xffff);
|
|
||||||
pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0),
|
|
||||||
PCI_LATENCY_TIMER, 0x80);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Unlock configuration lock in PCI function configuration register.
|
|
||||||
*/
|
|
||||||
pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
|
|
||||||
PCI_FUNCTION_CONFIG, ®16);
|
|
||||||
reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
|
|
||||||
pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
|
|
||||||
PCI_FUNCTION_CONFIG, reg16);
|
|
||||||
|
|
||||||
printf("Enabled PCI 32bit Agent Mode\n");
|
|
||||||
}
|
}
|
||||||
#else
|
#else
|
||||||
{
|
{
|
||||||
volatile immap_t *immr;
|
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
|
||||||
volatile clk83xx_t *clk;
|
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
|
||||||
volatile law83xx_t *pci_law;
|
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
|
||||||
volatile pot83xx_t *pci_pot;
|
#ifndef CONFIG_MPC83XX_PCI2
|
||||||
volatile pcictrl83xx_t *pci_ctrl;
|
struct pci_region *reg[] = { pci1_regions };
|
||||||
volatile pciconf83xx_t *pci_conf;
|
#else
|
||||||
|
struct pci_region *reg[] = { pci1_regions, pci2_regions };
|
||||||
|
#endif
|
||||||
|
|
||||||
u16 reg16;
|
/* initialize the PCA9555PW IO expander on the PIB board */
|
||||||
u32 val32;
|
pib_init();
|
||||||
u32 dev;
|
|
||||||
|
|
||||||
immr = (immap_t *) CONFIG_SYS_IMMR;
|
|
||||||
clk = (clk83xx_t *) & immr->clk;
|
|
||||||
pci_law = immr->sysconf.pcilaw;
|
|
||||||
pci_pot = immr->ios.pot;
|
|
||||||
pci_ctrl = immr->pci_ctrl;
|
|
||||||
pci_conf = immr->pci_conf;
|
|
||||||
/*
|
|
||||||
* Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
|
|
||||||
*/
|
|
||||||
val32 = clk->occr;
|
|
||||||
udelay(2000);
|
|
||||||
#if defined(PCI_66M)
|
#if defined(PCI_66M)
|
||||||
clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
|
clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
|
||||||
printf("PCI clock is 66MHz\n");
|
printf("PCI clock is 66MHz\n");
|
||||||
@ -158,129 +135,19 @@ void pci_init_board(void)
|
|||||||
#endif
|
#endif
|
||||||
udelay(2000);
|
udelay(2000);
|
||||||
|
|
||||||
/*
|
/* Configure PCI Local Access Windows */
|
||||||
* Configure PCI Local Access Windows
|
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
|
||||||
*/
|
|
||||||
pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
|
|
||||||
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
|
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
|
||||||
|
|
||||||
pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
|
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
|
||||||
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
|
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
|
||||||
|
|
||||||
/*
|
|
||||||
* Configure PCI Outbound Translation Windows
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* PCI mem space - prefetch */
|
|
||||||
pci_pot[0].potar = (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
|
|
||||||
pci_pot[0].pobar = (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
|
|
||||||
pci_pot[0].pocmr =
|
|
||||||
POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK);
|
|
||||||
|
|
||||||
/* PCI mmio - non-prefetch mem space */
|
|
||||||
pci_pot[1].potar = (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
|
|
||||||
pci_pot[1].pobar = (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
|
|
||||||
pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
|
|
||||||
|
|
||||||
/* PCI IO space */
|
|
||||||
pci_pot[2].potar = (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
|
|
||||||
pci_pot[2].pobar = (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
|
|
||||||
pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Configure PCI Inbound Translation Windows
|
|
||||||
*/
|
|
||||||
pci_ctrl[0].pitar1 = (CONFIG_SYS_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK;
|
|
||||||
pci_ctrl[0].pibar1 = (CONFIG_SYS_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK;
|
|
||||||
pci_ctrl[0].piebar1 = 0x0;
|
|
||||||
pci_ctrl[0].piwar1 =
|
|
||||||
PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
|
|
||||||
PIWAR_IWS_2G;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Release PCI RST Output signal
|
|
||||||
*/
|
|
||||||
udelay(2000);
|
|
||||||
pci_ctrl[0].gcr = 1;
|
|
||||||
udelay(2000);
|
udelay(2000);
|
||||||
|
|
||||||
hose[0].first_busno = 0;
|
#ifndef CONFIG_MPC83XX_PCI2
|
||||||
hose[0].last_busno = 0xff;
|
mpc83xx_pci_init(1, reg, 0);
|
||||||
|
#else
|
||||||
/* PCI memory prefetch space */
|
mpc83xx_pci_init(2, reg, 0);
|
||||||
pci_set_region(hose[0].regions + 0,
|
#endif
|
||||||
CONFIG_SYS_PCI_MEM_BASE,
|
|
||||||
CONFIG_SYS_PCI_MEM_PHYS,
|
|
||||||
CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
|
|
||||||
|
|
||||||
/* PCI memory space */
|
|
||||||
pci_set_region(hose[0].regions + 1,
|
|
||||||
CONFIG_SYS_PCI_MMIO_BASE,
|
|
||||||
CONFIG_SYS_PCI_MMIO_PHYS, CONFIG_SYS_PCI_MMIO_SIZE, PCI_REGION_MEM);
|
|
||||||
|
|
||||||
/* PCI IO space */
|
|
||||||
pci_set_region(hose[0].regions + 2,
|
|
||||||
CONFIG_SYS_PCI_IO_BASE,
|
|
||||||
CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
|
|
||||||
|
|
||||||
/* System memory space */
|
|
||||||
pci_set_region(hose[0].regions + 3,
|
|
||||||
CONFIG_SYS_PCI_SLV_MEM_LOCAL,
|
|
||||||
CONFIG_SYS_PCI_SLV_MEM_BUS,
|
|
||||||
CONFIG_SYS_PCI_SLV_MEM_SIZE,
|
|
||||||
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
|
|
||||||
|
|
||||||
hose[0].region_count = 4;
|
|
||||||
|
|
||||||
pci_setup_indirect(&hose[0],
|
|
||||||
(CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304));
|
|
||||||
|
|
||||||
pci_register_hose(hose);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Write command register
|
|
||||||
*/
|
|
||||||
reg16 = 0xff;
|
|
||||||
dev = PCI_BDF(0, 0, 0);
|
|
||||||
pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, ®16);
|
|
||||||
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
|
|
||||||
pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Clear non-reserved bits in status register.
|
|
||||||
*/
|
|
||||||
pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff);
|
|
||||||
pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80);
|
|
||||||
pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Hose scan.
|
|
||||||
*/
|
|
||||||
hose->last_busno = pci_hose_scan(hose);
|
|
||||||
}
|
}
|
||||||
#endif /* CONFIG_PCISLAVE */
|
#endif /* CONFIG_PCISLAVE */
|
||||||
|
|
||||||
#if defined(CONFIG_OF_LIBFDT)
|
|
||||||
void ft_pci_setup(void *blob, bd_t *bd)
|
|
||||||
{
|
|
||||||
int nodeoffset;
|
|
||||||
int tmp[2];
|
|
||||||
const char *path;
|
|
||||||
|
|
||||||
nodeoffset = fdt_path_offset(blob, "/aliases");
|
|
||||||
if (nodeoffset >= 0) {
|
|
||||||
path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
|
|
||||||
if (path) {
|
|
||||||
tmp[0] = cpu_to_be32(hose[0].first_busno);
|
|
||||||
tmp[1] = cpu_to_be32(hose[0].last_busno);
|
|
||||||
do_fixup_by_path(blob, path, "bus-range",
|
|
||||||
&tmp, sizeof(tmp), 1);
|
|
||||||
|
|
||||||
tmp[0] = cpu_to_be32(gd->pci_clk);
|
|
||||||
do_fixup_by_path(blob, path, "clock-frequency",
|
|
||||||
&tmp, sizeof(tmp[0]), 1);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
#endif /* CONFIG_OF_LIBFDT */
|
|
||||||
#endif /* CONFIG_PCI */
|
|
||||||
|
@ -25,8 +25,10 @@ include $(TOPDIR)/config.mk
|
|||||||
|
|
||||||
LIB = $(obj)lib$(BOARD).a
|
LIB = $(obj)lib$(BOARD).a
|
||||||
|
|
||||||
COBJS := $(BOARD).o pci.o
|
COBJS-y += $(BOARD).o
|
||||||
|
COBJS-$(CONFIG_PCI) += pci.o
|
||||||
|
|
||||||
|
COBJS := $(COBJS-y)
|
||||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||||
OBJS := $(addprefix $(obj),$(COBJS))
|
OBJS := $(addprefix $(obj),$(COBJS))
|
||||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
* Copyright (C) 2007 Freescale Semiconductor, Inc.
|
* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
|
||||||
*
|
*
|
||||||
* See file CREDITS for list of people who contributed to this
|
* See file CREDITS for list of people who contributed to this
|
||||||
* project.
|
* project.
|
||||||
@ -20,7 +20,6 @@
|
|||||||
#include <asm/fsl_i2c.h>
|
#include <asm/fsl_i2c.h>
|
||||||
#include <asm/fsl_serdes.h>
|
#include <asm/fsl_serdes.h>
|
||||||
|
|
||||||
#if defined(CONFIG_PCI)
|
|
||||||
static struct pci_region pci_regions[] = {
|
static struct pci_region pci_regions[] = {
|
||||||
{
|
{
|
||||||
bus_start: CONFIG_SYS_PCI_MEM_BASE,
|
bus_start: CONFIG_SYS_PCI_MEM_BASE,
|
||||||
@ -152,4 +151,3 @@ void ft_pcie_fixup(void *blob, bd_t *bd)
|
|||||||
do_fixup_by_path(blob, "pci2", "status", status,
|
do_fixup_by_path(blob, "pci2", "status", status,
|
||||||
strlen(status) + 1, 1);
|
strlen(status) + 1, 1);
|
||||||
}
|
}
|
||||||
#endif /* CONFIG_PCI */
|
|
||||||
|
@ -25,8 +25,10 @@ include $(TOPDIR)/config.mk
|
|||||||
|
|
||||||
LIB = $(obj)lib$(BOARD).a
|
LIB = $(obj)lib$(BOARD).a
|
||||||
|
|
||||||
COBJS := $(BOARD).o pci.o
|
COBJS-y += $(BOARD).o
|
||||||
|
COBJS-$(CONFIG_PCI) += pci.o
|
||||||
|
|
||||||
|
COBJS := $(COBJS-y)
|
||||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||||
OBJS := $(addprefix $(obj),$(COBJS))
|
OBJS := $(addprefix $(obj),$(COBJS))
|
||||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
* Copyright (C) 2007 Freescale Semiconductor, Inc.
|
* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
|
||||||
*
|
*
|
||||||
* See file CREDITS for list of people who contributed to this
|
* See file CREDITS for list of people who contributed to this
|
||||||
* project.
|
* project.
|
||||||
@ -15,7 +15,6 @@
|
|||||||
#include <pci.h>
|
#include <pci.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
|
|
||||||
#if defined(CONFIG_PCI)
|
|
||||||
static struct pci_region pci_regions[] = {
|
static struct pci_region pci_regions[] = {
|
||||||
{
|
{
|
||||||
bus_start: CONFIG_SYS_PCI_MEM_BASE,
|
bus_start: CONFIG_SYS_PCI_MEM_BASE,
|
||||||
@ -113,4 +112,3 @@ void pci_init_board(void)
|
|||||||
|
|
||||||
mpc83xx_pcie_init(2, pcie_reg, 0);
|
mpc83xx_pcie_init(2, pcie_reg, 0);
|
||||||
}
|
}
|
||||||
#endif /* CONFIG_PCI */
|
|
||||||
|
@ -24,8 +24,10 @@ include $(TOPDIR)/config.mk
|
|||||||
|
|
||||||
LIB = $(obj)lib$(BOARD).a
|
LIB = $(obj)lib$(BOARD).a
|
||||||
|
|
||||||
COBJS := $(BOARD).o pci.o
|
COBJS-y += $(BOARD).o
|
||||||
|
COBJS-$(CONFIG_PCI) += pci.o
|
||||||
|
|
||||||
|
COBJS := $(COBJS-y)
|
||||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||||
OBJS := $(addprefix $(obj),$(COBJS))
|
OBJS := $(addprefix $(obj),$(COBJS))
|
||||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||||
|
@ -1,6 +1,7 @@
|
|||||||
/*
|
/*
|
||||||
* pci.c -- WindRiver SBC8349 PCI board support.
|
* pci.c -- WindRiver SBC8349 PCI board support.
|
||||||
* Copyright (c) 2006 Wind River Systems, Inc.
|
* Copyright (c) 2006 Wind River Systems, Inc.
|
||||||
|
* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
|
||||||
*
|
*
|
||||||
* Based on MPC8349 PCI support but w/o PIB related code.
|
* Based on MPC8349 PCI support but w/o PIB related code.
|
||||||
*
|
*
|
||||||
@ -25,51 +26,37 @@
|
|||||||
*/
|
*/
|
||||||
|
|
||||||
#include <asm/mmu.h>
|
#include <asm/mmu.h>
|
||||||
|
#include <asm/io.h>
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <asm/global_data.h>
|
#include <mpc83xx.h>
|
||||||
#include <pci.h>
|
#include <pci.h>
|
||||||
#include <asm/mpc8349_pci.h>
|
|
||||||
#include <i2c.h>
|
#include <i2c.h>
|
||||||
#if defined(CONFIG_OF_LIBFDT)
|
#include <asm/fsl_i2c.h>
|
||||||
#include <libfdt.h>
|
|
||||||
#include <fdt_support.h>
|
|
||||||
#endif
|
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
#ifdef CONFIG_PCI
|
static struct pci_region pci1_regions[] = {
|
||||||
|
{
|
||||||
/* System RAM mapped to PCI space */
|
bus_start: CONFIG_SYS_PCI1_MEM_BASE,
|
||||||
#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
|
phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
|
||||||
#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
|
size: CONFIG_SYS_PCI1_MEM_SIZE,
|
||||||
|
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
|
||||||
#ifndef CONFIG_PCI_PNP
|
},
|
||||||
static struct pci_config_table pci_mpc8349emds_config_table[] = {
|
{
|
||||||
{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
|
bus_start: CONFIG_SYS_PCI1_IO_BASE,
|
||||||
PCI_IDSEL_NUMBER, PCI_ANY_ID,
|
phys_start: CONFIG_SYS_PCI1_IO_PHYS,
|
||||||
pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
|
size: CONFIG_SYS_PCI1_IO_SIZE,
|
||||||
PCI_ENET0_MEMADDR,
|
flags: PCI_REGION_IO
|
||||||
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
|
},
|
||||||
}
|
{
|
||||||
|
bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
|
||||||
|
phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
|
||||||
|
size: CONFIG_SYS_PCI1_MMIO_SIZE,
|
||||||
|
flags: PCI_REGION_MEM
|
||||||
},
|
},
|
||||||
{}
|
|
||||||
};
|
|
||||||
#endif
|
|
||||||
|
|
||||||
static struct pci_controller pci_hose[] = {
|
|
||||||
{
|
|
||||||
#ifndef CONFIG_PCI_PNP
|
|
||||||
config_table:pci_mpc8349emds_config_table,
|
|
||||||
#endif
|
|
||||||
},
|
|
||||||
{
|
|
||||||
#ifndef CONFIG_PCI_PNP
|
|
||||||
config_table:pci_mpc8349emds_config_table,
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
};
|
};
|
||||||
|
|
||||||
/**************************************************************************
|
/*
|
||||||
* pci_init_board()
|
* pci_init_board()
|
||||||
*
|
*
|
||||||
* NOTICE: PCI2 is not supported. There is only one
|
* NOTICE: PCI2 is not supported. There is only one
|
||||||
@ -79,288 +66,23 @@ static struct pci_controller pci_hose[] = {
|
|||||||
void
|
void
|
||||||
pci_init_board(void)
|
pci_init_board(void)
|
||||||
{
|
{
|
||||||
volatile immap_t * immr;
|
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
|
||||||
volatile clk83xx_t * clk;
|
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
|
||||||
volatile law83xx_t * pci_law;
|
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
|
||||||
volatile pot83xx_t * pci_pot;
|
struct pci_region *reg[] = { pci1_regions };
|
||||||
volatile pcictrl83xx_t * pci_ctrl;
|
|
||||||
volatile pciconf83xx_t * pci_conf;
|
|
||||||
u16 reg16;
|
|
||||||
u32 reg32;
|
|
||||||
u32 dev;
|
|
||||||
struct pci_controller * hose;
|
|
||||||
|
|
||||||
immr = (immap_t *)CONFIG_SYS_IMMR;
|
/* Enable all 8 PCI_CLK_OUTPUTS */
|
||||||
clk = (clk83xx_t *)&immr->clk;
|
|
||||||
pci_law = immr->sysconf.pcilaw;
|
|
||||||
pci_pot = immr->ios.pot;
|
|
||||||
pci_ctrl = immr->pci_ctrl;
|
|
||||||
pci_conf = immr->pci_conf;
|
|
||||||
|
|
||||||
hose = &pci_hose[0];
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
|
|
||||||
*/
|
|
||||||
|
|
||||||
reg32 = clk->occr;
|
|
||||||
udelay(2000);
|
|
||||||
clk->occr = 0xff000000;
|
clk->occr = 0xff000000;
|
||||||
udelay(2000);
|
udelay(2000);
|
||||||
|
|
||||||
/*
|
/* Configure PCI Local Access Windows */
|
||||||
* Release PCI RST Output signal
|
|
||||||
*/
|
|
||||||
pci_ctrl[0].gcr = 0;
|
|
||||||
udelay(2000);
|
|
||||||
pci_ctrl[0].gcr = 1;
|
|
||||||
|
|
||||||
#ifdef CONFIG_MPC83XX_PCI2
|
|
||||||
pci_ctrl[1].gcr = 0;
|
|
||||||
udelay(2000);
|
|
||||||
pci_ctrl[1].gcr = 1;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* We need to wait at least a 1sec based on PCI specs */
|
|
||||||
{
|
|
||||||
int i;
|
|
||||||
|
|
||||||
for (i = 0; i < 1000; ++i)
|
|
||||||
udelay (1000);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Configure PCI Local Access Windows
|
|
||||||
*/
|
|
||||||
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
|
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
|
||||||
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
|
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
|
||||||
|
|
||||||
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
|
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
|
||||||
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
|
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
|
||||||
|
|
||||||
/*
|
udelay(2000);
|
||||||
* Configure PCI Outbound Translation Windows
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* PCI1 mem space - prefetch */
|
|
||||||
pci_pot[0].potar = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
|
|
||||||
pci_pot[0].pobar = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
|
|
||||||
pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
|
|
||||||
|
|
||||||
/* PCI1 IO space */
|
|
||||||
pci_pot[1].potar = (CONFIG_SYS_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
|
|
||||||
pci_pot[1].pobar = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
|
|
||||||
pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
|
|
||||||
|
|
||||||
/* PCI1 mmio - non-prefetch mem space */
|
|
||||||
pci_pot[2].potar = (CONFIG_SYS_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
|
|
||||||
pci_pot[2].pobar = (CONFIG_SYS_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
|
|
||||||
pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Configure PCI Inbound Translation Windows
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* we need RAM mapped to PCI space for the devices to
|
|
||||||
* access main memory */
|
|
||||||
pci_ctrl[0].pitar1 = 0x0;
|
|
||||||
pci_ctrl[0].pibar1 = 0x0;
|
|
||||||
pci_ctrl[0].piebar1 = 0x0;
|
|
||||||
pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
|
|
||||||
|
|
||||||
hose->first_busno = 0;
|
|
||||||
hose->last_busno = 0xff;
|
|
||||||
|
|
||||||
/* PCI memory prefetch space */
|
|
||||||
pci_set_region(hose->regions + 0,
|
|
||||||
CONFIG_SYS_PCI1_MEM_BASE,
|
|
||||||
CONFIG_SYS_PCI1_MEM_PHYS,
|
|
||||||
CONFIG_SYS_PCI1_MEM_SIZE,
|
|
||||||
PCI_REGION_MEM|PCI_REGION_PREFETCH);
|
|
||||||
|
|
||||||
/* PCI memory space */
|
|
||||||
pci_set_region(hose->regions + 1,
|
|
||||||
CONFIG_SYS_PCI1_MMIO_BASE,
|
|
||||||
CONFIG_SYS_PCI1_MMIO_PHYS,
|
|
||||||
CONFIG_SYS_PCI1_MMIO_SIZE,
|
|
||||||
PCI_REGION_MEM);
|
|
||||||
|
|
||||||
/* PCI IO space */
|
|
||||||
pci_set_region(hose->regions + 2,
|
|
||||||
CONFIG_SYS_PCI1_IO_BASE,
|
|
||||||
CONFIG_SYS_PCI1_IO_PHYS,
|
|
||||||
CONFIG_SYS_PCI1_IO_SIZE,
|
|
||||||
PCI_REGION_IO);
|
|
||||||
|
|
||||||
/* System memory space */
|
|
||||||
pci_set_region(hose->regions + 3,
|
|
||||||
CONFIG_PCI_SYS_MEM_BUS,
|
|
||||||
CONFIG_PCI_SYS_MEM_PHYS,
|
|
||||||
gd->ram_size,
|
|
||||||
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
|
|
||||||
|
|
||||||
hose->region_count = 4;
|
|
||||||
|
|
||||||
pci_setup_indirect(hose,
|
|
||||||
(CONFIG_SYS_IMMR+0x8300),
|
|
||||||
(CONFIG_SYS_IMMR+0x8304));
|
|
||||||
|
|
||||||
pci_register_hose(hose);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Write to Command register
|
|
||||||
*/
|
|
||||||
reg16 = 0xff;
|
|
||||||
dev = PCI_BDF(hose->first_busno, 0, 0);
|
|
||||||
pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
|
|
||||||
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
|
|
||||||
pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Clear non-reserved bits in status register.
|
|
||||||
*/
|
|
||||||
pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
|
|
||||||
pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
|
|
||||||
pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
|
|
||||||
|
|
||||||
#ifdef CONFIG_PCI_SCAN_SHOW
|
|
||||||
printf("PCI: Bus Dev VenId DevId Class Int\n");
|
|
||||||
#endif
|
|
||||||
/*
|
|
||||||
* Hose scan.
|
|
||||||
*/
|
|
||||||
hose->last_busno = pci_hose_scan(hose);
|
|
||||||
|
|
||||||
#ifdef CONFIG_MPC83XX_PCI2
|
|
||||||
hose = &pci_hose[1];
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Configure PCI Outbound Translation Windows
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* PCI2 mem space - prefetch */
|
|
||||||
pci_pot[3].potar = (CONFIG_SYS_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
|
|
||||||
pci_pot[3].pobar = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
|
|
||||||
pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
|
|
||||||
|
|
||||||
/* PCI2 IO space */
|
|
||||||
pci_pot[4].potar = (CONFIG_SYS_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
|
|
||||||
pci_pot[4].pobar = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
|
|
||||||
pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
|
|
||||||
|
|
||||||
/* PCI2 mmio - non-prefetch mem space */
|
|
||||||
pci_pot[5].potar = (CONFIG_SYS_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
|
|
||||||
pci_pot[5].pobar = (CONFIG_SYS_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
|
|
||||||
pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Configure PCI Inbound Translation Windows
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* we need RAM mapped to PCI space for the devices to
|
|
||||||
* access main memory */
|
|
||||||
pci_ctrl[1].pitar1 = 0x0;
|
|
||||||
pci_ctrl[1].pibar1 = 0x0;
|
|
||||||
pci_ctrl[1].piebar1 = 0x0;
|
|
||||||
pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
|
|
||||||
|
|
||||||
hose->first_busno = pci_hose[0].last_busno + 1;
|
|
||||||
hose->last_busno = 0xff;
|
|
||||||
|
|
||||||
/* PCI memory prefetch space */
|
|
||||||
pci_set_region(hose->regions + 0,
|
|
||||||
CONFIG_SYS_PCI2_MEM_BASE,
|
|
||||||
CONFIG_SYS_PCI2_MEM_PHYS,
|
|
||||||
CONFIG_SYS_PCI2_MEM_SIZE,
|
|
||||||
PCI_REGION_MEM|PCI_REGION_PREFETCH);
|
|
||||||
|
|
||||||
/* PCI memory space */
|
|
||||||
pci_set_region(hose->regions + 1,
|
|
||||||
CONFIG_SYS_PCI2_MMIO_BASE,
|
|
||||||
CONFIG_SYS_PCI2_MMIO_PHYS,
|
|
||||||
CONFIG_SYS_PCI2_MMIO_SIZE,
|
|
||||||
PCI_REGION_MEM);
|
|
||||||
|
|
||||||
/* PCI IO space */
|
|
||||||
pci_set_region(hose->regions + 2,
|
|
||||||
CONFIG_SYS_PCI2_IO_BASE,
|
|
||||||
CONFIG_SYS_PCI2_IO_PHYS,
|
|
||||||
CONFIG_SYS_PCI2_IO_SIZE,
|
|
||||||
PCI_REGION_IO);
|
|
||||||
|
|
||||||
/* System memory space */
|
|
||||||
pci_set_region(hose->regions + 3,
|
|
||||||
CONFIG_PCI_SYS_MEM_BUS,
|
|
||||||
CONFIG_PCI_SYS_MEM_PHYS,
|
|
||||||
gd->ram_size,
|
|
||||||
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
|
|
||||||
|
|
||||||
hose->region_count = 4;
|
|
||||||
|
|
||||||
pci_setup_indirect(hose,
|
|
||||||
(CONFIG_SYS_IMMR+0x8380),
|
|
||||||
(CONFIG_SYS_IMMR+0x8384));
|
|
||||||
|
|
||||||
pci_register_hose(hose);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Write to Command register
|
|
||||||
*/
|
|
||||||
reg16 = 0xff;
|
|
||||||
dev = PCI_BDF(hose->first_busno, 0, 0);
|
|
||||||
pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
|
|
||||||
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
|
|
||||||
pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Clear non-reserved bits in status register.
|
|
||||||
*/
|
|
||||||
pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
|
|
||||||
pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
|
|
||||||
pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Hose scan.
|
|
||||||
*/
|
|
||||||
hose->last_busno = pci_hose_scan(hose);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
mpc83xx_pci_init(1, reg, 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
#if defined(CONFIG_OF_LIBFDT)
|
|
||||||
void ft_pci_setup(void *blob, bd_t *bd)
|
|
||||||
{
|
|
||||||
int nodeoffset;
|
|
||||||
int tmp[2];
|
|
||||||
const char *path;
|
|
||||||
|
|
||||||
nodeoffset = fdt_path_offset(blob, "/aliases");
|
|
||||||
if (nodeoffset >= 0) {
|
|
||||||
path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
|
|
||||||
if (path) {
|
|
||||||
tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
|
|
||||||
tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
|
|
||||||
do_fixup_by_path(blob, path, "bus-range",
|
|
||||||
&tmp, sizeof(tmp), 1);
|
|
||||||
|
|
||||||
tmp[0] = cpu_to_be32(gd->pci_clk);
|
|
||||||
do_fixup_by_path(blob, path, "clock-frequency",
|
|
||||||
&tmp, sizeof(tmp[0]), 1);
|
|
||||||
}
|
|
||||||
#ifdef CONFIG_MPC83XX_PCI2
|
|
||||||
path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
|
|
||||||
if (path) {
|
|
||||||
tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
|
|
||||||
tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
|
|
||||||
do_fixup_by_path(blob, path, "bus-range",
|
|
||||||
&tmp, sizeof(tmp), 1);
|
|
||||||
|
|
||||||
tmp[0] = cpu_to_be32(gd->pci_clk);
|
|
||||||
do_fixup_by_path(blob, path, "clock-frequency",
|
|
||||||
&tmp, sizeof(tmp[0]), 1);
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
}
|
|
||||||
#endif /* CONFIG_OF_LIBFDT */
|
|
||||||
#endif /* CONFIG_PCI */
|
|
||||||
|
@ -27,8 +27,10 @@ include $(TOPDIR)/config.mk
|
|||||||
|
|
||||||
LIB = $(obj)lib$(BOARD).a
|
LIB = $(obj)lib$(BOARD).a
|
||||||
|
|
||||||
COBJS = $(BOARD).o pci.o
|
COBJS-y += $(BOARD).o
|
||||||
|
COBJS-$(CONFIG_PCI) += pci.o
|
||||||
|
|
||||||
|
COBJS := $(COBJS-y)
|
||||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||||
OBJS := $(addprefix $(obj),$(COBJS))
|
OBJS := $(addprefix $(obj),$(COBJS))
|
||||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||||
|
@ -1,6 +1,7 @@
|
|||||||
/*
|
/*
|
||||||
* (C) Copyright 2005
|
* (C) Copyright 2005
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
|
||||||
*
|
*
|
||||||
* See file CREDITS for list of people who contributed to this
|
* See file CREDITS for list of people who contributed to this
|
||||||
* project.
|
* project.
|
||||||
@ -23,45 +24,37 @@
|
|||||||
*/
|
*/
|
||||||
|
|
||||||
#include <asm/mmu.h>
|
#include <asm/mmu.h>
|
||||||
|
#include <asm/io.h>
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <asm/global_data.h>
|
#include <mpc83xx.h>
|
||||||
#include <pci.h>
|
#include <pci.h>
|
||||||
#include <asm/mpc8349_pci.h>
|
#include <i2c.h>
|
||||||
#if defined(CONFIG_OF_LIBFDT)
|
#include <asm/fsl_i2c.h>
|
||||||
#include <libfdt.h>
|
|
||||||
#include <fdt_support.h>
|
|
||||||
#endif
|
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
#ifdef CONFIG_PCI
|
static struct pci_region pci1_regions[] = {
|
||||||
|
{
|
||||||
/* System RAM mapped to PCI space */
|
bus_start: CONFIG_SYS_PCI1_MEM_BASE,
|
||||||
#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
|
phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
|
||||||
#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
|
size: CONFIG_SYS_PCI1_MEM_SIZE,
|
||||||
#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
|
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
|
||||||
|
},
|
||||||
#ifndef CONFIG_PCI_PNP
|
{
|
||||||
static struct pci_config_table pci_tqm834x_config_table[] = {
|
bus_start: CONFIG_SYS_PCI1_IO_BASE,
|
||||||
{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
|
phys_start: CONFIG_SYS_PCI1_IO_PHYS,
|
||||||
PCI_IDSEL_NUMBER, PCI_ANY_ID,
|
size: CONFIG_SYS_PCI1_IO_SIZE,
|
||||||
pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
|
flags: PCI_REGION_IO
|
||||||
PCI_ENET0_MEMADDR,
|
},
|
||||||
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
|
{
|
||||||
}
|
bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
|
||||||
|
phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
|
||||||
|
size: CONFIG_SYS_PCI1_MMIO_SIZE,
|
||||||
|
flags: PCI_REGION_MEM
|
||||||
},
|
},
|
||||||
{}
|
|
||||||
};
|
|
||||||
#endif
|
|
||||||
|
|
||||||
static struct pci_controller pci1_hose = {
|
|
||||||
#ifndef CONFIG_PCI_PNP
|
|
||||||
config_table:pci_tqm834x_config_table,
|
|
||||||
#endif
|
|
||||||
};
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
/**************************************************************************
|
|
||||||
* pci_init_board()
|
* pci_init_board()
|
||||||
*
|
*
|
||||||
* NOTICE: MPC8349 internally has two PCI controllers (PCI1 and PCI2) but since
|
* NOTICE: MPC8349 internally has two PCI controllers (PCI1 and PCI2) but since
|
||||||
@ -76,30 +69,15 @@ static struct pci_controller pci1_hose = {
|
|||||||
void
|
void
|
||||||
pci_init_board(void)
|
pci_init_board(void)
|
||||||
{
|
{
|
||||||
volatile immap_t * immr;
|
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
|
||||||
volatile clk83xx_t * clk;
|
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
|
||||||
volatile law83xx_t * pci_law;
|
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
|
||||||
volatile pot83xx_t * pci_pot;
|
struct pci_region *reg[] = { pci1_regions };
|
||||||
volatile pcictrl83xx_t * pci_ctrl;
|
|
||||||
volatile pciconf83xx_t * pci_conf;
|
|
||||||
u16 reg16;
|
|
||||||
u32 reg32;
|
u32 reg32;
|
||||||
struct pci_controller * hose;
|
|
||||||
|
|
||||||
immr = (immap_t *)CONFIG_SYS_IMMR;
|
|
||||||
clk = (clk83xx_t *)&immr->clk;
|
|
||||||
pci_law = immr->sysconf.pcilaw;
|
|
||||||
pci_pot = immr->ios.pot;
|
|
||||||
pci_ctrl = immr->pci_ctrl;
|
|
||||||
pci_conf = immr->pci_conf;
|
|
||||||
|
|
||||||
hose = &pci1_hose;
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Configure PCI controller and PCI_CLK_OUTPUT
|
* Configure PCI controller and PCI_CLK_OUTPUT
|
||||||
*/
|
*
|
||||||
|
|
||||||
/*
|
|
||||||
* WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one
|
* WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one
|
||||||
* line actually used for clocking all external PCI devices in TQM83xx.
|
* line actually used for clocking all external PCI devices in TQM83xx.
|
||||||
* Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for
|
* Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for
|
||||||
@ -125,141 +103,14 @@ pci_init_board(void)
|
|||||||
clk->occr = reg32;
|
clk->occr = reg32;
|
||||||
udelay(2000);
|
udelay(2000);
|
||||||
|
|
||||||
/*
|
/* Configure PCI Local Access Windows */
|
||||||
* Release PCI RST Output signal
|
|
||||||
*/
|
|
||||||
pci_ctrl[0].gcr = 0;
|
|
||||||
udelay(2000);
|
|
||||||
pci_ctrl[0].gcr = 1;
|
|
||||||
udelay(2000);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Configure PCI Local Access Windows
|
|
||||||
*/
|
|
||||||
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
|
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
|
||||||
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
|
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
|
||||||
|
|
||||||
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
|
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
|
||||||
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M;
|
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M;
|
||||||
|
|
||||||
/*
|
udelay(2000);
|
||||||
* Configure PCI Outbound Translation Windows
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* PCI1 mem space */
|
mpc83xx_pci_init(1, reg, 0);
|
||||||
pci_pot[0].potar = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
|
|
||||||
pci_pot[0].pobar = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
|
|
||||||
pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK);
|
|
||||||
|
|
||||||
/* PCI1 IO space */
|
|
||||||
pci_pot[1].potar = (CONFIG_SYS_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
|
|
||||||
pci_pot[1].pobar = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
|
|
||||||
pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Configure PCI Inbound Translation Windows
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* we need RAM mapped to PCI space for the devices to
|
|
||||||
* access main memory */
|
|
||||||
pci_ctrl[0].pitar1 = 0x0;
|
|
||||||
pci_ctrl[0].pibar1 = 0x0;
|
|
||||||
pci_ctrl[0].piebar1 = 0x0;
|
|
||||||
pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_256M;
|
|
||||||
|
|
||||||
hose->first_busno = 0;
|
|
||||||
hose->last_busno = 0xff;
|
|
||||||
|
|
||||||
/* PCI memory space */
|
|
||||||
pci_set_region(hose->regions + 0,
|
|
||||||
CONFIG_SYS_PCI1_MEM_BASE,
|
|
||||||
CONFIG_SYS_PCI1_MEM_PHYS,
|
|
||||||
CONFIG_SYS_PCI1_MEM_SIZE,
|
|
||||||
PCI_REGION_MEM);
|
|
||||||
|
|
||||||
/* PCI IO space */
|
|
||||||
pci_set_region(hose->regions + 1,
|
|
||||||
CONFIG_SYS_PCI1_IO_BASE,
|
|
||||||
CONFIG_SYS_PCI1_IO_PHYS,
|
|
||||||
CONFIG_SYS_PCI1_IO_SIZE,
|
|
||||||
PCI_REGION_IO);
|
|
||||||
|
|
||||||
/* System memory space */
|
|
||||||
pci_set_region(hose->regions + 2,
|
|
||||||
CONFIG_PCI_SYS_MEM_BUS,
|
|
||||||
CONFIG_PCI_SYS_MEM_PHYS,
|
|
||||||
CONFIG_PCI_SYS_MEM_SIZE,
|
|
||||||
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
|
|
||||||
|
|
||||||
hose->region_count = 3;
|
|
||||||
|
|
||||||
pci_setup_indirect(hose,
|
|
||||||
(CONFIG_SYS_IMMR+0x8300),
|
|
||||||
(CONFIG_SYS_IMMR+0x8304));
|
|
||||||
|
|
||||||
pci_register_hose(hose);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Write to Command register
|
|
||||||
*/
|
|
||||||
reg16 = 0xff;
|
|
||||||
pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND,
|
|
||||||
®16);
|
|
||||||
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
|
|
||||||
pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND,
|
|
||||||
reg16);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Clear non-reserved bits in status register.
|
|
||||||
*/
|
|
||||||
pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS,
|
|
||||||
0xffff);
|
|
||||||
pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER,
|
|
||||||
0x80);
|
|
||||||
|
|
||||||
#ifdef CONFIG_PCI_SCAN_SHOW
|
|
||||||
printf("PCI: Bus Dev VenId DevId Class Int\n");
|
|
||||||
#endif
|
|
||||||
/*
|
|
||||||
* Hose scan.
|
|
||||||
*/
|
|
||||||
hose->last_busno = pci_hose_scan(hose);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
#if defined(CONFIG_OF_LIBFDT)
|
|
||||||
void ft_pci_setup(void *blob, bd_t *bd)
|
|
||||||
{
|
|
||||||
int nodeoffset;
|
|
||||||
int tmp[2];
|
|
||||||
const char *path;
|
|
||||||
|
|
||||||
nodeoffset = fdt_path_offset(blob, "/aliases");
|
|
||||||
if (nodeoffset >= 0) {
|
|
||||||
path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
|
|
||||||
if (path) {
|
|
||||||
tmp[0] = cpu_to_be32(pci1_hose.first_busno);
|
|
||||||
tmp[1] = cpu_to_be32(pci1_hose.last_busno);
|
|
||||||
do_fixup_by_path(blob, path, "bus-range",
|
|
||||||
&tmp, sizeof(tmp), 1);
|
|
||||||
|
|
||||||
tmp[0] = cpu_to_be32(gd->pci_clk);
|
|
||||||
do_fixup_by_path(blob, path, "clock-frequency",
|
|
||||||
&tmp, sizeof(tmp[0]), 1);
|
|
||||||
}
|
|
||||||
#ifdef CONFIG_MPC83XX_PCI2
|
|
||||||
path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
|
|
||||||
if (path) {
|
|
||||||
tmp[0] = cpu_to_be32(pci2_hose.first_busno);
|
|
||||||
tmp[1] = cpu_to_be32(pci2_hose.last_busno);
|
|
||||||
do_fixup_by_path(blob, path, "bus-range",
|
|
||||||
&tmp, sizeof(tmp), 1);
|
|
||||||
|
|
||||||
tmp[0] = cpu_to_be32(gd->pci_clk);
|
|
||||||
do_fixup_by_path(blob, path, "clock-frequency",
|
|
||||||
&tmp, sizeof(tmp[0]), 1);
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
}
|
|
||||||
#endif /* CONFIG_OF_LIBFDT */
|
|
||||||
#endif /* CONFIG_PCI */
|
|
||||||
|
@ -315,15 +315,15 @@
|
|||||||
* General PCI
|
* General PCI
|
||||||
* Addresses are mapped 1-1.
|
* Addresses are mapped 1-1.
|
||||||
*/
|
*/
|
||||||
#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
|
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
|
||||||
#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
|
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
|
||||||
#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
|
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
|
||||||
#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
|
#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
|
||||||
#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
|
#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
|
||||||
#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
|
#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
|
||||||
#define CONFIG_SYS_PCI_IO_BASE 0x00000000
|
#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
|
||||||
#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
|
#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
|
||||||
#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
|
#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
|
||||||
|
|
||||||
#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
|
#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
|
||||||
#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
|
#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
|
||||||
@ -334,6 +334,8 @@
|
|||||||
|
|
||||||
#define CONFIG_NET_MULTI
|
#define CONFIG_NET_MULTI
|
||||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||||
|
#define CONFIG_83XX_GENERIC_PCI
|
||||||
|
#define CONFIG_83XX_PCI_STREAMING
|
||||||
|
|
||||||
#undef CONFIG_EEPRO100
|
#undef CONFIG_EEPRO100
|
||||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||||
@ -500,14 +502,14 @@
|
|||||||
|
|
||||||
#ifdef CONFIG_PCI
|
#ifdef CONFIG_PCI
|
||||||
/* PCI MEM space: cacheable */
|
/* PCI MEM space: cacheable */
|
||||||
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
|
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||||
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
|
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||||
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
|
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
|
||||||
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
|
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
|
||||||
/* PCI MMIO space: cache-inhibit and guarded */
|
/* PCI MMIO space: cache-inhibit and guarded */
|
||||||
#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
|
#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
|
||||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||||
#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
|
#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||||
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
|
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
|
||||||
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
|
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
|
||||||
#else
|
#else
|
||||||
@ -536,9 +538,7 @@
|
|||||||
|
|
||||||
/*
|
/*
|
||||||
* Environment Configuration
|
* Environment Configuration
|
||||||
*/
|
*/ #define CONFIG_ENV_OVERWRITE
|
||||||
|
|
||||||
#define CONFIG_ENV_OVERWRITE
|
|
||||||
|
|
||||||
#if defined(CONFIG_UEC_ETH)
|
#if defined(CONFIG_UEC_ETH)
|
||||||
#define CONFIG_HAS_ETH0
|
#define CONFIG_HAS_ETH0
|
||||||
|
@ -382,6 +382,7 @@ boards, we say we have two, but don't display a message if we find only one. */
|
|||||||
|
|
||||||
#define CONFIG_NET_MULTI
|
#define CONFIG_NET_MULTI
|
||||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||||
|
#define CONFIG_83XX_GENERIC_PCI
|
||||||
|
|
||||||
#ifndef CONFIG_PCI_PNP
|
#ifndef CONFIG_PCI_PNP
|
||||||
#define PCI_ENET0_IOADDR 0x00000000
|
#define PCI_ENET0_IOADDR 0x00000000
|
||||||
|
@ -350,15 +350,15 @@
|
|||||||
* General PCI
|
* General PCI
|
||||||
* Addresses are mapped 1-1.
|
* Addresses are mapped 1-1.
|
||||||
*/
|
*/
|
||||||
#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
|
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
|
||||||
#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
|
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
|
||||||
#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
|
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
|
||||||
#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
|
#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
|
||||||
#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
|
#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
|
||||||
#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
|
#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
|
||||||
#define CONFIG_SYS_PCI_IO_BASE 0x00000000
|
#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
|
||||||
#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
|
#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
|
||||||
#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
|
#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
|
||||||
|
|
||||||
#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
|
#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
|
||||||
#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
|
#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
|
||||||
@ -369,6 +369,8 @@
|
|||||||
|
|
||||||
#define CONFIG_NET_MULTI
|
#define CONFIG_NET_MULTI
|
||||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||||
|
#define CONFIG_83XX_GENERIC_PCI
|
||||||
|
#define CONFIG_83XX_PCI_STREAMING
|
||||||
|
|
||||||
#undef CONFIG_EEPRO100
|
#undef CONFIG_EEPRO100
|
||||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||||
@ -539,14 +541,14 @@
|
|||||||
|
|
||||||
#ifdef CONFIG_PCI
|
#ifdef CONFIG_PCI
|
||||||
/* PCI MEM space: cacheable */
|
/* PCI MEM space: cacheable */
|
||||||
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
|
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||||
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
|
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||||
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
|
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
|
||||||
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
|
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
|
||||||
/* PCI MMIO space: cache-inhibit and guarded */
|
/* PCI MMIO space: cache-inhibit and guarded */
|
||||||
#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
|
#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
|
||||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||||
#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
|
#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||||
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
|
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
|
||||||
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
|
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
|
||||||
#else
|
#else
|
||||||
|
@ -247,12 +247,16 @@ extern int tqm834x_num_flash_banks;
|
|||||||
#if defined(CONFIG_PCI)
|
#if defined(CONFIG_PCI)
|
||||||
|
|
||||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||||
|
#define CONFIG_83XX_GENERIC_PCI
|
||||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||||
|
|
||||||
/* PCI1 host bridge */
|
/* PCI1 host bridge */
|
||||||
#define CONFIG_SYS_PCI1_MEM_BASE 0xc0000000
|
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
|
||||||
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
|
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
|
||||||
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
|
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
|
||||||
|
#define CONFIG_SYS_PCI1_MMIO_BASE (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
|
||||||
|
#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
|
||||||
|
#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
|
||||||
#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
|
#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
|
||||||
#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
|
#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
|
||||||
#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
|
#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
|
||||||
@ -418,10 +422,10 @@ extern int tqm834x_num_flash_banks;
|
|||||||
#ifdef CONFIG_PCI
|
#ifdef CONFIG_PCI
|
||||||
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
|
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||||
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
|
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||||
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
|
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_MEMCOHERENCE | BATL_GUARDEDSTORAGE)
|
||||||
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
|
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||||
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||||
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP)
|
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
|
||||||
#else
|
#else
|
||||||
#define CONFIG_SYS_IBAT3L (0)
|
#define CONFIG_SYS_IBAT3L (0)
|
||||||
#define CONFIG_SYS_IBAT3U (0)
|
#define CONFIG_SYS_IBAT3U (0)
|
||||||
|
@ -329,6 +329,7 @@
|
|||||||
|
|
||||||
#define CONFIG_NET_MULTI
|
#define CONFIG_NET_MULTI
|
||||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||||
|
#define CONFIG_83XX_GENERIC_PCI
|
||||||
|
|
||||||
#undef CONFIG_EEPRO100
|
#undef CONFIG_EEPRO100
|
||||||
#undef CONFIG_TULIP
|
#undef CONFIG_TULIP
|
||||||
|
Loading…
Reference in New Issue
Block a user