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https://github.com/brain-hackers/u-boot-brain
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MIPS: add support for Broadcom MIPS BCM3380 SoC family
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Álvaro Fernández Rojas
Daniel Schwierzeck
parent
603058f4ab
commit
23a2168398
154
arch/mips/dts/brcm,bcm3380.dtsi
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154
arch/mips/dts/brcm,bcm3380.dtsi
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/*
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* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <dt-bindings/clock/bcm3380-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/reset/bcm3380-reset.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "brcm,bcm3380";
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cpus {
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reg = <0x14e00000 0x4>;
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#address-cells = <1>;
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#size-cells = <0>;
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u-boot,dm-pre-reloc;
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cpu@0 {
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compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
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device_type = "cpu";
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reg = <0>;
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u-boot,dm-pre-reloc;
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};
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cpu@1 {
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compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
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device_type = "cpu";
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reg = <1>;
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u-boot,dm-pre-reloc;
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};
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};
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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u-boot,dm-pre-reloc;
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periph_osc: periph-osc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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u-boot,dm-pre-reloc;
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};
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periph_clk0: periph-clk@14e00004 {
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compatible = "brcm,bcm6345-clk";
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reg = <0x14e00004 0x4>;
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#clock-cells = <1>;
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};
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periph_clk1: periph-clk@14e00008 {
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compatible = "brcm,bcm6345-clk";
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reg = <0x14e00008 0x4>;
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#clock-cells = <1>;
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};
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};
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ubus {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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u-boot,dm-pre-reloc;
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memory-controller@12000000 {
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compatible = "brcm,bcm6328-mc";
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reg = <0x12000000 0x1000>;
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u-boot,dm-pre-reloc;
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};
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periph_rst0: reset-controller@14e0008c {
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compatible = "brcm,bcm6345-reset";
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reg = <0x14e0008c 0x4>;
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#reset-cells = <1>;
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};
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periph_rst1: reset-controller@14e00090 {
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compatible = "brcm,bcm6345-reset";
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reg = <0x14e00090 0x4>;
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#reset-cells = <1>;
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};
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pll_cntl: syscon@14e00094 {
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compatible = "syscon";
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reg = <0x14e00094 0x4>;
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};
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syscon-reboot {
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compatible = "syscon-reboot";
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regmap = <&pll_cntl>;
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offset = <0x0>;
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mask = <0x1>;
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};
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wdt: watchdog@14e000dc {
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compatible = "brcm,bcm6345-wdt";
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reg = <0x14e000dc 0xc>;
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clocks = <&periph_osc>;
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};
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&wdt>;
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};
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gpio0: gpio-controller@14e00100 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x14e00100 0x4>, <0x14e00108 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio1: gpio-controller@14e00104 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x14e00104 0x4>, <0x14e0010c 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <3>;
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status = "disabled";
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};
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uart0: serial@14e00200 {
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compatible = "brcm,bcm6345-uart";
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reg = <0x14e00200 0x18>;
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clocks = <&periph_osc>;
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status = "disabled";
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};
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uart1: serial@14e00220 {
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compatible = "brcm,bcm6345-uart";
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reg = <0x14e00220 0x18>;
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clocks = <&periph_osc>;
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status = "disabled";
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};
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leds: led-controller@14e00f00 {
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compatible = "brcm,bcm6328-leds";
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reg = <0x14e00f00 0x1c>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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};
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@ -2,6 +2,7 @@ menu "Broadcom MIPS platforms"
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depends on ARCH_BMIPS
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config SYS_SOC
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default "bcm3380" if SOC_BMIPS_BCM3380
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default "bcm6328" if SOC_BMIPS_BCM6328
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default "bcm6348" if SOC_BMIPS_BCM6348
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default "bcm6358" if SOC_BMIPS_BCM6358
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@ -10,6 +11,17 @@ config SYS_SOC
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choice
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prompt "Broadcom MIPS SoC select"
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config SOC_BMIPS_BCM3380
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bool "BMIPS BCM3380 family"
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select SUPPORTS_BIG_ENDIAN
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select SUPPORTS_CPU_MIPS32_R1
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select MIPS_TUNE_4KC
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select MIPS_L1_CACHE_SHIFT_4
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select SWAP_IO_SPACE
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select SYSRESET_WATCHDOG
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help
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This supports BMIPS BCM3380 family.
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config SOC_BMIPS_BCM6328
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bool "BMIPS BCM6328 family"
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select SUPPORTS_BIG_ENDIAN
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25
include/configs/bmips_bcm3380.h
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25
include/configs/bmips_bcm3380.h
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@ -0,0 +1,25 @@
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/*
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* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_BMIPS_BCM3380_H
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#define __CONFIG_BMIPS_BCM3380_H
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/* CPU */
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#define CONFIG_SYS_MIPS_TIMER_FREQ 166500000
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/* RAM */
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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/* U-Boot */
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#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
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#if defined(CONFIG_BMIPS_BOOT_RAM)
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_SYS_INIT_SP_OFFSET 0x2000
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#endif
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#endif /* __CONFIG_BMIPS_BCM3380_H */
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23
include/dt-bindings/clock/bcm3380-clock.h
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23
include/dt-bindings/clock/bcm3380-clock.h
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/*
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* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
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*
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* Derived from Broadcom GPL Source Code:
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* Copyright (C) Broadcom Corporation
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __DT_BINDINGS_CLOCK_BCM3380_H
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#define __DT_BINDINGS_CLOCK_BCM3380_H
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#define BCM3380_CLK0_DDR 0
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#define BCM3380_CLK0_FPM 1
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#define BCM3380_CLK0_CRYPTO 2
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#define BCM3380_CLK0_EPHY 3
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#define BCM3380_CLK0_PCIE 16
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#define BCM3380_CLK0_SPI 17
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#define BCM3380_CLK0_ENET0 18
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#define BCM3380_CLK0_ENET1 19
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#define BCM3380_CLK0_PCM 27
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#endif /* __DT_BINDINGS_CLOCK_BCM3380_H */
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16
include/dt-bindings/reset/bcm3380-reset.h
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16
include/dt-bindings/reset/bcm3380-reset.h
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@ -0,0 +1,16 @@
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/*
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* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
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*
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* Derived from Broadcom GPL Source Code:
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* Copyright (C) Broadcom Corporation
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __DT_BINDINGS_RESET_BCM3380_H
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#define __DT_BINDINGS_RESET_BCM3380_H
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#define BCM3380_RST0_SPI 0
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#define BCM3380_RST0_PCM 13
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#endif /* __DT_BINDINGS_RESET_BCM3380_H */
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