brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-06-09 23:36:03 +09:00
Code Issues Projects Releases Wiki Activity

spi: dw: Add SoC-specific compatible strings

Browse Source 
This adds SoC-specific compatible strings to all users of the designware
spi device. This will allow for the correct driver to be selected for each
device. Where it is publicly documented, a compatible string for the
specific device version has also been added. Devices without
publicly-documented device versions include MSCC SoCs, and Arc Socs. All
compatible strings except those for SoCFPGAs and some of the versioned
strings have been taken from Linux.

Since SSI_MAX_XFER_SIZE is determined at runtime, this is not strictly
necessary. However, it is a good cleanup and brings things closer to Linux.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
Sean Anderson 2020-10-16 18:57:50 -04:00 committed by Jagan Teki
parent ddd3450f39
commit 237e5880f8
9 changed files with 28 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arc/dts/axs10x_mb.dtsi
View File

@ -90,7 +90,7 @@
};
spi0: spi@0 {
compatible = "snps,dw-apb-ssi";
compatible = "snps,axs10x-spi", "snps,dw-apb-ssi";
reg = <0x0 0x100>;
#address-cells = <1>;
#size-cells = <0>;

2
arch/arc/dts/hsdk-common.dtsi
View File

@ -128,7 +128,7 @@
};
spi0: spi@f0020000 {
compatible = "snps,dw-apb-ssi";
compatible = "snps,hsdk-spi", "snps,dw-apb-ssi";
reg = <0xf0020000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;

6
arch/arm/dts/socfpga.dtsi
View File

@ -804,7 +804,8 @@
};
spi0: spi@fff00000 {
compatible = "snps,dw-apb-ssi";
compatible = "altr,socfpga-spi", "snps,dw-apb-ssi-3.20",
"snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfff00000 0x1000>;
@ -816,7 +817,8 @@
};
spi1: spi@fff01000 {
compatible = "snps,dw-apb-ssi";
compatible = "altr,socfpga-spi", "snps,dw-apb-ssi-3.20",
"snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfff01000 0x1000>;

6
arch/arm/dts/socfpga_agilex.dtsi
View File

@ -366,7 +366,8 @@
};
spi0: spi@ffda4000 {
compatible = "snps,dw-apb-ssi";
compatible = "intel,agilex-spi",
"snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xffda4000 0x1000>;
@ -379,7 +380,8 @@
};
spi1: spi@ffda5000 {
compatible = "snps,dw-apb-ssi";
compatible = "intel,agilex-spi",
"snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xffda5000 0x1000>;

6
arch/arm/dts/socfpga_arria10.dtsi
View File

@ -604,7 +604,8 @@
};
spi0: spi@ffda4000 {
compatible = "snps,dw-apb-ssi";
compatible = "altr,socfpga-arria10-spi",
"snps,dw-apb-ssi-3.22a", "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xffda4000 0x100>;
@ -617,7 +618,8 @@
};
spi1: spi@ffda5000 {
compatible = "snps,dw-apb-ssi";
compatible = "altr,socfpga-arria10-spi",
"snps,dw-apb-ssi-3.22a", "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xffda5000 0x100>;

6
arch/arm/dts/socfpga_stratix10.dtsi
View File

@ -268,7 +268,8 @@
};
spi0: spi@ffda4000 {
compatible = "snps,dw-apb-ssi";
compatible = "intel,stratix10-spi",
"snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xffda4000 0x1000>;
@ -281,7 +282,8 @@
};
spi1: spi@ffda5000 {
compatible = "snps,dw-apb-ssi";
compatible = "intel,stratix10-spi",
"snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xffda5000 0x1000>;

2
arch/mips/dts/mscc,jr2.dtsi
View File

@ -94,7 +94,7 @@
spi0: spi-master@101000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dw-apb-ssi";
compatible = "mscc,jaguar2-spi", "snps,dw-apb-ssi";
reg = <0x101000 0x40>;
num-chipselect = <4>;
bus-num = <0>;

2
arch/mips/dts/mscc,ocelot.dtsi
View File

@ -100,7 +100,7 @@
spi0: spi-master@101000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dw-apb-ssi";
compatible = "mscc,ocelot-spi", "snps,dw-apb-ssi";
reg = <0x101000 0x40>;
num-chipselect = <4>;
bus-num = <0>;

13
arch/riscv/dts/k210.dtsi
View File

@ -284,7 +284,8 @@
};
spi2: spi@50240000 {
compatible = "kendryte,k120-spislave",
compatible = "canaan,kendryte-k210-spi",
"snps,dw-apb-ssi-4.01",
"snps,dw-apb-ssi";
spi-slave;
reg = <0x50240000 0x100>;
@ -557,7 +558,8 @@
spi0: spi@52000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "kendryte,k210-spi",
compatible = "canaan,kendryte-k210-spi",
"snps,dw-apb-ssi-4.01",
"snps,dw-apb-ssi";
reg = <0x52000000 0x100>;
interrupts = <1>;
@ -573,7 +575,8 @@
spi1: spi@53000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "kendryte,k210-spi",
compatible = "canaan,kendryte-k210-spi",
"snps,dw-apb-ssi-4.01",
"snps,dw-apb-ssi";
reg = <0x53000000 0x100>;
interrupts = <2>;
@ -589,8 +592,8 @@
spi3: spi@54000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "kendryte,k210-spi",
"snps,dw-apb-ssi";
compatible = "canaan,kendryte-k210-ssi",
"snps,dwc-ssi-1.01a";
reg = <0x54000000 0x200>;
interrupts = <4>;
clocks = <&sysclk K210_CLK_SPI3>;