mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
iMX28: Fix ARM vector handling
This patch introduces proper ARM vector handling for i.MX28 CPU. This issue wasn't addressed because the interrupts weren't enabled on any ARMv5 core, therefore the issue wasn't noticed earlier. In previous implementation, the vectoring code used by i.MX28 CPU when an exception happened was that of the SPL. With this change, the branch target when an exception happens can be reconfigured by U-Boot. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
This commit is contained in:
Marek Vasut
Stefano Babic
parent
b68d57c310
commit
22fe68fbdc
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@ -35,6 +35,8 @@
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* 1 second delay should be plenty of time for block reset. */
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#define RESET_MAX_TIMEOUT 1000000
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@ -116,11 +118,31 @@ int mx28_reset_block(struct mx28_register *reg)
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return 0;
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}
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void mx28_fixup_vt(uint32_t start_addr)
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{
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uint32_t *vt = (uint32_t *)0x20;
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int i;
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for (i = 0; i < 8; i++)
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vt[i] = start_addr + (4 * i);
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}
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#ifdef CONFIG_ARCH_MISC_INIT
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int arch_misc_init(void)
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{
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mx28_fixup_vt(gd->relocaddr);
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return 0;
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}
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#endif
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#ifdef CONFIG_ARCH_CPU_INIT
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int arch_cpu_init(void)
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{
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struct mx28_clkctrl_regs *clkctrl_regs =
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(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
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extern uint32_t _start;
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mx28_fixup_vt((uint32_t)&_start);
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/*
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* Enable NAND clock
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@ -58,54 +58,58 @@
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.globl _start
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_start:
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b reset
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#ifdef CONFIG_SPL_BUILD
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/* No exception handlers in preloader */
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ldr pc, _hang
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ldr pc, _hang
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ldr pc, _hang
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ldr pc, _hang
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b reset
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ldr pc, _hang
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ldr pc, _hang
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b undefined_instruction
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b software_interrupt
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b prefetch_abort
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b data_abort
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b not_used
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b irq
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b fiq
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_hang:
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.word do_hang
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/* pad to 64 byte boundary */
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.word 0x12345678
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.word 0x12345678
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.word 0x12345678
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.word 0x12345678
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.word 0x12345678
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.word 0x12345678
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.word 0x12345678
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#else
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ldr pc, _undefined_instruction
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ldr pc, _software_interrupt
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ldr pc, _prefetch_abort
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ldr pc, _data_abort
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ldr pc, _not_used
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ldr pc, _irq
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ldr pc, _fiq
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/*
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* Vector table, located at address 0x20.
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* This table allows the code running AFTER SPL, the U-Boot, to install it's
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* interrupt handlers here. The problem is that the U-Boot is loaded into RAM,
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* including it's interrupt vectoring table and the table at 0x0 is still the
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* SPLs. So if interrupt happens in U-Boot, the SPLs interrupt vectoring table
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* is still used.
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*/
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_vt_reset:
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.word _reset
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_vt_undefined_instruction:
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.word _hang
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_vt_software_interrupt:
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.word _hang
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_vt_prefetch_abort:
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.word _hang
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_vt_data_abort:
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.word _hang
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_vt_not_used:
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.word _reset
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_vt_irq:
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.word _hang
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_vt_fiq:
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.word _hang
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_undefined_instruction:
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.word undefined_instruction
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_software_interrupt:
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.word software_interrupt
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_prefetch_abort:
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.word prefetch_abort
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_data_abort:
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.word data_abort
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_not_used:
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.word not_used
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_irq:
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.word irq
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_fiq:
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.word fiq
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reset:
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ldr pc, _vt_reset
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undefined_instruction:
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ldr pc, _vt_undefined_instruction
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software_interrupt:
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ldr pc, _vt_software_interrupt
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prefetch_abort:
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ldr pc, _vt_prefetch_abort
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data_abort:
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ldr pc, _vt_data_abort
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not_used:
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ldr pc, _vt_not_used
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irq:
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ldr pc, _vt_irq
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fiq:
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ldr pc, _vt_fiq
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#endif /* CONFIG_SPL_BUILD */
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.balignl 16,0xdeadbeef
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/*
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*************************************************************************
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*
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@ -162,7 +166,7 @@ IRQ_STACK_START_IN:
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* the actual reset code
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*/
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reset:
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_reset:
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/*
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* Store all registers on old stack pointer, this will allow us later to
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* return to the BootROM and let the BootROM load U-Boot into RAM.
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@ -220,177 +224,11 @@ cpu_init_crit:
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mcr p15, 0, r0, c1, c0, 0
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mov pc, lr /* back to my caller */
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.align 5
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
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#ifndef CONFIG_SPL_BUILD
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/*
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*************************************************************************
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*
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* Interrupt handling
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*
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*************************************************************************
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*/
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@
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@ IRQ stack frame.
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@
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#define S_FRAME_SIZE 72
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#define S_OLD_R0 68
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#define S_PSR 64
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#define S_PC 60
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#define S_LR 56
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#define S_SP 52
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#define S_IP 48
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#define S_FP 44
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#define S_R10 40
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#define S_R9 36
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#define S_R8 32
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#define S_R7 28
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#define S_R6 24
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#define S_R5 20
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#define S_R4 16
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#define S_R3 12
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#define S_R2 8
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#define S_R1 4
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#define S_R0 0
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#define MODE_SVC 0x13
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#define I_BIT 0x80
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/*
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* use bad_save_user_regs for abort/prefetch/undef/swi ...
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* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
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*/
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.macro bad_save_user_regs
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@ carve out a frame on current user stack
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sub sp, sp, #S_FRAME_SIZE
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stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
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ldr r2, IRQ_STACK_START_IN
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@ get values for "aborted" pc and cpsr (into parm regs)
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ldmia r2, {r2 - r3}
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add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
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add r5, sp, #S_SP
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mov r1, lr
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stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
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mov r0, sp @ save current stack into r0 (param register)
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.endm
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.macro irq_save_user_regs
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sub sp, sp, #S_FRAME_SIZE
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stmia sp, {r0 - r12} @ Calling r0-r12
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@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
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add r8, sp, #S_PC
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stmdb r8, {sp, lr}^ @ Calling SP, LR
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str lr, [r8, #0] @ Save calling PC
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mrs r6, spsr
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str r6, [r8, #4] @ Save CPSR
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str r0, [r8, #8] @ Save OLD_R0
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mov r0, sp
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.endm
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.macro irq_restore_user_regs
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ldmia sp, {r0 - lr}^ @ Calling r0 - lr
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mov r0, r0
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ldr lr, [sp, #S_PC] @ Get PC
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add sp, sp, #S_FRAME_SIZE
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subs pc, lr, #4 @ return & move spsr_svc into cpsr
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.endm
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.macro get_bad_stack
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ldr r13, IRQ_STACK_START_IN @ setup our mode stack
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str lr, [r13] @ save caller lr in position 0 of saved stack
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mrs lr, spsr @ get the spsr
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str lr, [r13, #4] @ save spsr in position 1 of saved stack
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mov r13, #MODE_SVC @ prepare SVC-Mode
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@ msr spsr_c, r13
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msr spsr, r13 @ switch modes, make sure moves will execute
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mov lr, pc @ capture return pc
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movs pc, lr @ jump to next instruction & switch modes.
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.endm
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.macro get_irq_stack @ setup IRQ stack
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ldr sp, IRQ_STACK_START
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.endm
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.macro get_fiq_stack @ setup FIQ stack
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ldr sp, FIQ_STACK_START
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.endm
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#endif /* CONFIG_SPL_BUILD */
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/*
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* exception handlers
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*/
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#ifdef CONFIG_SPL_BUILD
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.align 5
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do_hang:
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_hang:
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ldr sp, _TEXT_BASE /* switch to abort stack */
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1:
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bl 1b /* hang and never return */
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#else /* !CONFIG_SPL_BUILD */
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.align 5
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undefined_instruction:
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get_bad_stack
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bad_save_user_regs
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bl do_undefined_instruction
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.align 5
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software_interrupt:
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get_bad_stack
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bad_save_user_regs
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bl do_software_interrupt
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.align 5
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prefetch_abort:
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get_bad_stack
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bad_save_user_regs
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bl do_prefetch_abort
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.align 5
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data_abort:
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get_bad_stack
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bad_save_user_regs
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bl do_data_abort
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.align 5
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not_used:
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get_bad_stack
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bad_save_user_regs
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bl do_not_used
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#ifdef CONFIG_USE_IRQ
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.align 5
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irq:
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get_irq_stack
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irq_save_user_regs
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bl do_irq
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irq_restore_user_regs
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.align 5
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fiq:
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get_fiq_stack
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/* someone ought to write a more effiction fiq_save_user_regs */
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irq_save_user_regs
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bl do_fiq
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irq_restore_user_regs
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#else
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.align 5
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irq:
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get_bad_stack
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bad_save_user_regs
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bl do_irq
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.align 5
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fiq:
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get_bad_stack
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bad_save_user_regs
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bl do_fiq
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#endif
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#endif /* CONFIG_SPL_BUILD */
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@ -41,6 +41,7 @@
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#define CONFIG_SYS_DCACHE_OFF
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_ARCH_MISC_INIT
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/*
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* SPL
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