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powerpc/8xxx: Add base support for the SEC4
Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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@ -183,4 +183,10 @@ void fdt_fixup_crypto_node(void *blob, int sec_rev)
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printf("WARNING: could not set crypto property: %s\n",
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printf("WARNING: could not set crypto property: %s\n",
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fdt_strerror(err));
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fdt_strerror(err));
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}
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}
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#elif CONFIG_SYS_FSL_SEC_COMPAT >= 4 /* SEC4 */
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void fdt_fixup_crypto_node(void *blob, int sec_rev)
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{
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if (!sec_rev)
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fdt_del_node_and_alias(blob, "crypto");
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}
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#endif
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#endif
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@ -69,7 +69,9 @@
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/*
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/*
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* SEC (crypto unit) major compatible version determination
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* SEC (crypto unit) major compatible version determination
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*/
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*/
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#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83xx)
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#if defined(CONFIG_FSL_CORENET)
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#elif defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83xx)
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#endif
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#endif
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@ -2045,6 +2045,41 @@ enum {
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FSL_SRDS_B3_LANE_D = 23,
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FSL_SRDS_B3_LANE_D = 23,
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};
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};
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/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
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#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
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typedef struct ccsr_sec {
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u8 res1[0xfa0];
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u32 crnr_ms; /* CHA Revision Number Register, MS */
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u32 crnr_ls; /* CHA Revision Number Register, LS */
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u32 ctpr_ms; /* Compile Time Parameters Register, MS */
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#define SEC_CTPR_MS_AXI_LIODN 0x08000000
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#define SEC_CTPR_MS_QI 0x02000000
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u32 ctpr_ls; /* Compile Time Parameters Register, LS */
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u8 res2[0x10];
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u32 far_ms; /* Fault Address Register, MS */
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u32 far_ls; /* Fault Address Register, LS */
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u32 falr; /* Fault Address LIODN Register */
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u32 fadr; /* Fault Address Detail Register */
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u8 res3[0x4];
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u32 csta; /* CAAM Status Register */
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u8 res4[0x8];
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u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
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#define SEC_RVID_MA 0x0f000000
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u32 ccbvid; /* CHA Cluster Block Version ID Register */
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u32 chavid_ms; /* CHA Version ID Register, MS */
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u32 chavid_ls; /* CHA Version ID Register, LS */
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u32 chanum_ms; /* CHA Number Register, MS */
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#define SEC_CHANUM_MS_JQNUM_MASK 0xf0000000
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#define SEC_CHANUM_MS_JQNUM_SHIFT 28
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#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
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#define SEC_CHANUM_MS_DECONUM_SHIFT 24
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u32 chanum_ls; /* CHA Number Register, LS */
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u32 caamvid_ms; /* CAAM Version ID Register, MS */
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u32 caamvid_ls; /* CAAM Version ID Register, LS */
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u8 res5[0xf000];
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} ccsr_sec_t;
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#endif
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#ifdef CONFIG_FSL_CORENET
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#ifdef CONFIG_FSL_CORENET
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#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
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#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
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#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000
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#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000
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@ -2059,6 +2094,7 @@ enum {
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#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
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#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
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#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
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#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
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#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x210000
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#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x210000
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#define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
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#define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET 0x318000
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#define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET 0x318000
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#define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET 0x31a000
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#define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET 0x31a000
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#define CONFIG_SYS_TSEC1_OFFSET 0x4e0000 /* FM1@DTSEC0 */
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#define CONFIG_SYS_TSEC1_OFFSET 0x4e0000 /* FM1@DTSEC0 */
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@ -2143,6 +2179,8 @@ enum {
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(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
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(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
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#define CONFIG_SYS_MPC85xx_USB_ADDR \
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#define CONFIG_SYS_MPC85xx_USB_ADDR \
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(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET)
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(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET)
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#define CONFIG_SYS_FSL_SEC_ADDR \
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(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
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#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
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#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
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#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
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#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
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