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ppc4xx: Flush dcache after DDR2 autocalibration with caches on

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Flush the dcache before removing the TLB with caches enabled.
Otherwise this might lead to problems later on, e.g. while booting
Linux (as seen on ICON-440SPe).

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2011-09-16 12:54:58 +02:00
parent 25fb02abdf
commit 226502e01b
1 changed files with 7 additions and 0 deletions
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7
arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
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@ -656,6 +656,13 @@ phys_size_t initdram(int board_type)
program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
#endif
/*
* Flush the dcache before removing the TLB with caches
* enabled. Otherwise this might lead to problems later on,
* e.g. while booting Linux (as seen on ICON-440SPe).
*/
flush_dcache();
/*
* Now after initialization (auto-calibration and ECC generation)
* remove the TLB entries with caches enabled and program again with