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- fix sd-emmc controller A init on G12A/G12B/SM1 SoCs

Browse Source 
- add GXBB USB PHY driver
 - enable access to SPI NOR Flash on VIM2 and VIM3/VIM3L boards
 - fix USB PHYs Power-Up on on VIM3/VIM3L boards
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Merge tag 'u-boot-amlogic-20200428' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic

- fix sd-emmc controller A init on G12A/G12B/SM1 SoCs
- add GXBB USB PHY driver
- enable access to SPI NOR Flash on VIM2 and VIM3/VIM3L boards
- fix USB PHYs Power-Up on on VIM3/VIM3L boards
This commit is contained in:
Tom Rini 2020-04-28 10:09:16 -04:00
commit 221c4d9826
30 changed files with 633 additions and 101 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm/dts/meson-axg-s400.dts
View File

@ -313,15 +313,15 @@
dai-tdm-slot-rx-mask-1 = <1 1>;
mclk-fs = <256>;
codec@0 {
codec-0 {
sound-dai = <&lineout>;
};
codec@1 {
codec-1 {
sound-dai = <&speaker_amp1>;
};
codec@2 {
codec-2 {
sound-dai = <&linein>;
};

136
arch/arm/dts/meson-g12-common.dtsi
View File

@ -295,17 +295,9 @@
};
};
emmc_pins: emmc {
emmc_ctrl_pins: emmc-ctrl {
mux-0 {
groups = "emmc_nand_d0",
"emmc_nand_d1",
"emmc_nand_d2",
"emmc_nand_d3",
"emmc_nand_d4",
"emmc_nand_d5",
"emmc_nand_d6",
"emmc_nand_d7",
"emmc_cmd";
groups = "emmc_cmd";
function = "emmc";
bias-pull-up;
drive-strength-microamp = <4000>;
@ -319,6 +311,34 @@
};
};
emmc_data_4b_pins: emmc-data-4b {
mux-0 {
groups = "emmc_nand_d0",
"emmc_nand_d1",
"emmc_nand_d2",
"emmc_nand_d3";
function = "emmc";
bias-pull-up;
drive-strength-microamp = <4000>;
};
};
emmc_data_8b_pins: emmc-data-8b {
mux-0 {
groups = "emmc_nand_d0",
"emmc_nand_d1",
"emmc_nand_d2",
"emmc_nand_d3",
"emmc_nand_d4",
"emmc_nand_d5",
"emmc_nand_d6",
"emmc_nand_d7";
function = "emmc";
bias-pull-up;
drive-strength-microamp = <4000>;
};
};
emmc_ds_pins: emmc-ds {
mux {
groups = "emmc_nand_ds";
@ -573,6 +593,17 @@
};
};
nor_pins: nor {
mux {
groups = "nor_d",
"nor_q",
"nor_c",
"nor_cs";
function = "nor";
bias-disable;
};
};
pdm_din0_a_pins: pdm-din0-a {
mux {
groups = "pdm_din0_a";
@ -957,6 +988,57 @@
};
};
spicc0_x_pins: spicc0-x {
mux {
groups = "spi0_mosi_x",
"spi0_miso_x",
"spi0_clk_x";
function = "spi0";
drive-strength-microamp = <4000>;
bias-disable;
};
};
spicc0_ss0_x_pins: spicc0-ss0-x {
mux {
groups = "spi0_ss0_x";
function = "spi0";
drive-strength-microamp = <4000>;
bias-disable;
};
};
spicc0_c_pins: spicc0-c {
mux {
groups = "spi0_mosi_c",
"spi0_miso_c",
"spi0_ss0_c",
"spi0_clk_c";
function = "spi0";
drive-strength-microamp = <4000>;
bias-disable;
};
};
spicc1_pins: spicc1 {
mux {
groups = "spi1_mosi",
"spi1_miso",
"spi1_clk";
function = "spi1";
drive-strength-microamp = <4000>;
};
};
spicc1_ss0_pins: spicc1-ss0 {
mux {
groups = "spi1_ss0";
function = "spi1";
drive-strength-microamp = <4000>;
bias-disable;
};
};
tdm_a_din0_pins: tdm-a-din0 {
mux {
groups = "tdm_a_din0";
@ -2051,6 +2133,39 @@
amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
};
spicc0: spi@13000 {
compatible = "amlogic,meson-g12a-spicc";
reg = <0x0 0x13000 0x0 0x44>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_SPICC0>,
<&clkc CLKID_SPICC0_SCLK>;
clock-names = "core", "pclk";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spicc1: spi@15000 {
compatible = "amlogic,meson-g12a-spicc";
reg = <0x0 0x15000 0x0 0x44>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_SPICC1>,
<&clkc CLKID_SPICC1_SCLK>;
clock-names = "core", "pclk";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spifc: spi@14000 {
compatible = "amlogic,meson-gxbb-spifc";
status = "disabled";
reg = <0x0 0x14000 0x0 0x80>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_CLK81>;
};
pwm_ef: pwm@19000 {
compatible = "amlogic,meson-g12a-ee-pwm";
reg = <0x0 0x19000 0x0 0x20>;
@ -2220,6 +2335,7 @@
dr_mode = "host";
snps,dis_u2_susphy_quirk;
snps,quirk-frame-length-adjustment;
snps,parkmode-disable-ss-quirk;
};
};

1
arch/arm/dts/meson-g12.dtsi
View File

@ -56,6 +56,7 @@
<&clkc_audio AUD_CLKID_PDM_DCLK>,
<&clkc_audio AUD_CLKID_PDM_SYSCLK>;
clock-names = "pclk", "dclk", "sysclk";
resets = <&clkc_audio AUD_RESET_PDM>;
status = "disabled";
};

4
arch/arm/dts/meson-g12a-sei510.dts
View File

@ -269,7 +269,7 @@
dai-tdm-slot-tx-mask-3 = <1 1>;
mclk-fs = <256>;
codec@0 {
codec {
sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
};
};
@ -472,7 +472,7 @@
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";

2
arch/arm/dts/meson-g12a-u200.dts
View File

@ -271,7 +271,7 @@
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";

7
arch/arm/dts/meson-g12b-a311d-khadas-vim3-u-boot.dtsi Normal file
View File

@ -0,0 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#include "meson-khadas-vim3-u-boot.dtsi"

4
arch/arm/dts/meson-g12b-khadas-vim3.dtsi
View File

@ -8,6 +8,8 @@
#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
/ {
model = "Khadas VIM3";
vddcpu_a: regulator-vddcpu-a {
/*
* MP8756GD Regulator.
@ -48,7 +50,7 @@
sound {
compatible = "amlogic,axg-sound-card";
model = "G12A-KHADAS-VIM3";
model = "G12B-KHADAS-VIM3";
audio-aux-devs = <&tdmout_b>;
audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
"TDMOUT_B IN 1", "FRDDR_B OUT 1",

25
arch/arm/dts/meson-g12b-odroid-n2.dts
View File

@ -208,7 +208,7 @@
sound {
compatible = "amlogic,axg-sound-card";
model = "G12A-ODROIDN2";
model = "G12B-ODROID-N2";
audio-aux-devs = <&tdmout_b>;
audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
"TDMOUT_B IN 1", "FRDDR_B OUT 1",
@ -435,7 +435,7 @@
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
@ -451,6 +451,27 @@
vqmmc-supply = <&flash_1v8>;
};
/*
* EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR pins
* and eMMC Data 4 to 7 pins.
* Replace emmc_data_8b_pins to emmc_data_4b_pins from sd_emmc_c pinctrl-0,
* and change bus-width to 4 then spifc can be enabled.
* The SW1 slide should also be set to the correct position.
*/
&spifc {
status = "disabled";
pinctrl-0 = <&nor_pins>;
pinctrl-names = "default";
mx25u64: spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mxicy,mx25u6435f", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <104000000>;
};
};
&tdmif_b {
status = "okay";
};

52
arch/arm/dts/meson-gx.dtsi
View File

@ -12,6 +12,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&gic>;
@ -83,6 +84,7 @@
enable-method = "psci";
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
#cooling-cells = <2>;
};
cpu1: cpu@1 {
@ -92,6 +94,7 @@
enable-method = "psci";
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
#cooling-cells = <2>;
};
cpu2: cpu@2 {
@ -101,6 +104,7 @@
enable-method = "psci";
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
#cooling-cells = <2>;
};
cpu3: cpu@3 {
@ -110,6 +114,7 @@
enable-method = "psci";
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
#cooling-cells = <2>;
};
l2: l2-cache0 {
@ -117,6 +122,53 @@
};
};
thermal-zones {
cpu-thermal {
polling-delay-passive = <250>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
thermal-sensors = <&scpi_sensors 0>;
trips {
cpu_passive: cpu-passive {
temperature = <80000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
cpu_hot: cpu-hot {
temperature = <90000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "hot";
};
cpu_critical: cpu-critical {
temperature = <110000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "critical";
};
};
cpu_cooling_maps: cooling-maps {
map0 {
trip = <&cpu_passive>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu_hot>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
arm-pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,

1
arch/arm/dts/meson-gxbb-odroidc2.dts
View File

@ -248,6 +248,7 @@
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
linux,rc-map-name = "rc-odroid";
};
&gpio_ao {

9
arch/arm/dts/meson-gxl-s905x-p212.dtsi
View File

@ -15,7 +15,6 @@
/ {
aliases {
serial0 = &uart_AO;
serial1 = &uart_A;
ethernet0 = &ethmac;
};
@ -180,6 +179,14 @@
pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
pinctrl-names = "default";
uart-has-rtscts;
bluetooth {
compatible = "brcm,bcm43438-bt";
shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
max-speed = <2000000>;
clocks = <&wifi32k>;
clock-names = "lpo";
};
};
&uart_AO {

15
arch/arm/dts/meson-gxm-khadas-vim2-u-boot.dtsi
View File

@ -5,3 +5,18 @@
*/
#include "meson-gx-u-boot.dtsi"
/ {
aliases {
spi0 = &spifc;
};
};
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
};
&spifc {
status = "okay";
};

89
arch/arm/dts/meson-gxm-khadas-vim2.dts
View File

@ -8,7 +8,6 @@
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/thermal/thermal.h>
#include "meson-gxm.dtsi"
@ -100,49 +99,6 @@
clock-names = "ext_clock";
};
thermal-zones {
cpu-thermal {
polling-delay-passive = <250>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
thermal-sensors = <&scpi_sensors 0>;
trips {
cpu_alert0: cpu-alert0 {
temperature = <70000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "active";
};
cpu_alert1: cpu-alert1 {
temperature = <80000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert0>;
cooling-device = <&gpio_fan THERMAL_NO_LIMIT 1>;
};
map1 {
trip = <&cpu_alert1>;
cooling-device = <&gpio_fan 2 THERMAL_NO_LIMIT>,
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
hdmi_5v: regulator-hdmi-5v {
compatible = "regulator-fixed";
@ -198,36 +154,23 @@
hdmi-phandle = <&hdmi_tx>;
};
&cpu0 {
#cooling-cells = <2>;
};
&cpu1 {
#cooling-cells = <2>;
};
&cpu_cooling_maps {
map0 {
cooling-device = <&gpio_fan THERMAL_NO_LIMIT 1>;
};
&cpu2 {
#cooling-cells = <2>;
};
&cpu3 {
#cooling-cells = <2>;
};
&cpu4 {
#cooling-cells = <2>;
};
&cpu5 {
#cooling-cells = <2>;
};
&cpu6 {
#cooling-cells = <2>;
};
&cpu7 {
#cooling-cells = <2>;
map1 {
cooling-device = <&gpio_fan 2 THERMAL_NO_LIMIT>,
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
&ethmac {
@ -327,7 +270,7 @@
#size-cells = <0>;
bus-width = <4>;
max-frequency = <50000000>;
max-frequency = <60000000>;
non-removable;
disable-wp;

28
arch/arm/dts/meson-gxm.dtsi
View File

@ -49,6 +49,7 @@
enable-method = "psci";
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 1>;
#cooling-cells = <2>;
};
cpu5: cpu@101 {
@ -58,6 +59,7 @@
enable-method = "psci";
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 1>;
#cooling-cells = <2>;
};
cpu6: cpu@102 {
@ -67,6 +69,7 @@
enable-method = "psci";
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 1>;
#cooling-cells = <2>;
};
cpu7: cpu@103 {
@ -76,6 +79,7 @@
enable-method = "psci";
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 1>;
#cooling-cells = <2>;
};
};
};
@ -124,6 +128,30 @@
compatible = "amlogic,meson-gxm-aoclkc", "amlogic,meson-gx-aoclkc";
};
&cpu_cooling_maps {
map0 {
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
&saradc {
compatible = "amlogic,meson-gxm-saradc", "amlogic,meson-saradc";
};

21
arch/arm/dts/meson-khadas-vim3-u-boot.dtsi Normal file
View File

@ -0,0 +1,21 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
/ {
aliases {
spi0 = &spifc;
};
};
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_4b_pins>, <&emmc_ds_pins>;
bus-width = <4>;
};
&spifc {
status = "okay";
};

24
arch/arm/dts/meson-khadas-vim3.dtsi
View File

@ -9,8 +9,6 @@
#include <dt-bindings/gpio/meson-g12a-gpio.h>
/ {
model = "Khadas VIM3";
aliases {
serial0 = &uart_AO;
ethernet0 = &ethmac;
@ -312,7 +310,7 @@
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
@ -328,6 +326,26 @@
vqmmc-supply = <&emmc_1v8>;
};
/*
* EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR CS
* and eMMC Data 4 to 7 pins.
* Replace emmc_data_8b_pins to emmc_data_4b_pins from sd_emmc_c pinctrl-0,
* and change bus-width to 4 then spifc can be enabled.
*/
&spifc {
status = "disabled";
pinctrl-0 = <&nor_pins>;
pinctrl-names = "default";
w25q32: spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "winbond,w25q128fw", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <104000000>;
};
};
&uart_A {
status = "okay";
pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;

7
arch/arm/dts/meson-sm1-khadas-vim3l-u-boot.dtsi Normal file
View File

@ -0,0 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#include "meson-khadas-vim3-u-boot.dtsi"

8
arch/arm/dts/meson-sm1-khadas-vim3l.dts
View File

@ -72,9 +72,10 @@
/*
* The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
* lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
* an USB3.0 Type A connector and a M.2 Key M slot. The PHY driving
* these differential lines is shared between the USB3.0 controller
* and the PCIe Controller, thus only a single controller can use it.
* an USB3.0 Type A connector and a M.2 Key M slot.
* The PHY driving these differential lines is shared between
* the USB3.0 controller and the PCIe Controller, thus only
* a single controller can use it.
* If the MCU is configured to mux the PCIe/USB3.0 differential lines
* to the M.2 Key M slot, uncomment the following block to disable
* USB3.0 from the USB Complex and enable the PCIe controller.
@ -82,7 +83,6 @@
* testing purposes, but instead rely on the firmware/bootloader to
* update these nodes accordingly if PCIe mode is selected by the MCU.
*/
/*
&pcie {
status = "okay";

3
arch/arm/dts/meson-sm1-sei610.dts
View File

@ -518,7 +518,7 @@
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
@ -593,6 +593,7 @@
compatible = "brcm,bcm43438-bt";
interrupt-parent = <&gpio_intc>;
interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wakeup";
shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
max-speed = <2000000>;
clocks = <&wifi32k>;

1
arch/arm/dts/meson-sm1.dtsi
View File

@ -448,6 +448,7 @@
<&clkc_audio AUD_CLKID_PDM_DCLK>,
<&clkc_audio AUD_CLKID_PDM_SYSCLK>;
clock-names = "pclk", "dclk", "sysclk";
resets = <&clkc_audio AUD_RESET_PDM>;
status = "disabled";
};
};

8
configs/khadas-vim2_defconfig
View File

@ -19,6 +19,8 @@ CONFIG_CMD_ADC=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF_TEST=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
@ -30,7 +32,10 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SARADC_MESON=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
@ -44,6 +49,9 @@ CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MESON_SPIFC=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y

9
configs/khadas-vim3_defconfig
View File

@ -18,6 +18,8 @@ CONFIG_MISC_INIT_R=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF_TEST=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
@ -28,6 +30,10 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
@ -41,6 +47,9 @@ CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MESON_SPIFC=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y

9
configs/khadas-vim3l_defconfig
View File

@ -18,6 +18,8 @@ CONFIG_MISC_INIT_R=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF_TEST=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
@ -28,6 +30,10 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
@ -43,6 +49,9 @@ CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MESON_SPIFC=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y

2
drivers/clk/meson/g12a.c
View File

@ -112,6 +112,7 @@ static struct meson_gate gates[NUM_CLKS] = {
MESON_GATE(CLKID_I2C, HHI_GCLK_MPEG0, 9),
MESON_GATE(CLKID_UART0, HHI_GCLK_MPEG0, 13),
MESON_GATE(CLKID_SPICC1, HHI_GCLK_MPEG0, 14),
MESON_GATE(CLKID_SD_EMMC_A, HHI_GCLK_MPEG0, 4),
MESON_GATE(CLKID_SD_EMMC_B, HHI_GCLK_MPEG0, 25),
MESON_GATE(CLKID_SD_EMMC_C, HHI_GCLK_MPEG0, 26),
MESON_GATE(CLKID_ETH, HHI_GCLK_MPEG1, 3),
@ -127,6 +128,7 @@ static struct meson_gate gates[NUM_CLKS] = {
MESON_GATE(CLKID_FCLK_DIV4, HHI_FIX_PLL_CNTL1, 21),
MESON_GATE(CLKID_FCLK_DIV5, HHI_FIX_PLL_CNTL1, 22),
MESON_GATE(CLKID_FCLK_DIV7, HHI_FIX_PLL_CNTL1, 23),
MESON_GATE(CLKID_SD_EMMC_A_CLK0, HHI_SD_EMMC_CLK_CNTL, 7),
MESON_GATE(CLKID_SD_EMMC_B_CLK0, HHI_SD_EMMC_CLK_CNTL, 23),
MESON_GATE(CLKID_SD_EMMC_C_CLK0, HHI_NAND_CLK_CNTL, 7),
MESON_GATE(CLKID_VPU_0, HHI_VPU_CLK_CNTL, 8),

8
drivers/phy/Kconfig
View File

@ -154,6 +154,14 @@ config PHY_STM32_USBPHYC
between an HS USB OTG controller and an HS USB Host controller,
selected by an USB switch.
config MESON_GXBB_USB_PHY
bool "Amlogic Meson GXBB USB PHY"
depends on PHY && ARCH_MESON && MESON_GXBB
imply REGMAP
help
This is the generic phy driver for the Amlogic Meson GXBB
USB2 PHY.
config MESON_GXL_USB_PHY
bool "Amlogic Meson GXL USB PHYs"
depends on PHY && ARCH_MESON && (MESON_GXL || MESON_GXM)

1
drivers/phy/Makefile
View File

@ -16,6 +16,7 @@ obj-$(CONFIG_STI_USB_PHY) += sti_usb_phy.o
obj-$(CONFIG_PHY_RCAR_GEN2) += phy-rcar-gen2.o
obj-$(CONFIG_PHY_RCAR_GEN3) += phy-rcar-gen3.o
obj-$(CONFIG_PHY_STM32_USBPHYC) += phy-stm32-usbphyc.o
obj-$(CONFIG_MESON_GXBB_USB_PHY) += meson-gxbb-usb2.o
obj-$(CONFIG_MESON_GXL_USB_PHY) += meson-gxl-usb2.o meson-gxl-usb3.o
obj-$(CONFIG_MESON_G12A_USB_PHY) += meson-g12a-usb2.o meson-g12a-usb3-pcie.o
obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o

235
drivers/phy/meson-gxbb-usb2.c Normal file
View File

@ -0,0 +1,235 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Meson8, Meson8b and GXBB USB2 PHY driver
*
* Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
* Copyright (C) 2018 BayLibre, SAS
*
* Author: Beniamino Galvani <b.galvani@gmail.com>
*/
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <generic-phy.h>
#include <power/regulator.h>
#include <regmap.h>
#include <reset.h>
#define REG_CONFIG 0x00
#define REG_CONFIG_CLK_EN BIT(0)
#define REG_CONFIG_CLK_SEL_MASK GENMASK(3, 1)
#define REG_CONFIG_CLK_DIV_MASK GENMASK(10, 4)
#define REG_CONFIG_CLK_32k_ALTSEL BIT(15)
#define REG_CONFIG_TEST_TRIG BIT(31)
#define REG_CTRL 0x04
#define REG_CTRL_SOFT_PRST BIT(0)
#define REG_CTRL_SOFT_HRESET BIT(1)
#define REG_CTRL_SS_SCALEDOWN_MODE_MASK GENMASK(3, 2)
#define REG_CTRL_CLK_DET_RST BIT(4)
#define REG_CTRL_INTR_SEL BIT(5)
#define REG_CTRL_CLK_DETECTED BIT(8)
#define REG_CTRL_SOF_SENT_RCVD_TGL BIT(9)
#define REG_CTRL_SOF_TOGGLE_OUT BIT(10)
#define REG_CTRL_POWER_ON_RESET BIT(15)
#define REG_CTRL_SLEEPM BIT(16)
#define REG_CTRL_TX_BITSTUFF_ENN_H BIT(17)
#define REG_CTRL_TX_BITSTUFF_ENN BIT(18)
#define REG_CTRL_COMMON_ON BIT(19)
#define REG_CTRL_REF_CLK_SEL_MASK GENMASK(21, 20)
#define REG_CTRL_REF_CLK_SEL_SHIFT 20
#define REG_CTRL_FSEL_MASK GENMASK(24, 22)
#define REG_CTRL_FSEL_SHIFT 22
#define REG_CTRL_PORT_RESET BIT(25)
#define REG_CTRL_THREAD_ID_MASK GENMASK(31, 26)
/* bits [31:26], [24:21] and [15:3] seem to be read-only */
#define REG_ADP_BC 0x0c
#define REG_ADP_BC_VBUS_VLD_EXT_SEL BIT(0)
#define REG_ADP_BC_VBUS_VLD_EXT BIT(1)
#define REG_ADP_BC_OTG_DISABLE BIT(2)
#define REG_ADP_BC_ID_PULLUP BIT(3)
#define REG_ADP_BC_DRV_VBUS BIT(4)
#define REG_ADP_BC_ADP_PRB_EN BIT(5)
#define REG_ADP_BC_ADP_DISCHARGE BIT(6)
#define REG_ADP_BC_ADP_CHARGE BIT(7)
#define REG_ADP_BC_SESS_END BIT(8)
#define REG_ADP_BC_DEVICE_SESS_VLD BIT(9)
#define REG_ADP_BC_B_VALID BIT(10)
#define REG_ADP_BC_A_VALID BIT(11)
#define REG_ADP_BC_ID_DIG BIT(12)
#define REG_ADP_BC_VBUS_VALID BIT(13)
#define REG_ADP_BC_ADP_PROBE BIT(14)
#define REG_ADP_BC_ADP_SENSE BIT(15)
#define REG_ADP_BC_ACA_ENABLE BIT(16)
#define REG_ADP_BC_DCD_ENABLE BIT(17)
#define REG_ADP_BC_VDAT_DET_EN_B BIT(18)
#define REG_ADP_BC_VDAT_SRC_EN_B BIT(19)
#define REG_ADP_BC_CHARGE_SEL BIT(20)
#define REG_ADP_BC_CHARGE_DETECT BIT(21)
#define REG_ADP_BC_ACA_PIN_RANGE_C BIT(22)
#define REG_ADP_BC_ACA_PIN_RANGE_B BIT(23)
#define REG_ADP_BC_ACA_PIN_RANGE_A BIT(24)
#define REG_ADP_BC_ACA_PIN_GND BIT(25)
#define REG_ADP_BC_ACA_PIN_FLOAT BIT(26)
#define RESET_COMPLETE_TIME 500
#define ACA_ENABLE_COMPLETE_TIME 50
struct phy_meson_gxbb_usb2_priv {
struct regmap *regmap;
struct reset_ctl_bulk resets;
#if CONFIG_IS_ENABLED(DM_REGULATOR)
struct udevice *phy_supply;
#endif
};
static int phy_meson_gxbb_usb2_power_on(struct phy *phy)
{
struct udevice *dev = phy->dev;
struct phy_meson_gxbb_usb2_priv *priv = dev_get_priv(dev);
uint val;
#if CONFIG_IS_ENABLED(DM_REGULATOR)
if (priv->phy_supply) {
int ret = regulator_set_enable(priv->phy_supply, true);
if (ret)
return ret;
}
#endif
regmap_update_bits(priv->regmap, REG_CONFIG,
REG_CONFIG_CLK_32k_ALTSEL,
REG_CONFIG_CLK_32k_ALTSEL);
regmap_update_bits(priv->regmap, REG_CTRL,
REG_CTRL_REF_CLK_SEL_MASK,
0x2 << REG_CTRL_REF_CLK_SEL_SHIFT);
regmap_update_bits(priv->regmap, REG_CTRL,
REG_CTRL_FSEL_MASK,
0x5 << REG_CTRL_FSEL_SHIFT);
/* reset the PHY */
regmap_update_bits(priv->regmap, REG_CTRL,
REG_CTRL_POWER_ON_RESET,
REG_CTRL_POWER_ON_RESET);
udelay(RESET_COMPLETE_TIME);
regmap_update_bits(priv->regmap, REG_CTRL,
REG_CTRL_POWER_ON_RESET,
0);
udelay(RESET_COMPLETE_TIME);
regmap_update_bits(priv->regmap, REG_CTRL,
REG_CTRL_SOF_TOGGLE_OUT,
REG_CTRL_SOF_TOGGLE_OUT);
/* Set host mode */
regmap_update_bits(priv->regmap, REG_ADP_BC,
REG_ADP_BC_ACA_ENABLE,
REG_ADP_BC_ACA_ENABLE);
udelay(ACA_ENABLE_COMPLETE_TIME);
regmap_read(priv->regmap, REG_ADP_BC, &val);
if (val & REG_ADP_BC_ACA_PIN_FLOAT) {
pr_err("Error powering on GXBB USB PHY\n");
return -EINVAL;
}
return 0;
}
static int phy_meson_gxbb_usb2_power_off(struct phy *phy)
{
#if CONFIG_IS_ENABLED(DM_REGULATOR)
struct udevice *dev = phy->dev;
struct phy_meson_gxbb_usb2_priv *priv = dev_get_priv(dev);
if (priv->phy_supply) {
int ret = regulator_set_enable(priv->phy_supply, false);
if (ret)
return ret;
}
#endif
return 0;
}
static struct phy_ops meson_gxbb_usb2_phy_ops = {
.power_on = phy_meson_gxbb_usb2_power_on,
.power_off = phy_meson_gxbb_usb2_power_off,
};
static int meson_gxbb_usb2_phy_probe(struct udevice *dev)
{
struct phy_meson_gxbb_usb2_priv *priv = dev_get_priv(dev);
struct clk clk_usb_general, clk_usb;
int ret;
ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
if (ret)
return ret;
ret = clk_get_by_name(dev, "usb_general", &clk_usb_general);
if (ret)
return ret;
ret = clk_enable(&clk_usb_general);
if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
pr_err("Failed to enable PHY general clock\n");
return ret;
}
ret = clk_get_by_name(dev, "usb", &clk_usb);
if (ret)
return ret;
ret = clk_enable(&clk_usb);
if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
pr_err("Failed to enable PHY clock\n");
return ret;
}
#if CONFIG_IS_ENABLED(DM_REGULATOR)
ret = device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
if (ret && ret != -ENOENT) {
pr_err("Failed to get PHY regulator\n");
return ret;
}
#endif
ret = reset_get_bulk(dev, &priv->resets);
if (!ret) {
ret = reset_deassert_bulk(&priv->resets);
if (ret) {
pr_err("Failed to deassert reset\n");
return ret;
}
}
return 0;
}
static int meson_gxbb_usb2_phy_remove(struct udevice *dev)
{
struct phy_meson_gxbb_usb2_priv *priv = dev_get_priv(dev);
return reset_release_bulk(&priv->resets);
}
static const struct udevice_id meson_gxbb_usb2_phy_ids[] = {
{ .compatible = "amlogic,meson8-usb2-phy" },
{ .compatible = "amlogic,meson8b-usb2-phy" },
{ .compatible = "amlogic,meson-gxbb-usb2-phy" },
{ }
};
U_BOOT_DRIVER(meson_gxbb_usb2_phy) = {
.name = "meson_gxbb_usb2_phy",
.id = UCLASS_PHY,
.of_match = meson_gxbb_usb2_phy_ids,
.probe = meson_gxbb_usb2_phy_probe,
.remove = meson_gxbb_usb2_phy_remove,
.ops = &meson_gxbb_usb2_phy_ops,
.priv_auto_alloc_size = sizeof(struct phy_meson_gxbb_usb2_priv),
};

16
drivers/usb/dwc3/dwc3-meson-g12a.c
View File

@ -408,6 +408,15 @@ static int dwc3_meson_g12a_probe(struct udevice *dev)
goto err_phy_init;
}
for (i = 0; i < PHY_COUNT; ++i) {
if (!priv->phys[i].dev)
continue;
ret = generic_phy_power_on(&priv->phys[i]);
if (ret)
goto err_phy_init;
}
return 0;
err_phy_init:
@ -430,6 +439,13 @@ static int dwc3_meson_g12a_remove(struct udevice *dev)
clk_release_all(&priv->clk, 1);
for (i = 0; i < PHY_COUNT; ++i) {
if (!priv->phys[i].dev)
continue;
generic_phy_power_off(&priv->phys[i]);
}
for (i = 0 ; i < PHY_COUNT ; ++i) {
if (!priv->phys[i].dev)
continue;

2
include/dt-bindings/clock/g12a-clkc.h
View File

@ -143,5 +143,7 @@
#define CLKID_CPU1_CLK 253
#define CLKID_CPU2_CLK 254
#define CLKID_CPU3_CLK 255
#define CLKID_SPICC0_SCLK 258
#define CLKID_SPICC1_SCLK 261
#endif /* __G12A_CLKC_H */

1
include/dt-bindings/clock/gxbb-clkc.h
View File

@ -146,5 +146,6 @@
#define CLKID_CTS_VDAC 201
#define CLKID_HDMI_TX 202
#define CLKID_HDMI 205
#define CLKID_ACODEC 206
#endif /* __GXBB_CLKC_H */