mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
Merge tag 'u-boot-rockchip-20190809' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Add rk3399 boards Khadas Edge/-V/-Captain - Add fully souce code support for rk3328 including TPL/DRAM init - Enable boot from eMMC for rk3399 rock960/ficus boards - turn on the IO supply for dw_mmc
This commit is contained in:
Tom Rini
commit
21bc1935b1
|
|
@ -108,6 +108,9 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
|
|||
rk3399-ficus.dtb \
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rk3399-firefly.dtb \
|
||||
rk3399-gru-bob.dtb \
|
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rk3399-khadas-edge.dtb \
|
||||
rk3399-khadas-edge-captain.dtb \
|
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rk3399-khadas-edge-v.dtb \
|
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rk3399-nanopc-t4.dtb \
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rk3399-nanopi-m4.dtb \
|
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rk3399-nanopi-neo4.dtb \
|
||||
|
|
|
|||
33
arch/arm/dts/rk3328-evb-u-boot.dtsi
Normal file
33
arch/arm/dts/rk3328-evb-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
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*/
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#include "rk3328-sdram-ddr3-666.dtsi"
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||||
|
||||
/ {
|
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aliases {
|
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mmc0 = &emmc;
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mmc1 = &sdmmc;
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};
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chosen {
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u-boot,spl-boot-order = &emmc, &sdmmc;
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};
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};
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&cru {
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u-boot,dm-pre-reloc;
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};
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&uart2 {
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u-boot,dm-pre-reloc;
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};
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&emmc {
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u-boot,dm-pre-reloc;
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};
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&sdmmc {
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u-boot,dm-pre-reloc;
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};
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|
@ -4,6 +4,8 @@
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* SPDX-License-Identifier: GPL-2.0+
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*/
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||||
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#include "rk3328-sdram-lpddr3-1600.dtsi"
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||||
/ {
|
||||
aliases {
|
||||
mmc0 = &emmc;
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||||
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|
@ -25,10 +27,8 @@
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|||
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&emmc {
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||||
u-boot,dm-pre-reloc;
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fifo-mode;
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};
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|
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&sdmmc {
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u-boot,dm-pre-reloc;
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fifo-mode;
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};
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|
|
|
|||
215
arch/arm/dts/rk3328-sdram-ddr3-666.dtsi
Normal file
215
arch/arm/dts/rk3328-sdram-ddr3-666.dtsi
Normal file
|
|
@ -0,0 +1,215 @@
|
|||
/*
|
||||
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
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||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
&dmc {
|
||||
rockchip,sdram-params = <
|
||||
0x1
|
||||
0xC
|
||||
0x3
|
||||
0x1
|
||||
0x0
|
||||
0x0
|
||||
0x10
|
||||
0x10
|
||||
0
|
||||
|
||||
0x9028b189
|
||||
0x00000000
|
||||
0x00000021
|
||||
0x00000482
|
||||
0x00000015
|
||||
0x00000222
|
||||
0x000000ff
|
||||
|
||||
333
|
||||
3
|
||||
0
|
||||
|
||||
0x00000000
|
||||
0x43041001
|
||||
0x00000064
|
||||
0x0028003b
|
||||
0x000000d0
|
||||
0x00020053
|
||||
0x000000d4
|
||||
0x00020000
|
||||
0x000000d8
|
||||
0x00000100
|
||||
0x000000dc
|
||||
0x03200000
|
||||
0x000000e0
|
||||
0x00000000
|
||||
0x000000e4
|
||||
0x00090000
|
||||
0x000000f4
|
||||
0x000f011f
|
||||
0x00000100
|
||||
0x07090b06
|
||||
0x00000104
|
||||
0x00050209
|
||||
0x00000108
|
||||
0x03030407
|
||||
0x0000010c
|
||||
0x00202006
|
||||
0x00000110
|
||||
0x03020204
|
||||
0x00000114
|
||||
0x03030202
|
||||
0x00000120
|
||||
0x00000903
|
||||
0x00000180
|
||||
0x00800020
|
||||
0x00000184
|
||||
0x00000000
|
||||
0x00000190
|
||||
0x07010001
|
||||
0x00000198
|
||||
0x05001100
|
||||
0x000001a0
|
||||
0xc0400003
|
||||
0x00000240
|
||||
0x06000604
|
||||
0x00000244
|
||||
0x00000201
|
||||
0x00000250
|
||||
0x00000f00
|
||||
0x00000490
|
||||
0x00000001
|
||||
0xffffffff
|
||||
0xffffffff
|
||||
0xffffffff
|
||||
0xffffffff
|
||||
0xffffffff
|
||||
0xffffffff
|
||||
0xffffffff
|
||||
0xffffffff
|
||||
0xffffffff
|
||||
0xffffffff
|
||||
|
||||
0x00000004
|
||||
0x0000000a
|
||||
0x00000028
|
||||
0x00000006
|
||||
0x0000002c
|
||||
0x00000000
|
||||
0x00000030
|
||||
0x00000005
|
||||
0xffffffff
|
||||
0xffffffff
|
||||
|
||||
0x77
|
||||
0x88
|
||||
0x79
|
||||
0x79
|
||||
0x87
|
||||
0x97
|
||||
0x87
|
||||
0x78
|
||||
0x77
|
||||
0x78
|
||||
0x87
|
||||
0x88
|
||||
0x87
|
||||
0x87
|
||||
0x77
|
||||
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x69
|
||||
0x9
|
||||
|
||||
0x77
|
||||
0x78
|
||||
0x77
|
||||
0x78
|
||||
0x77
|
||||
0x78
|
||||
0x77
|
||||
0x78
|
||||
0x77
|
||||
0x79
|
||||
0x9
|
||||
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x69
|
||||
0x9
|
||||
|
||||
0x77
|
||||
0x78
|
||||
0x77
|
||||
0x77
|
||||
0x77
|
||||
0x77
|
||||
0x77
|
||||
0x77
|
||||
0x77
|
||||
0x79
|
||||
0x9
|
||||
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x69
|
||||
0x9
|
||||
|
||||
0x77
|
||||
0x78
|
||||
0x77
|
||||
0x78
|
||||
0x77
|
||||
0x78
|
||||
0x77
|
||||
0x78
|
||||
0x77
|
||||
0x79
|
||||
0x9
|
||||
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x69
|
||||
0x9
|
||||
|
||||
0x77
|
||||
0x78
|
||||
0x77
|
||||
0x77
|
||||
0x77
|
||||
0x77
|
||||
0x77
|
||||
0x77
|
||||
0x77
|
||||
0x79
|
||||
0x9
|
||||
>;
|
||||
};
|
||||
215
arch/arm/dts/rk3328-sdram-lpddr3-1600.dtsi
Normal file
215
arch/arm/dts/rk3328-sdram-lpddr3-1600.dtsi
Normal file
|
|
@ -0,0 +1,215 @@
|
|||
/*
|
||||
* (C) 2017 Theobroma Systems Design und Consulting GmbH
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
&dmc {
|
||||
rockchip,sdram-params = <
|
||||
0x1
|
||||
0xC
|
||||
0x3
|
||||
0x1
|
||||
0x0
|
||||
0x0
|
||||
0x10
|
||||
0x10
|
||||
0
|
||||
|
||||
0x98899459
|
||||
0x00000000
|
||||
0x0000002e
|
||||
0x00000544
|
||||
0x00000015
|
||||
0x00000432
|
||||
0x000000ff
|
||||
|
||||
800
|
||||
6
|
||||
1
|
||||
|
||||
0x00000000
|
||||
0x43041008
|
||||
0x00000064
|
||||
0x00300054
|
||||
0x000000d0
|
||||
0x00500002
|
||||
0x000000d4
|
||||
0x00010000
|
||||
0x000000d8
|
||||
0x00000e03
|
||||
0x000000dc
|
||||
0x0043001a
|
||||
0x000000e0
|
||||
0x00010000
|
||||
0x000000e4
|
||||
0x000e0005
|
||||
0x000000f4
|
||||
0x000f011f
|
||||
0x00000100
|
||||
0x0b141b11
|
||||
0x00000104
|
||||
0x0003031a
|
||||
0x00000108
|
||||
0x03060809
|
||||
0x0000010c
|
||||
0x00606000
|
||||
0x00000110
|
||||
0x08020409
|
||||
0x00000114
|
||||
0x01010606
|
||||
0x00000118
|
||||
0x02020004
|
||||
0x00000120
|
||||
0x00000404
|
||||
0x00000138
|
||||
0x00000058
|
||||
0x00000180
|
||||
0x00900024
|
||||
0x00000184
|
||||
0x01400000
|
||||
0x00000190
|
||||
0x07050002
|
||||
0x00000198
|
||||
0x05001100
|
||||
0x000001a0
|
||||
0xc0400003
|
||||
0x00000240
|
||||
0x0a020b28
|
||||
0x00000244
|
||||
0x00000101
|
||||
0x00000250
|
||||
0x00000f00
|
||||
0x00000490
|
||||
0x00000001
|
||||
0xffffffff
|
||||
0xffffffff
|
||||
0xffffffff
|
||||
0xffffffff
|
||||
0xffffffff
|
||||
0xffffffff
|
||||
|
||||
0x00000004
|
||||
0x0000000b
|
||||
0x00000028
|
||||
0x0000000c
|
||||
0x0000002c
|
||||
0x00000000
|
||||
0x00000030
|
||||
0x00000006
|
||||
0xffffffff
|
||||
0xffffffff
|
||||
|
||||
0x77
|
||||
0x88
|
||||
0x79
|
||||
0x79
|
||||
0x87
|
||||
0x97
|
||||
0x87
|
||||
0x78
|
||||
0x77
|
||||
0x78
|
||||
0x87
|
||||
0x88
|
||||
0x87
|
||||
0x87
|
||||
0x77
|
||||
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x69
|
||||
0x9
|
||||
|
||||
0x77
|
||||
0x78
|
||||
0x77
|
||||
0x78
|
||||
0x77
|
||||
0x78
|
||||
0x77
|
||||
0x78
|
||||
0x77
|
||||
0x79
|
||||
0x9
|
||||
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x69
|
||||
0x9
|
||||
|
||||
0x77
|
||||
0x78
|
||||
0x77
|
||||
0x77
|
||||
0x77
|
||||
0x77
|
||||
0x77
|
||||
0x77
|
||||
0x77
|
||||
0x79
|
||||
0x9
|
||||
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x69
|
||||
0x9
|
||||
|
||||
0x77
|
||||
0x78
|
||||
0x77
|
||||
0x78
|
||||
0x77
|
||||
0x78
|
||||
0x77
|
||||
0x78
|
||||
0x77
|
||||
0x79
|
||||
0x9
|
||||
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x69
|
||||
0x9
|
||||
|
||||
0x77
|
||||
0x78
|
||||
0x77
|
||||
0x77
|
||||
0x77
|
||||
0x77
|
||||
0x77
|
||||
0x77
|
||||
0x77
|
||||
0x79
|
||||
0x9
|
||||
>;
|
||||
};
|
||||
215
arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi
Normal file
215
arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi
Normal file
|
|
@ -0,0 +1,215 @@
|
|||
/*
|
||||
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
&dmc {
|
||||
rockchip,sdram-params = <
|
||||
0x1
|
||||
0xC
|
||||
0x3
|
||||
0x1
|
||||
0x0
|
||||
0x0
|
||||
0x10
|
||||
0x10
|
||||
0
|
||||
|
||||
0x0c48a18a
|
||||
0x00000000
|
||||
0x00000021
|
||||
0x00000482
|
||||
0x00000015
|
||||
0x0000021a
|
||||
0x000000ff
|
||||
|
||||
333
|
||||
6
|
||||
0
|
||||
|
||||
0x00000000
|
||||
0xc3040008
|
||||
0x00000064
|
||||
0x00140023
|
||||
0x000000d0
|
||||
0x00220002
|
||||
0x000000d4
|
||||
0x00010000
|
||||
0x000000d8
|
||||
0x00000703
|
||||
0x000000dc
|
||||
0x00830004
|
||||
0x000000e0
|
||||
0x00010000
|
||||
0x000000e4
|
||||
0x00070003
|
||||
0x00000100
|
||||
0x06090b07
|
||||
0x00000104
|
||||
0x0002020b
|
||||
0x00000108
|
||||
0x02030506
|
||||
0x0000010c
|
||||
0x00505000
|
||||
0x00000110
|
||||
0x03020204
|
||||
0x00000114
|
||||
0x01010303
|
||||
0x00000118
|
||||
0x02020003
|
||||
0x00000120
|
||||
0x00000303
|
||||
0x00000138
|
||||
0x00000025
|
||||
0x00000180
|
||||
0x003c000f
|
||||
0x00000184
|
||||
0x00900000
|
||||
0x00000190
|
||||
0x07020000
|
||||
0x00000198
|
||||
0x05001100
|
||||
0x000001a0
|
||||
0xc0400003
|
||||
0x00000240
|
||||
0x0900090c
|
||||
0x00000244
|
||||
0x00000101
|
||||
0x00000250
|
||||
0x00000f00
|
||||
0x00000490
|
||||
0x00000001
|
||||
0xffffffff
|
||||
0xffffffff
|
||||
0xffffffff
|
||||
0xffffffff
|
||||
0xffffffff
|
||||
0xffffffff
|
||||
0xffffffff
|
||||
0xffffffff
|
||||
|
||||
0x00000004
|
||||
0x0000000b
|
||||
0x00000028
|
||||
0x00000006
|
||||
0x0000002c
|
||||
0x00000000
|
||||
0x00000030
|
||||
0x00000003
|
||||
0xffffffff
|
||||
0xffffffff
|
||||
|
||||
0x77
|
||||
0x88
|
||||
0x79
|
||||
0x79
|
||||
0x87
|
||||
0x97
|
||||
0x87
|
||||
0x78
|
||||
0x77
|
||||
0x78
|
||||
0x87
|
||||
0x88
|
||||
0x87
|
||||
0x87
|
||||
0x77
|
||||
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x69
|
||||
0x9
|
||||
|
||||
0x77
|
||||
0x78
|
||||
0x77
|
||||
0x78
|
||||
0x77
|
||||
0x78
|
||||
0x77
|
||||
0x78
|
||||
0x77
|
||||
0x79
|
||||
0x9
|
||||
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x69
|
||||
0x9
|
||||
|
||||
0x77
|
||||
0x78
|
||||
0x77
|
||||
0x77
|
||||
0x77
|
||||
0x77
|
||||
0x77
|
||||
0x77
|
||||
0x77
|
||||
0x79
|
||||
0x9
|
||||
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x69
|
||||
0x9
|
||||
|
||||
0x77
|
||||
0x78
|
||||
0x77
|
||||
0x78
|
||||
0x77
|
||||
0x78
|
||||
0x77
|
||||
0x78
|
||||
0x77
|
||||
0x79
|
||||
0x9
|
||||
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x78
|
||||
0x69
|
||||
0x9
|
||||
|
||||
0x77
|
||||
0x78
|
||||
0x77
|
||||
0x77
|
||||
0x77
|
||||
0x77
|
||||
0x77
|
||||
0x77
|
||||
0x77
|
||||
0x79
|
||||
0x9
|
||||
>;
|
||||
};
|
||||
|
|
@ -351,10 +351,15 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
dmc: dmc@ff400000 {
|
||||
dmc: dmc {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "rockchip,rk3328-dmc", "syscon";
|
||||
reg = <0x0 0xff400000 0x0 0x1000>;
|
||||
compatible = "rockchip,rk3328-dmc";
|
||||
reg = <0x0 0xff400000 0x0 0x1000
|
||||
0x0 0xff780000 0x0 0x3000
|
||||
0x0 0xff100000 0x0 0x1000
|
||||
0x0 0xff440000 0x0 0x1000
|
||||
0x0 0xff720000 0x0 0x1000
|
||||
0x0 0xff798000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
cru: clock-controller@ff440000 {
|
||||
|
|
|
|||
|
|
@ -3,4 +3,11 @@
|
|||
* Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
|
||||
*/
|
||||
|
||||
#include "rk3399-u-boot.dtsi"
|
||||
#include "rk3399-sdram-ddr3-1600.dtsi"
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
u-boot,spl-boot-order = &sdhci, &sdmmc;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
6
arch/arm/dts/rk3399-khadas-edge-captain-u-boot.dtsi
Normal file
6
arch/arm/dts/rk3399-khadas-edge-captain-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2019 Nick Xie <nick@khadas.com>
|
||||
*/
|
||||
|
||||
#include "rk3399-khadas-edge-u-boot.dtsi"
|
||||
27
arch/arm/dts/rk3399-khadas-edge-captain.dts
Normal file
27
arch/arm/dts/rk3399-khadas-edge-captain.dts
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd.
|
||||
* (https://www.khadas.com)
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk3399-khadas-edge.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Khadas Edge-Captain";
|
||||
compatible = "khadas,edge-captain", "rockchip,rk3399";
|
||||
};
|
||||
|
||||
&gmac {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
ep-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
num-lanes = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
13
arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi
Normal file
13
arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2019 Nick Xie <nick@khadas.com>
|
||||
*/
|
||||
|
||||
#include "rk3399-u-boot.dtsi"
|
||||
#include "rk3399-sdram-lpddr4-100.dtsi"
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
|
||||
};
|
||||
};
|
||||
6
arch/arm/dts/rk3399-khadas-edge-v-u-boot.dtsi
Normal file
6
arch/arm/dts/rk3399-khadas-edge-v-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2019 Nick Xie <nick@khadas.com>
|
||||
*/
|
||||
|
||||
#include "rk3399-khadas-edge-u-boot.dtsi"
|
||||
27
arch/arm/dts/rk3399-khadas-edge-v.dts
Normal file
27
arch/arm/dts/rk3399-khadas-edge-v.dts
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd.
|
||||
* (https://www.khadas.com)
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk3399-khadas-edge.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Khadas Edge-V";
|
||||
compatible = "khadas,edge-v", "rockchip,rk3399";
|
||||
};
|
||||
|
||||
&gmac {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
ep-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
num-lanes = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
13
arch/arm/dts/rk3399-khadas-edge.dts
Normal file
13
arch/arm/dts/rk3399-khadas-edge.dts
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd.
|
||||
* (https://www.khadas.com)
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk3399-khadas-edge.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Khadas Edge";
|
||||
compatible = "khadas,edge", "rockchip,rk3399";
|
||||
};
|
||||
804
arch/arm/dts/rk3399-khadas-edge.dtsi
Normal file
804
arch/arm/dts/rk3399-khadas-edge.dtsi
Normal file
|
|
@ -0,0 +1,804 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd.
|
||||
* (https://www.khadas.com)
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/input/linux-event-codes.h>
|
||||
#include <dt-bindings/pwm/pwm.h>
|
||||
#include "rk3399.dtsi"
|
||||
#include "rk3399-opp.dtsi"
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
clkin_gmac: external-gmac-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <125000000>;
|
||||
clock-output-names = "clkin_gmac";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
sdio_pwrseq: sdio-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
clocks = <&rk808 1>;
|
||||
clock-names = "ext_clock";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_enable_h>;
|
||||
|
||||
/*
|
||||
* On the module itself this is one of these (depending
|
||||
* on the actual card populated):
|
||||
* - SDIO_RESET_L_WL_REG_ON
|
||||
* - PDN (power down when low)
|
||||
*/
|
||||
reset-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
/* switched by pmic_sleep */
|
||||
vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc1v8_s3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc_1v8>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie: vcc3v3-pcie-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_pcie";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vsys_3v3>;
|
||||
};
|
||||
|
||||
/* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
|
||||
vcc5v0_host: vcc5v0-host-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_host_en>;
|
||||
regulator-name = "vcc5v0_host";
|
||||
regulator-always-on;
|
||||
vin-supply = <&vsys_5v0>;
|
||||
};
|
||||
|
||||
vdd_log: vdd-log {
|
||||
compatible = "pwm-regulator";
|
||||
pwms = <&pwm2 0 25000 1>;
|
||||
regulator-name = "vdd_log";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
vin-supply = <&vsys_3v3>;
|
||||
};
|
||||
|
||||
vsys: vsys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vsys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vsys_3v3: vsys-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vsys_3v3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vsys>;
|
||||
};
|
||||
|
||||
vsys_5v0: vsys-5v0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vsys_5v0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vsys>;
|
||||
};
|
||||
|
||||
adc-keys {
|
||||
compatible = "adc-keys";
|
||||
io-channels = <&saradc 1>;
|
||||
io-channel-names = "buttons";
|
||||
keyup-threshold-microvolt = <1800000>;
|
||||
poll-interval = <100>;
|
||||
|
||||
recovery {
|
||||
label = "Recovery";
|
||||
linux,code = <KEY_VENDOR>;
|
||||
press-threshold-microvolt = <18000>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
autorepeat;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwrbtn>;
|
||||
|
||||
power {
|
||||
debounce-interval = <100>;
|
||||
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
|
||||
label = "GPIO Key Power";
|
||||
linux,code = <KEY_POWER>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sys_led_gpio>, <&user_led_gpio>;
|
||||
|
||||
sys-led {
|
||||
label = "sys_led";
|
||||
linux,default-trigger = "heartbeat";
|
||||
gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
user-led {
|
||||
label = "user_led";
|
||||
default-state = "off";
|
||||
gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
fan: pwm-fan {
|
||||
compatible = "pwm-fan";
|
||||
cooling-levels = <0 150 200 255>;
|
||||
#cooling-cells = <2>;
|
||||
fan-supply = <&vsys_5v0>;
|
||||
pwms = <&pwm0 0 40000 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpu_l0 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_l1 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_l2 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_l3 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_b0 {
|
||||
cpu-supply = <&vdd_cpu_b>;
|
||||
};
|
||||
|
||||
&cpu_b1 {
|
||||
cpu-supply = <&vdd_cpu_b>;
|
||||
};
|
||||
|
||||
&cpu_thermal {
|
||||
trips {
|
||||
cpu_warm: cpu_warm {
|
||||
temperature = <55000>;
|
||||
hysteresis = <2000>;
|
||||
type = "active";
|
||||
};
|
||||
|
||||
cpu_hot: cpu_hot {
|
||||
temperature = <65000>;
|
||||
hysteresis = <2000>;
|
||||
type = "active";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map2 {
|
||||
trip = <&cpu_warm>;
|
||||
cooling-device = <&fan THERMAL_NO_LIMIT 1>;
|
||||
};
|
||||
|
||||
map3 {
|
||||
trip = <&cpu_hot>;
|
||||
cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&emmc_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac {
|
||||
assigned-clocks = <&cru SCLK_RMII_SRC>;
|
||||
assigned-clock-parents = <&clkin_gmac>;
|
||||
clock_in_out = "input";
|
||||
phy-supply = <&vcc_lan>;
|
||||
phy-mode = "rgmii";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii_pins>;
|
||||
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 10000 50000>;
|
||||
tx_delay = <0x28>;
|
||||
rx_delay = <0x11>;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu_thermal {
|
||||
trips {
|
||||
gpu_warm: gpu_warm {
|
||||
temperature = <55000>;
|
||||
hysteresis = <2000>;
|
||||
type = "active";
|
||||
};
|
||||
|
||||
gpu_hot: gpu_hot {
|
||||
temperature = <65000>;
|
||||
hysteresis = <2000>;
|
||||
type = "active";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map1 {
|
||||
trip = <&gpu_warm>;
|
||||
cooling-device = <&fan THERMAL_NO_LIMIT 1>;
|
||||
};
|
||||
|
||||
map2 {
|
||||
trip = <&gpu_hot>;
|
||||
cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
ddc-i2c-bus = <&i2c3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_cec>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_sound {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
i2c-scl-rising-time-ns = <450>;
|
||||
i2c-scl-falling-time-ns = <15>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
clock-frequency = <400000>;
|
||||
i2c-scl-rising-time-ns = <168>;
|
||||
i2c-scl-falling-time-ns = <4>;
|
||||
status = "okay";
|
||||
|
||||
rk808: pmic@1b {
|
||||
compatible = "rockchip,rk808";
|
||||
reg = <0x1b>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <RK_PC6 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "xin32k", "rk808-clkout2";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int_l>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vsys_3v3>;
|
||||
vcc2-supply = <&vsys_3v3>;
|
||||
vcc3-supply = <&vsys_3v3>;
|
||||
vcc4-supply = <&vsys_3v3>;
|
||||
vcc6-supply = <&vsys_3v3>;
|
||||
vcc7-supply = <&vsys_3v3>;
|
||||
vcc8-supply = <&vsys_3v3>;
|
||||
vcc9-supply = <&vsys_3v3>;
|
||||
vcc10-supply = <&vsys_3v3>;
|
||||
vcc11-supply = <&vsys_3v3>;
|
||||
vcc12-supply = <&vsys_3v3>;
|
||||
vddio-supply = <&vcc_1v8>;
|
||||
|
||||
regulators {
|
||||
vdd_center: DCDC_REG1 {
|
||||
regulator-name = "vdd_center";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_l: DCDC_REG2 {
|
||||
regulator-name = "vdd_cpu_l";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG4 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc1v8_apio2: LDO_REG1 {
|
||||
regulator-name = "vcc1v8_apio2";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_vldo2: LDO_REG2 {
|
||||
regulator-name = "vcc_vldo2";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc1v8_pmupll: LDO_REG3 {
|
||||
regulator-name = "vcc1v8_pmupll";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG4 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_vldo5: LDO_REG5 {
|
||||
regulator-name = "vcc_vldo5";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v5: LDO_REG6 {
|
||||
regulator-name = "vcc_1v5";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1500000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc1v8_codec: LDO_REG7 {
|
||||
regulator-name = "vcc1v8_codec";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v0: LDO_REG8 {
|
||||
regulator-name = "vcc_3v0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_s3: vcc_lan: SWITCH_REG1 {
|
||||
regulator-name = "vcc3v3_s3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_s0: SWITCH_REG2 {
|
||||
regulator-name = "vcc3v3_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_b: regulator@40 {
|
||||
compatible = "silergy,syr827";
|
||||
reg = <0x40>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cpu_b_sleep>;
|
||||
regulator-name = "vdd_cpu_b";
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-ramp-delay = <1000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vsys_3v3>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: regulator@41 {
|
||||
compatible = "silergy,syr828";
|
||||
reg = <0x41>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gpu_sleep>;
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-ramp-delay = <1000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vsys_3v3>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c8 {
|
||||
clock-frequency = <400000>;
|
||||
i2c-scl-rising-time-ns = <160>;
|
||||
i2c-scl-falling-time-ns = <30>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2s0 {
|
||||
rockchip,playback-channels = <8>;
|
||||
rockchip,capture-channels = <8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2s1 {
|
||||
rockchip,playback-channels = <2>;
|
||||
rockchip,capture-channels = <2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2s2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&io_domains {
|
||||
bt656-supply = <&vcc1v8_apio2>;
|
||||
audio-supply = <&vcc1v8_codec>;
|
||||
sdmmc-supply = <&vccio_sd>;
|
||||
gpio1830-supply = <&vcc_3v0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmu1830-supply = <&vcc_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
bt {
|
||||
bt_host_wake_l: bt-host-wake-l {
|
||||
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
bt_reg_on_h: bt-reg-on-h {
|
||||
rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
bt_wake_l: bt-wake-l {
|
||||
rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
buttons {
|
||||
pwrbtn: pwrbtn {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
sys_led_gpio: sys_led-gpio {
|
||||
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
user_led_gpio: user_led-gpio {
|
||||
rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int_l: pmic-int-l {
|
||||
rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
cpu_b_sleep: cpu-b-sleep {
|
||||
rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
|
||||
gpu_sleep: gpu-sleep {
|
||||
rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio-pwrseq {
|
||||
wifi_enable_h: wifi-enable-h {
|
||||
rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb2 {
|
||||
vcc5v0_host_en: vcc5v0-host-en {
|
||||
rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
wifi {
|
||||
wifi_host_wake_l: wifi-host-wake-l {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca1v8_s3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdio0 {
|
||||
/* WiFi & BT combo module Ampak AP6356S */
|
||||
bus-width = <4>;
|
||||
cap-sdio-irq;
|
||||
cap-sd-highspeed;
|
||||
keep-power-in-suspend;
|
||||
mmc-pwrseq = <&sdio_pwrseq>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
|
||||
sd-uhs-sdr104;
|
||||
vqmmc-supply = <&vcc1v8_s3>;
|
||||
vmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
|
||||
brcmf: wifi@1 {
|
||||
compatible = "brcm,bcm4329-fmac";
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
interrupt-names = "host-wake";
|
||||
brcm,drive-strength = <5>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_host_wake_l>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
max-frequency = <150000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
mmc-hs400-1_8v;
|
||||
mmc-hs400-enhanced-strobe;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tcphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tcphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
/* tshut mode 0:CRU 1:GPIO */
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
/* tshut polarity 0:LOW 1:HIGH */
|
||||
rockchip,hw-tshut-polarity = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0 {
|
||||
status = "okay";
|
||||
|
||||
u2phy0_otg: otg-port {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
u2phy0_host: host-port {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&u2phy1 {
|
||||
status = "okay";
|
||||
|
||||
u2phy1_otg: otg-port {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
u2phy1_host: host-port {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>;
|
||||
status = "okay";
|
||||
|
||||
bluetooth {
|
||||
compatible = "brcm,bcm43438-bt";
|
||||
clocks = <&rk808 1>;
|
||||
clock-names = "lpo";
|
||||
device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
|
||||
host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
|
||||
shutdown-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
|
||||
max-speed = <4000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>;
|
||||
vbat-supply = <&vsys_3v3>;
|
||||
vddio-supply = <&vcc_1v8>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd3_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3_0 {
|
||||
status = "okay";
|
||||
dr_mode = "otg";
|
||||
};
|
||||
|
||||
&usbdrd3_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3_1 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&vopb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -3,4 +3,11 @@
|
|||
* Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
|
||||
*/
|
||||
|
||||
#include "rk3399-u-boot.dtsi"
|
||||
#include "rk3399-sdram-lpddr3-2GB-1600.dtsi"
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
u-boot,spl-boot-order = &sdhci, &sdmmc;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
441
arch/arm/include/asm/arch-rockchip/sdram_rk3328.h
Normal file
441
arch/arm/include/asm/arch-rockchip/sdram_rk3328.h
Normal file
|
|
@ -0,0 +1,441 @@
|
|||
/*
|
||||
* Copyright (C) 2016-2017 Rockchip Electronics Co., Ltd
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARCH_SDRAM_RK3328_H
|
||||
#define _ASM_ARCH_SDRAM_RK3328_H
|
||||
|
||||
#define SR_IDLE 93
|
||||
#define PD_IDLE 13
|
||||
#define SDRAM_ADDR 0x00000000
|
||||
#define PATTERN (0x5aa5f00f)
|
||||
|
||||
/* ddr pctl registers define */
|
||||
#define DDR_PCTL2_MSTR 0x0
|
||||
#define DDR_PCTL2_STAT 0x4
|
||||
#define DDR_PCTL2_MSTR1 0x8
|
||||
#define DDR_PCTL2_MRCTRL0 0x10
|
||||
#define DDR_PCTL2_MRCTRL1 0x14
|
||||
#define DDR_PCTL2_MRSTAT 0x18
|
||||
#define DDR_PCTL2_MRCTRL2 0x1c
|
||||
#define DDR_PCTL2_DERATEEN 0x20
|
||||
#define DDR_PCTL2_DERATEINT 0x24
|
||||
#define DDR_PCTL2_PWRCTL 0x30
|
||||
#define DDR_PCTL2_PWRTMG 0x34
|
||||
#define DDR_PCTL2_HWLPCTL 0x38
|
||||
#define DDR_PCTL2_RFSHCTL0 0x50
|
||||
#define DDR_PCTL2_RFSHCTL1 0x54
|
||||
#define DDR_PCTL2_RFSHCTL2 0x58
|
||||
#define DDR_PCTL2_RFSHCTL4 0x5c
|
||||
#define DDR_PCTL2_RFSHCTL3 0x60
|
||||
#define DDR_PCTL2_RFSHTMG 0x64
|
||||
#define DDR_PCTL2_RFSHTMG1 0x68
|
||||
#define DDR_PCTL2_RFSHCTL5 0x6c
|
||||
#define DDR_PCTL2_INIT0 0xd0
|
||||
#define DDR_PCTL2_INIT1 0xd4
|
||||
#define DDR_PCTL2_INIT2 0xd8
|
||||
#define DDR_PCTL2_INIT3 0xdc
|
||||
#define DDR_PCTL2_INIT4 0xe0
|
||||
#define DDR_PCTL2_INIT5 0xe4
|
||||
#define DDR_PCTL2_INIT6 0xe8
|
||||
#define DDR_PCTL2_INIT7 0xec
|
||||
#define DDR_PCTL2_DIMMCTL 0xf0
|
||||
#define DDR_PCTL2_RANKCTL 0xf4
|
||||
#define DDR_PCTL2_CHCTL 0xfc
|
||||
#define DDR_PCTL2_DRAMTMG0 0x100
|
||||
#define DDR_PCTL2_DRAMTMG1 0x104
|
||||
#define DDR_PCTL2_DRAMTMG2 0x108
|
||||
#define DDR_PCTL2_DRAMTMG3 0x10c
|
||||
#define DDR_PCTL2_DRAMTMG4 0x110
|
||||
#define DDR_PCTL2_DRAMTMG5 0x114
|
||||
#define DDR_PCTL2_DRAMTMG6 0x118
|
||||
#define DDR_PCTL2_DRAMTMG7 0x11c
|
||||
#define DDR_PCTL2_DRAMTMG8 0x120
|
||||
#define DDR_PCTL2_DRAMTMG9 0x124
|
||||
#define DDR_PCTL2_DRAMTMG10 0x128
|
||||
#define DDR_PCTL2_DRAMTMG11 0x12c
|
||||
#define DDR_PCTL2_DRAMTMG12 0x130
|
||||
#define DDR_PCTL2_DRAMTMG13 0x134
|
||||
#define DDR_PCTL2_DRAMTMG14 0x138
|
||||
#define DDR_PCTL2_DRAMTMG15 0x13c
|
||||
#define DDR_PCTL2_DRAMTMG16 0x140
|
||||
#define DDR_PCTL2_ZQCTL0 0x180
|
||||
#define DDR_PCTL2_ZQCTL1 0x184
|
||||
#define DDR_PCTL2_ZQCTL2 0x188
|
||||
#define DDR_PCTL2_ZQSTAT 0x18c
|
||||
#define DDR_PCTL2_DFITMG0 0x190
|
||||
#define DDR_PCTL2_DFITMG1 0x194
|
||||
#define DDR_PCTL2_DFILPCFG0 0x198
|
||||
#define DDR_PCTL2_DFILPCFG1 0x19c
|
||||
#define DDR_PCTL2_DFIUPD0 0x1a0
|
||||
#define DDR_PCTL2_DFIUPD1 0x1a4
|
||||
#define DDR_PCTL2_DFIUPD2 0x1a8
|
||||
#define DDR_PCTL2_DFIMISC 0x1b0
|
||||
#define DDR_PCTL2_DFITMG2 0x1b4
|
||||
#define DDR_PCTL2_DFITMG3 0x1b8
|
||||
#define DDR_PCTL2_DFISTAT 0x1bc
|
||||
#define DDR_PCTL2_DBICTL 0x1c0
|
||||
#define DDR_PCTL2_ADDRMAP0 0x200
|
||||
#define DDR_PCTL2_ADDRMAP1 0x204
|
||||
#define DDR_PCTL2_ADDRMAP2 0x208
|
||||
#define DDR_PCTL2_ADDRMAP3 0x20c
|
||||
#define DDR_PCTL2_ADDRMAP4 0x210
|
||||
#define DDR_PCTL2_ADDRMAP5 0x214
|
||||
#define DDR_PCTL2_ADDRMAP6 0x218
|
||||
#define DDR_PCTL2_ADDRMAP7 0x21c
|
||||
#define DDR_PCTL2_ADDRMAP8 0x220
|
||||
#define DDR_PCTL2_ADDRMAP9 0x224
|
||||
#define DDR_PCTL2_ADDRMAP10 0x228
|
||||
#define DDR_PCTL2_ADDRMAP11 0x22c
|
||||
#define DDR_PCTL2_ODTCFG 0x240
|
||||
#define DDR_PCTL2_ODTMAP 0x244
|
||||
#define DDR_PCTL2_SCHED 0x250
|
||||
#define DDR_PCTL2_SCHED1 0x254
|
||||
#define DDR_PCTL2_PERFHPR1 0x25c
|
||||
#define DDR_PCTL2_PERFLPR1 0x264
|
||||
#define DDR_PCTL2_PERFWR1 0x26c
|
||||
#define DDR_PCTL2_DQMAP0 0x280
|
||||
#define DDR_PCTL2_DQMAP1 0x284
|
||||
#define DDR_PCTL2_DQMAP2 0x288
|
||||
#define DDR_PCTL2_DQMAP3 0x28c
|
||||
#define DDR_PCTL2_DQMAP4 0x290
|
||||
#define DDR_PCTL2_DQMAP5 0x294
|
||||
#define DDR_PCTL2_DBG0 0x300
|
||||
#define DDR_PCTL2_DBG1 0x304
|
||||
#define DDR_PCTL2_DBGCAM 0x308
|
||||
#define DDR_PCTL2_DBGCMD 0x30c
|
||||
#define DDR_PCTL2_DBGSTAT 0x310
|
||||
#define DDR_PCTL2_SWCTL 0x320
|
||||
#define DDR_PCTL2_SWSTAT 0x324
|
||||
#define DDR_PCTL2_POISONCFG 0x36c
|
||||
#define DDR_PCTL2_POISONSTAT 0x370
|
||||
#define DDR_PCTL2_ADVECCINDEX 0x374
|
||||
#define DDR_PCTL2_ADVECCSTAT 0x378
|
||||
#define DDR_PCTL2_PSTAT 0x3fc
|
||||
#define DDR_PCTL2_PCCFG 0x400
|
||||
#define DDR_PCTL2_PCFGR_n 0x404
|
||||
#define DDR_PCTL2_PCFGW_n 0x408
|
||||
#define DDR_PCTL2_PCTRL_n 0x490
|
||||
|
||||
/* PCTL2_MRSTAT */
|
||||
#define MR_WR_BUSY BIT(0)
|
||||
|
||||
/* PHY_REG0 */
|
||||
#define DIGITAL_DERESET BIT(3)
|
||||
#define ANALOG_DERESET BIT(2)
|
||||
#define DIGITAL_RESET (0 << 3)
|
||||
#define ANALOG_RESET (0 << 2)
|
||||
|
||||
/* PHY_REG1 */
|
||||
#define PHY_DDR2 (0)
|
||||
#define PHY_LPDDR2 (1)
|
||||
#define PHY_DDR3 (2)
|
||||
#define PHY_LPDDR3 (3)
|
||||
#define PHY_DDR4 (4)
|
||||
#define PHY_BL_4 (0 << 2)
|
||||
#define PHY_BL_8 BIT(2)
|
||||
|
||||
/* PHY_REG2 */
|
||||
#define PHY_DTT_EN BIT(0)
|
||||
#define PHY_DTT_DISB (0 << 0)
|
||||
#define PHY_WRITE_LEVELING_EN BIT(2)
|
||||
#define PHY_WRITE_LEVELING_DISB (0 << 2)
|
||||
#define PHY_SELECT_CS0 (2)
|
||||
#define PHY_SELECT_CS1 (1)
|
||||
#define PHY_SELECT_CS0_1 (0)
|
||||
#define PHY_WRITE_LEVELING_SELECTCS(n) (n << 6)
|
||||
#define PHY_DATA_TRAINING_SELECTCS(n) (n << 4)
|
||||
|
||||
#define PHY_DDR3_RON_RTT_DISABLE (0)
|
||||
#define PHY_DDR3_RON_RTT_451ohm (1)
|
||||
#define PHY_DDR3_RON_RTT_225ohm (2)
|
||||
#define PHY_DDR3_RON_RTT_150ohm (3)
|
||||
#define PHY_DDR3_RON_RTT_112ohm (4)
|
||||
#define PHY_DDR3_RON_RTT_90ohm (5)
|
||||
#define PHY_DDR3_RON_RTT_75ohm (6)
|
||||
#define PHY_DDR3_RON_RTT_64ohm (7)
|
||||
#define PHY_DDR3_RON_RTT_56ohm (16)
|
||||
#define PHY_DDR3_RON_RTT_50ohm (17)
|
||||
#define PHY_DDR3_RON_RTT_45ohm (18)
|
||||
#define PHY_DDR3_RON_RTT_41ohm (19)
|
||||
#define PHY_DDR3_RON_RTT_37ohm (20)
|
||||
#define PHY_DDR3_RON_RTT_34ohm (21)
|
||||
#define PHY_DDR3_RON_RTT_33ohm (22)
|
||||
#define PHY_DDR3_RON_RTT_30ohm (23)
|
||||
#define PHY_DDR3_RON_RTT_28ohm (24)
|
||||
#define PHY_DDR3_RON_RTT_26ohm (25)
|
||||
#define PHY_DDR3_RON_RTT_25ohm (26)
|
||||
#define PHY_DDR3_RON_RTT_23ohm (27)
|
||||
#define PHY_DDR3_RON_RTT_22ohm (28)
|
||||
#define PHY_DDR3_RON_RTT_21ohm (29)
|
||||
#define PHY_DDR3_RON_RTT_20ohm (30)
|
||||
#define PHY_DDR3_RON_RTT_19ohm (31)
|
||||
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_DISABLE (0)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_480ohm (1)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_240ohm (2)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_160ohm (3)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_120ohm (4)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_96ohm (5)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_80ohm (6)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_68ohm (7)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_60ohm (16)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_53ohm (17)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_48ohm (18)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_43ohm (19)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_40ohm (20)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_37ohm (21)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_34ohm (22)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_32ohm (23)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_30ohm (24)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_28ohm (25)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_26ohm (26)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_25ohm (27)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_24ohm (28)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_22ohm (29)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_21ohm (30)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_20ohm (31)
|
||||
|
||||
/* noc registers define */
|
||||
#define DDRCONF 0x8
|
||||
#define DDRTIMING 0xc
|
||||
#define DDRMODE 0x10
|
||||
#define READLATENCY 0x14
|
||||
#define AGING0 0x18
|
||||
#define AGING1 0x1c
|
||||
#define AGING2 0x20
|
||||
#define AGING3 0x24
|
||||
#define AGING4 0x28
|
||||
#define AGING5 0x2c
|
||||
#define ACTIVATE 0x38
|
||||
#define DEVTODEV 0x3c
|
||||
#define DDR4TIMING 0x40
|
||||
|
||||
/* DDR GRF */
|
||||
#define DDR_GRF_CON(n) (0 + (n) * 4)
|
||||
#define DDR_GRF_STATUS_BASE (0X100)
|
||||
#define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4)
|
||||
|
||||
/* CRU_SOFTRESET_CON5 */
|
||||
#define ddrphy_psrstn_req(n) (((0x1 << 15) << 16) | (n << 15))
|
||||
#define ddrphy_srstn_req(n) (((0x1 << 14) << 16) | (n << 14))
|
||||
#define ddrctrl_psrstn_req(n) (((0x1 << 13) << 16) | (n << 13))
|
||||
#define ddrctrl_srstn_req(n) (((0x1 << 12) << 16) | (n << 12))
|
||||
#define ddrmsch_srstn_req(n) (((0x1 << 11) << 16) | (n << 11))
|
||||
#define msch_srstn_req(n) (((0x1 << 9) << 16) | (n << 9))
|
||||
#define dfimon_srstn_req(n) (((0x1 << 8) << 16) | (n << 8))
|
||||
#define grf_ddr_srstn_req(n) (((0x1 << 7) << 16) | (n << 7))
|
||||
/* CRU_SOFTRESET_CON9 */
|
||||
#define ddrctrl_asrstn_req(n) (((0x1 << 9) << 16) | (n << 9))
|
||||
|
||||
/* CRU register */
|
||||
#define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4)
|
||||
#define CRU_MODE (0x80)
|
||||
#define CRU_GLB_CNT_TH (0x90)
|
||||
#define CRU_CLKSEL_CON_BASE 0x100
|
||||
#define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON_BASE + ((i) * 4))
|
||||
#define CRU_CLKGATE_CON_BASE 0x200
|
||||
#define CRU_CLKGATE_CON(i) (CRU_CLKGATE_CON_BASE + ((i) * 4))
|
||||
#define CRU_CLKSFTRST_CON_BASE 0x300
|
||||
#define CRU_CLKSFTRST_CON(i) (CRU_CLKSFTRST_CON_BASE + ((i) * 4))
|
||||
|
||||
/* CRU_PLL_CON0 */
|
||||
#define PB(n) ((0x1 << (15 + 16)) | ((n) << 15))
|
||||
#define POSTDIV1(n) ((0x7 << (12 + 16)) | ((n) << 12))
|
||||
#define FBDIV(n) ((0xFFF << 16) | (n))
|
||||
|
||||
/* CRU_PLL_CON1 */
|
||||
#define RSTMODE(n) ((0x1 << (15 + 16)) | ((n) << 15))
|
||||
#define RST(n) ((0x1 << (14 + 16)) | ((n) << 14))
|
||||
#define PD(n) ((0x1 << (13 + 16)) | ((n) << 13))
|
||||
#define DSMPD(n) ((0x1 << (12 + 16)) | ((n) << 12))
|
||||
#define LOCK(n) (((n) >> 10) & 0x1)
|
||||
#define POSTDIV2(n) ((0x7 << (6 + 16)) | ((n) << 6))
|
||||
#define REFDIV(n) ((0x3F << 16) | (n))
|
||||
|
||||
union noc_ddrtiming {
|
||||
u32 d32;
|
||||
struct {
|
||||
unsigned acttoact:6;
|
||||
unsigned rdtomiss:6;
|
||||
unsigned wrtomiss:6;
|
||||
unsigned burstlen:3;
|
||||
unsigned rdtowr:5;
|
||||
unsigned wrtord:5;
|
||||
unsigned bwratio:1;
|
||||
} b;
|
||||
} NOC_TIMING_T;
|
||||
|
||||
union noc_activate {
|
||||
u32 d32;
|
||||
struct {
|
||||
unsigned rrd:4;
|
||||
unsigned faw:6;
|
||||
unsigned fawbank:1;
|
||||
unsigned reserved1:21;
|
||||
} b;
|
||||
};
|
||||
|
||||
union noc_devtodev {
|
||||
u32 d32;
|
||||
struct {
|
||||
unsigned busrdtord:2;
|
||||
unsigned busrdtowr:2;
|
||||
unsigned buswrtord:2;
|
||||
unsigned reserved2:26;
|
||||
} b;
|
||||
};
|
||||
|
||||
union noc_ddr4timing {
|
||||
u32 d32;
|
||||
struct {
|
||||
unsigned ccdl:3;
|
||||
unsigned wrtordl:5;
|
||||
unsigned rrdl:4;
|
||||
unsigned reserved2:20;
|
||||
} b;
|
||||
};
|
||||
|
||||
union noc_ddrmode {
|
||||
u32 d32;
|
||||
struct {
|
||||
unsigned autoprecharge:1;
|
||||
unsigned bwratioextended:1;
|
||||
unsigned reserved3:30;
|
||||
} b;
|
||||
};
|
||||
|
||||
u32 addrmap[21][9] = {
|
||||
/* map0 map1 map2 map3 map4 map5 map6 map7 map8 */
|
||||
{22, 0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x06060606,
|
||||
0x06060606, 0x00000f0f, 0x3f3f},
|
||||
{23, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707,
|
||||
0x07070707, 0x00000f0f, 0x3f3f},
|
||||
{23, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808,
|
||||
0x0f080808, 0x00000f0f, 0x3f3f},
|
||||
{24, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808,
|
||||
0x08080808, 0x00000f0f, 0x3f3f},
|
||||
{24, 0x000a0a0a, 0x00000000, 0x00000000, 0x00000000, 0x09090909,
|
||||
0x0f090909, 0x00000f0f, 0x3f3f},
|
||||
{6, 0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x07070707,
|
||||
0x07070707, 0x00000f0f, 0x3f3f},
|
||||
{7, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x08080808,
|
||||
0x08080808, 0x00000f0f, 0x3f3f},
|
||||
{8, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x09090909,
|
||||
0x0f090909, 0x00000f0f, 0x3f3f},
|
||||
{22, 0x001f0808, 0x00000000, 0x00000000, 0x00001f1f, 0x06060606,
|
||||
0x06060606, 0x00000f0f, 0x3f3f},
|
||||
{23, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707,
|
||||
0x0f070707, 0x00000f0f, 0x3f3f},
|
||||
|
||||
{24, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808,
|
||||
0x08080808, 0x00000f0f, 0x0801},
|
||||
{23, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808,
|
||||
0x0f080808, 0x00000f0f, 0x0801},
|
||||
{24, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707,
|
||||
0x07070707, 0x00000f07, 0x0700},
|
||||
{23, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707,
|
||||
0x07070707, 0x00000f0f, 0x0700},
|
||||
{24, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707,
|
||||
0x07070707, 0x00000f07, 0x3f01},
|
||||
{23, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707,
|
||||
0x07070707, 0x00000f0f, 0x3f01},
|
||||
{24, 0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x06060606,
|
||||
0x06060606, 0x00000f06, 0x3f00},
|
||||
{8, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x09090909,
|
||||
0x0f090909, 0x00000f0f, 0x0801},
|
||||
{7, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x08080808,
|
||||
0x08080808, 0x00000f0f, 0x0700},
|
||||
{7, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808,
|
||||
0x08080808, 0x00000f0f, 0x3f01},
|
||||
|
||||
{6, 0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707,
|
||||
0x07070707, 0x00000f07, 0x3f00}
|
||||
};
|
||||
|
||||
struct rk3328_msch_timings {
|
||||
union noc_ddrtiming ddrtiming;
|
||||
union noc_ddrmode ddrmode;
|
||||
u32 readlatency;
|
||||
union noc_activate activate;
|
||||
union noc_devtodev devtodev;
|
||||
union noc_ddr4timing ddr4timing;
|
||||
u32 agingx0;
|
||||
};
|
||||
|
||||
struct rk3328_msch_regs {
|
||||
u32 coreid;
|
||||
u32 revisionid;
|
||||
u32 ddrconf;
|
||||
u32 ddrtiming;
|
||||
u32 ddrmode;
|
||||
u32 readlatency;
|
||||
u32 aging0;
|
||||
u32 aging1;
|
||||
u32 aging2;
|
||||
u32 aging3;
|
||||
u32 aging4;
|
||||
u32 aging5;
|
||||
u32 reserved[2];
|
||||
u32 activate;
|
||||
u32 devtodev;
|
||||
u32 ddr4_timing;
|
||||
};
|
||||
|
||||
struct rk3328_ddr_grf_regs {
|
||||
u32 ddr_grf_con[4];
|
||||
u32 reserved[(0x100 - 0x10) / 4];
|
||||
u32 ddr_grf_status[11];
|
||||
};
|
||||
|
||||
struct rk3328_ddr_pctl_regs {
|
||||
u32 pctl[30][2];
|
||||
};
|
||||
|
||||
struct rk3328_ddr_phy_regs {
|
||||
u32 phy[5][2];
|
||||
};
|
||||
|
||||
struct rk3328_ddr_skew {
|
||||
u32 a0_a1_skew[15];
|
||||
u32 cs0_dm0_skew[11];
|
||||
u32 cs0_dm1_skew[11];
|
||||
u32 cs0_dm2_skew[11];
|
||||
u32 cs0_dm3_skew[11];
|
||||
u32 cs1_dm0_skew[11];
|
||||
u32 cs1_dm1_skew[11];
|
||||
u32 cs1_dm2_skew[11];
|
||||
u32 cs1_dm3_skew[11];
|
||||
};
|
||||
|
||||
struct rk3328_sdram_channel {
|
||||
unsigned int rank;
|
||||
unsigned int col;
|
||||
/* 3:8bank, 2:4bank */
|
||||
unsigned int bk;
|
||||
/* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
|
||||
unsigned int bw;
|
||||
/* die buswidth, 2:32bit, 1:16bit, 0:8bit */
|
||||
unsigned int dbw;
|
||||
unsigned int row_3_4;
|
||||
unsigned int cs0_row;
|
||||
unsigned int cs1_row;
|
||||
unsigned int ddrconfig;
|
||||
struct rk3328_msch_timings noc_timings;
|
||||
};
|
||||
|
||||
struct rk3328_sdram_params {
|
||||
struct rk3328_sdram_channel ch;
|
||||
unsigned int ddr_freq;
|
||||
unsigned int dramtype;
|
||||
unsigned int odt;
|
||||
struct rk3328_ddr_pctl_regs pctl_regs;
|
||||
struct rk3328_ddr_phy_regs phy_regs;
|
||||
struct rk3328_ddr_skew skew;
|
||||
};
|
||||
|
||||
#define PHY_REG(base, n) (base + 4 * (n))
|
||||
|
||||
#endif
|
||||
|
|
@ -110,9 +110,14 @@ config ROCKCHIP_RK3328
|
|||
select ARM64
|
||||
select SUPPORT_SPL
|
||||
select SPL
|
||||
select SUPPORT_TPL
|
||||
select TPL
|
||||
select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL
|
||||
select TPL_NEEDS_SEPARATE_STACK if TPL
|
||||
imply ROCKCHIP_COMMON_BOARD
|
||||
imply SPL_ROCKCHIP_COMMON_BOARD
|
||||
imply SPL_SERIAL_SUPPORT
|
||||
imply TPL_SERIAL_SUPPORT
|
||||
imply SPL_SEPARATE_BSS
|
||||
select ENABLE_ARM_SOC_BOOT0_HOOK
|
||||
select DEBUG_UART_BOARD_INIT
|
||||
|
|
|
|||
|
|
@ -27,6 +27,18 @@ config SPL_LIBCOMMON_SUPPORT
|
|||
config SPL_LIBGENERIC_SUPPORT
|
||||
default y
|
||||
|
||||
config TPL_LDSCRIPT
|
||||
default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
|
||||
|
||||
config TPL_TEXT_BASE
|
||||
default 0xff091000
|
||||
|
||||
config TPL_MAX_SIZE
|
||||
default 28672
|
||||
|
||||
config TPL_STACK
|
||||
default 0xff098000
|
||||
|
||||
source "board/rockchip/evb_rk3328/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
#define CRU_BASE 0xFF440000
|
||||
#define GRF_BASE 0xFF100000
|
||||
#define UART2_BASE 0xFF130000
|
||||
#define FW_DDR_CON_REG 0xFF7C0040
|
||||
|
||||
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
|
||||
[BROM_BOOTSOURCE_EMMC] = "rksdmmc@ff520000",
|
||||
|
|
@ -46,8 +47,12 @@ struct mm_region *mem_map = rk3328_mem_map;
|
|||
|
||||
int arch_cpu_init(void)
|
||||
{
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
/* We do some SoC one time setting here. */
|
||||
|
||||
/* Disable the ddr secure region setting to make it non-secure */
|
||||
rk_setreg(FW_DDR_CON_REG, 0x200);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -6,6 +6,24 @@ F: include/configs/evb_rk3399.h
|
|||
F: configs/evb-rk3399_defconfig
|
||||
F: configs/firefly-rk3399_defconfig
|
||||
|
||||
KHADAS-EDGE
|
||||
M: Nick Xie <nick@khadas.com>
|
||||
S: Maintained
|
||||
F: configs/khadas-edge-rk3399_defconfig
|
||||
F: arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi
|
||||
|
||||
KHADAS-EDGE-CAPTAIN
|
||||
M: Nick Xie <nick@khadas.com>
|
||||
S: Maintained
|
||||
F: configs/khadas-edge-captain-rk3399_defconfig
|
||||
F: arch/arm/dts/rk3399-khadas-edge-captain-u-boot.dtsi
|
||||
|
||||
KHADAS-EDGE-V
|
||||
M: Nick Xie <nick@khadas.com>
|
||||
S: Maintained
|
||||
F: configs/khadas-edge-v-rk3399_defconfig
|
||||
F: arch/arm/dts/rk3399-khadas-edge-v-u-boot.dtsi
|
||||
|
||||
NANOPC-T4
|
||||
M: Jagan Teki <jagan@amarulasolutions.com>
|
||||
S: Maintained
|
||||
|
|
|
|||
|
|
@ -1,5 +1,11 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_TPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_TPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
|
||||
CONFIG_SYS_TEXT_BASE=0x00200000
|
||||
CONFIG_ROCKCHIP_RK3328=y
|
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
|
|
@ -9,31 +15,50 @@ CONFIG_DEBUG_UART_CLOCK=24000000
|
|||
CONFIG_DEBUG_UART=y
|
||||
# CONFIG_ANDROID_BOOT_IMAGE is not set
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-evb.dtb"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_TPL_SYS_MALLOC_SIMPLE=y
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_ATF_SUPPORT=y
|
||||
CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
|
||||
CONFIG_TPL_BOOTROM_SUPPORT=y
|
||||
CONFIG_TPL_DRIVERS_MISC_SUPPORT=y
|
||||
CONFIG_TPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_TPL_SERIAL_PRESENT=y
|
||||
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000
|
||||
CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3328-evb"
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3328-evb"
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_TPL_OF_CONTROL=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_TPL_DM=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_TPL_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_TPL_SYSCON=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_SPL_CLK=y
|
||||
CONFIG_TPL_CLK=y
|
||||
CONFIG_FASTBOOT_BUF_ADDR=0x800800
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=1
|
||||
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
CONFIG_TPL_OF_PLATDATA=y
|
||||
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
|
|
@ -44,6 +69,7 @@ CONFIG_ETH_DESIGNWARE=y
|
|||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_PHY=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_PMIC_RK8XX=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
|
|
@ -51,9 +77,14 @@ CONFIG_DM_REGULATOR_FIXED=y
|
|||
CONFIG_REGULATOR_RK8XX=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_RAM=y
|
||||
CONFIG_SPL_RAM=y
|
||||
CONFIG_TPL_RAM=y
|
||||
CONFIG_BAUDRATE=1500000
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_DEBUG_UART_ANNOUNCE=y
|
||||
CONFIG_DEBUG_UART_SKIP_INIT=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
|
|
@ -69,4 +100,6 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x2207
|
|||
CONFIG_USB_GADGET_PRODUCT_NUM=0x330a
|
||||
CONFIG_USB_GADGET_DWC2_OTG=y
|
||||
CONFIG_USE_TINY_PRINTF=y
|
||||
CONFIG_SPL_TINY_MEMSET=y
|
||||
CONFIG_TPL_TINY_MEMSET=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
|
|
|
|||
60
configs/khadas-edge-captain-rk3399_defconfig
Normal file
60
configs/khadas-edge-captain-rk3399_defconfig
Normal file
|
|
@ -0,0 +1,60 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x00200000
|
||||
CONFIG_ROCKCHIP_RK3399=y
|
||||
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_SPL_STACK_R_ADDR=0x80000
|
||||
CONFIG_DEBUG_UART_BASE=0xFF1A0000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-captain.dtbi"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
|
||||
CONFIG_TPL=y
|
||||
CONFIG_SYS_PROMPT="kedge# "
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3399-khadas-edge-captain"
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_PMIC_RK8XX=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_REGULATOR_RK8XX=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_RAM_RK3399_LPDDR4=y
|
||||
CONFIG_BAUDRATE=1500000
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_ETHER_ASIX=y
|
||||
CONFIG_USB_ETHER_ASIX88179=y
|
||||
CONFIG_USB_ETHER_MCS7830=y
|
||||
CONFIG_USB_ETHER_RTL8152=y
|
||||
CONFIG_USB_ETHER_SMSC95XX=y
|
||||
CONFIG_SPL_TINY_MEMSET=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
59
configs/khadas-edge-rk3399_defconfig
Normal file
59
configs/khadas-edge-rk3399_defconfig
Normal file
|
|
@ -0,0 +1,59 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x00200000
|
||||
CONFIG_ROCKCHIP_RK3399=y
|
||||
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_SPL_STACK_R_ADDR=0x80000
|
||||
CONFIG_DEBUG_UART_BASE=0xFF1A0000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge.dtb"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
|
||||
CONFIG_TPL=y
|
||||
CONFIG_SYS_PROMPT="kedge# "
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3399-khadas-edge"
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_PMIC_RK8XX=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_REGULATOR_RK8XX=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_RAM_RK3399_LPDDR4=y
|
||||
CONFIG_BAUDRATE=1500000
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_ETHER_ASIX=y
|
||||
CONFIG_USB_ETHER_ASIX88179=y
|
||||
CONFIG_USB_ETHER_MCS7830=y
|
||||
CONFIG_USB_ETHER_RTL8152=y
|
||||
CONFIG_USB_ETHER_SMSC95XX=y
|
||||
CONFIG_SPL_TINY_MEMSET=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
60
configs/khadas-edge-v-rk3399_defconfig
Normal file
60
configs/khadas-edge-v-rk3399_defconfig
Normal file
|
|
@ -0,0 +1,60 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x00200000
|
||||
CONFIG_ROCKCHIP_RK3399=y
|
||||
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_SPL_STACK_R_ADDR=0x80000
|
||||
CONFIG_DEBUG_UART_BASE=0xFF1A0000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-v.dtbi"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
|
||||
CONFIG_TPL=y
|
||||
CONFIG_SYS_PROMPT="kedge# "
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3399-khadas-edge-v"
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_PMIC_RK8XX=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_REGULATOR_RK8XX=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_RAM_RK3399_LPDDR4=y
|
||||
CONFIG_BAUDRATE=1500000
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_ETHER_ASIX=y
|
||||
CONFIG_USB_ETHER_ASIX88179=y
|
||||
CONFIG_USB_ETHER_MCS7830=y
|
||||
CONFIG_USB_ETHER_RTL8152=y
|
||||
CONFIG_USB_ETHER_SMSC95XX=y
|
||||
CONFIG_SPL_TINY_MEMSET=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
|
|
@ -34,15 +34,20 @@ CONFIG_CMD_USB=y
|
|||
CONFIG_CMD_TIME=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64"
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_TPL_OF_CONTROL=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_TPL_OF_PLATDATA=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_TPL_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_TPL_SYSCON=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_SPL_CLK=y
|
||||
CONFIG_TPL_CLK=y
|
||||
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
|
|
@ -65,6 +70,7 @@ CONFIG_REGULATOR_RK8XX=y
|
|||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_RAM=y
|
||||
CONFIG_SPL_RAM=y
|
||||
CONFIG_TPL_RAM=y
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_BAUDRATE=1500000
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
|
|
@ -85,4 +91,12 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x330a
|
|||
CONFIG_USB_GADGET_DWC2_OTG=y
|
||||
CONFIG_USE_TINY_PRINTF=y
|
||||
CONFIG_SPL_TINY_MEMSET=y
|
||||
CONFIG_TPL_TINY_MEMSET=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
CONFIG_TPL_DM=y
|
||||
CONFIG_TPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_TPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
|
||||
CONFIG_TPL_BOOTROM_SUPPORT=y
|
||||
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
|
||||
CONFIG_TPL_SYS_MALLOC_SIMPLE=y
|
||||
|
|
|
|||
|
|
@ -309,17 +309,11 @@ Booting from an SD card on Pine64 Rock64 (RK3328)
|
|||
=================================================
|
||||
|
||||
For Rock64 rk3328 board the following three parts are required:
|
||||
TPL, SPL, and the u-boot image tree blob. While u-boot-spl.bin and
|
||||
u-boot.itb are to be compiled as usual, TPL is currently not
|
||||
implemented in u-boot, so you need to pick one from rkbin:
|
||||
|
||||
- Get the rkbin
|
||||
|
||||
=> git clone https://github.com/rockchip-linux/rkbin.git
|
||||
TPL, SPL, and the u-boot image tree blob.
|
||||
|
||||
- Create TPL/SPL image
|
||||
|
||||
=> tools/mkimage -n rk3328 -T rksd -d rkbin/bin/rk33/rk3328_ddr_333MHz_v1.16.bin idbloader.img
|
||||
=> tools/mkimage -n rk3328 -T rksd -d tpl/u-boot-tpl.bin idbloader.img
|
||||
=> cat spl/u-boot-spl.bin >> idbloader.img
|
||||
|
||||
- Write TPL/SPL image at 64 sector
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
#include <mmc.h>
|
||||
#include <dwmmc.h>
|
||||
#include <wait_bit.h>
|
||||
#include <power/regulator.h>
|
||||
|
||||
#define PAGE_SIZE 4096
|
||||
|
||||
|
|
@ -493,6 +494,21 @@ static int dwmci_set_ios(struct mmc *mmc)
|
|||
if (host->clksel)
|
||||
host->clksel(host);
|
||||
|
||||
#if CONFIG_IS_ENABLED(DM_REGULATOR)
|
||||
if (mmc->vqmmc_supply) {
|
||||
int ret;
|
||||
|
||||
if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
|
||||
regulator_set_value(mmc->vqmmc_supply, 1800000);
|
||||
else
|
||||
regulator_set_value(mmc->vqmmc_supply, 3300000);
|
||||
|
||||
ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user