mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-28 23:50:26 +09:00
Convert socfpga: select CONFIG_HW_WATCHDOG support for ARCH_SOCFPGA
All Socfpga boards from ./include/configs/socfpga_* define CONFIG_HW_WATCHDOG. To ease CONFIG_HW_WATCHDOG conversion to Kconfig select it in config ARCH_SOCFPGA (arch/arm/Kconfig) section. Signed-off-by: Lukasz Majewski <lukma@denx.de> Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
This commit is contained in:
parent
a6fbf94550
commit
21a9f435f3
@ -701,6 +701,7 @@ config ARCH_SOCFPGA
|
|||||||
select DM_SPI_FLASH
|
select DM_SPI_FLASH
|
||||||
select DM_SPI
|
select DM_SPI
|
||||||
select ENABLE_ARM_SOC_BOOT0_HOOK
|
select ENABLE_ARM_SOC_BOOT0_HOOK
|
||||||
|
select HW_WATCHDOG
|
||||||
select ARCH_EARLY_INIT_R
|
select ARCH_EARLY_INIT_R
|
||||||
select ARCH_MISC_INIT
|
select ARCH_MISC_INIT
|
||||||
select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
|
select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
|
||||||
|
@ -9,8 +9,6 @@
|
|||||||
|
|
||||||
#include <asm/arch/base_addr_a10.h>
|
#include <asm/arch/base_addr_a10.h>
|
||||||
|
|
||||||
#define CONFIG_HW_WATCHDOG
|
|
||||||
|
|
||||||
/* Booting Linux */
|
/* Booting Linux */
|
||||||
#define CONFIG_LOADADDR 0x01000000
|
#define CONFIG_LOADADDR 0x01000000
|
||||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||||
|
@ -8,8 +8,6 @@
|
|||||||
|
|
||||||
#include <asm/arch/base_addr_ac5.h>
|
#include <asm/arch/base_addr_ac5.h>
|
||||||
|
|
||||||
#define CONFIG_HW_WATCHDOG
|
|
||||||
|
|
||||||
/* Memory configurations */
|
/* Memory configurations */
|
||||||
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
|
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
|
||||||
|
|
||||||
|
@ -8,8 +8,6 @@
|
|||||||
|
|
||||||
#include <asm/arch/base_addr_ac5.h>
|
#include <asm/arch/base_addr_ac5.h>
|
||||||
|
|
||||||
#define CONFIG_HW_WATCHDOG
|
|
||||||
|
|
||||||
/* Memory configurations */
|
/* Memory configurations */
|
||||||
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
|
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
|
||||||
|
|
||||||
|
@ -8,8 +8,6 @@
|
|||||||
|
|
||||||
#include <asm/arch/base_addr_ac5.h>
|
#include <asm/arch/base_addr_ac5.h>
|
||||||
|
|
||||||
#define CONFIG_HW_WATCHDOG
|
|
||||||
|
|
||||||
/* Memory configurations */
|
/* Memory configurations */
|
||||||
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */
|
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */
|
||||||
|
|
||||||
|
@ -8,8 +8,6 @@
|
|||||||
|
|
||||||
#include <asm/arch/base_addr_ac5.h>
|
#include <asm/arch/base_addr_ac5.h>
|
||||||
|
|
||||||
#define CONFIG_HW_WATCHDOG
|
|
||||||
|
|
||||||
/* Memory configurations */
|
/* Memory configurations */
|
||||||
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */
|
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */
|
||||||
|
|
||||||
|
@ -8,8 +8,6 @@
|
|||||||
|
|
||||||
#include <asm/arch/base_addr_ac5.h>
|
#include <asm/arch/base_addr_ac5.h>
|
||||||
|
|
||||||
#define CONFIG_HW_WATCHDOG
|
|
||||||
|
|
||||||
/* Memory configurations */
|
/* Memory configurations */
|
||||||
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */
|
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */
|
||||||
|
|
||||||
|
@ -9,8 +9,6 @@
|
|||||||
|
|
||||||
#include <asm/arch/base_addr_ac5.h>
|
#include <asm/arch/base_addr_ac5.h>
|
||||||
|
|
||||||
#define CONFIG_HW_WATCHDOG
|
|
||||||
|
|
||||||
/* Memory configurations */
|
/* Memory configurations */
|
||||||
#define PHYS_SDRAM_1_SIZE 0x10000000
|
#define PHYS_SDRAM_1_SIZE 0x10000000
|
||||||
|
|
||||||
|
@ -8,8 +8,6 @@
|
|||||||
|
|
||||||
#include <asm/arch/base_addr_ac5.h>
|
#include <asm/arch/base_addr_ac5.h>
|
||||||
|
|
||||||
#define CONFIG_HW_WATCHDOG
|
|
||||||
|
|
||||||
/* Memory configurations */
|
/* Memory configurations */
|
||||||
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on MCV */
|
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on MCV */
|
||||||
|
|
||||||
|
@ -8,8 +8,6 @@
|
|||||||
|
|
||||||
#include <asm/arch/base_addr_ac5.h>
|
#include <asm/arch/base_addr_ac5.h>
|
||||||
|
|
||||||
#define CONFIG_HW_WATCHDOG
|
|
||||||
|
|
||||||
/* Memory configurations */
|
/* Memory configurations */
|
||||||
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
|
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
|
||||||
|
|
||||||
|
@ -8,8 +8,6 @@
|
|||||||
|
|
||||||
#include <asm/arch/base_addr_ac5.h>
|
#include <asm/arch/base_addr_ac5.h>
|
||||||
|
|
||||||
#define CONFIG_HW_WATCHDOG
|
|
||||||
|
|
||||||
/* Memory configurations */
|
/* Memory configurations */
|
||||||
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCrates */
|
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCrates */
|
||||||
|
|
||||||
|
@ -8,8 +8,6 @@
|
|||||||
|
|
||||||
#include <asm/arch/base_addr_ac5.h>
|
#include <asm/arch/base_addr_ac5.h>
|
||||||
|
|
||||||
#define CONFIG_HW_WATCHDOG
|
|
||||||
|
|
||||||
/* Memory configurations */
|
/* Memory configurations */
|
||||||
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */
|
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */
|
||||||
|
|
||||||
|
@ -8,8 +8,6 @@
|
|||||||
|
|
||||||
#include <asm/arch/base_addr_ac5.h>
|
#include <asm/arch/base_addr_ac5.h>
|
||||||
|
|
||||||
#define CONFIG_HW_WATCHDOG
|
|
||||||
|
|
||||||
/* Memory configurations */
|
/* Memory configurations */
|
||||||
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on VINING_FPGA */
|
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on VINING_FPGA */
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user