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armv8: Fix TCR macros for shareability attribute

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For ARMv8, outer shareable is 0b10, inner shareable is 0b11 at bit
position [13:12] of TCR_ELx register.

Signed-off-by: Zhichun Hua <zhichun.hua@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Zhichun Hua 2015-06-29 15:49:37 +08:00 committed by York Sun
parent 2519560017
commit 21a257b9b3
1 changed files with 2 additions and 2 deletions
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4
arch/arm/include/asm/armv8/mmu.h
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@ -93,8 +93,8 @@
#define TCR_ORGN_WBNWA (3 << 10)
#define TCR_ORGN_MASK (3 << 10)
#define TCR_SHARED_NON (0 << 12)
#define TCR_SHARED_OUTER (1 << 12)
#define TCR_SHARED_INNER (2 << 12)
#define TCR_SHARED_OUTER (2 << 12)
#define TCR_SHARED_INNER (3 << 12)
#define TCR_TG0_4K (0 << 14)
#define TCR_TG0_64K (1 << 14)
#define TCR_TG0_16K (2 << 14)