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arm64: zynqmp: Sync zynqmp fpga manager with mainline

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Sync zynqmp fpga manager with mainline.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Nava kishore Manne 2019-10-18 18:07:32 +02:00 committed by Michal Simek
parent 39419c21bf
commit 21620990cf
2 changed files with 11 additions and 5 deletions
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4
arch/arm/dts/zynqmp-clk-ccf.dtsi
View File

@ -291,3 +291,7 @@
&xlnx_dp_snd_codec0 {
clocks = <&zynqmp_clk DP_AUDIO_REF>;
};
&zynqmp_pcap {
clocks = <&zynqmp_clk PCAP>;
};

12
arch/arm/dts/zynqmp.dtsi
View File

@ -149,6 +149,11 @@
#power-domain-cells = <0x1>;
u-boot,dm-pre-reloc;
zynqmp_pcap: pcap {
compatible = "xlnx,zynqmp-pcap-fpga";
clock-names = "ref_clk";
};
zynqmp_power: zynqmp-power {
u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-power";
@ -180,9 +185,10 @@
fpga_full: fpga-full {
compatible = "fpga-region";
fpga-mgr = <&pcap>;
fpga-mgr = <&zynqmp_pcap>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
};
nvmem_firmware {
@ -195,10 +201,6 @@
};
};
pcap: pcap {
compatible = "xlnx,zynqmp-pcap-fpga";
};
rst: reset-controller {
compatible = "xlnx,zynqmp-reset";
#reset-cells = <1>;