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https://github.com/brain-hackers/u-boot-brain
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tegra2: Simplify tegra_start() boot path
The Tegra2 boot path is more complicated than it needs to be. Since we want to move to building most of U-Boot with ARMv7 and only a small part with ARMv4T (for AVP) it should be as simple as possible. This makes tegra2_start() into a simple function which either does AVP init or A9 init depending on which core is running it. Both cores now following the same init path, beginning at _start, and the special Tegra2 boot path code is no longer required. Only two files need to be built for ARMv4T, and this is handled in the Tegra2 CPU Makefile. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
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@ -23,6 +23,11 @@
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# MA 02111-1307 USA
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# MA 02111-1307 USA
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#
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#
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# The AVP is ARMv4T architecture so we must use special compiler
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# flags for any startup files it might use.
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CFLAGS_arch/arm/cpu/armv7/tegra2/ap20.o += -march=armv4t
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CFLAGS_arch/arm/cpu/armv7/tegra2/clock.o += -march=armv4t
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include $(TOPDIR)/config.mk
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(SOC).o
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LIB = $(obj)lib$(SOC).o
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@ -31,7 +31,12 @@
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#include <asm/arch/scu.h>
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#include <asm/arch/scu.h>
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#include <common.h>
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#include <common.h>
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u32 s_first_boot = 1;
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/* Returns 1 if the current CPU executing is a Cortex-A9, else 0 */
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static int ap20_cpu_is_cortexa9(void)
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{
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u32 id = readb(NV_PA_PG_UP_BASE + PG_UP_TAG_0);
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return id == (PG_UP_TAG_0_PID_CPU & 0xff);
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}
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void init_pllx(void)
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void init_pllx(void)
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{
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{
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@ -283,38 +288,37 @@ void init_pmc_scratch(void)
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writel(CONFIG_SYS_BOARD_ODMDATA, &pmc->pmc_scratch20);
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writel(CONFIG_SYS_BOARD_ODMDATA, &pmc->pmc_scratch20);
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}
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}
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void cpu_start(void)
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void tegra2_start(void)
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{
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{
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struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
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struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
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/* enable JTAG */
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/* If we are the AVP, start up the first Cortex-A9 */
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writel(0xC0, &pmt->pmt_cfg_ctl);
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if (!ap20_cpu_is_cortexa9()) {
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/* enable JTAG */
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writel(0xC0, &pmt->pmt_cfg_ctl);
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if (s_first_boot) {
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/*
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/*
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* Need to set this before cold-booting,
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* If we are ARM7 - give it a different stack. We are about to
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* otherwise we'll end up in an infinite loop.
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* start up the A9 which will want to use this one.
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*/
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*/
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s_first_boot = 0;
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asm volatile("ldr sp, =%c0\n"
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cold_boot();
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: : "i"(AVP_EARLY_BOOT_STACK_LIMIT));
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}
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}
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void tegra2_start()
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start_cpu((u32)_start);
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{
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halt_avp();
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if (s_first_boot) {
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/* not reached */
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/* Init Debug UART Port (115200 8n1) */
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uart_init();
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/* Init PMC scratch memory */
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init_pmc_scratch();
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}
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}
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#ifdef CONFIG_ENABLE_CORTEXA9
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/* Init PMC scratch memory */
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/* take the mpcore out of reset */
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init_pmc_scratch();
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cpu_start();
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/* configure cache */
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enable_scu();
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cache_configure();
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#endif
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/* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
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asm volatile(
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"mrc p15, 0, r0, c1, c0, 1\n"
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"orr r0, r0, #0x41\n"
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"mcr p15, 0, r0, c1, c0, 1\n");
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/* FIXME: should have ap20's L2 disabled too? */
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}
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}
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@ -102,3 +102,6 @@ void uart_init(void);
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void udelay(unsigned long);
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void udelay(unsigned long);
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void cold_boot(void);
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void cold_boot(void);
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void cache_configure(void);
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void cache_configure(void);
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/* This is the main entry into U-Boot, used by the Cortex-A9 */
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extern void _start(void);
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