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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

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This commit is contained in:
Tom Rini 2014-11-14 16:39:32 -05:00
commit 2086e388d5
26 changed files with 411 additions and 11 deletions
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1
arch/powerpc/cpu/mpc83xx/start.S
View File

@ -283,6 +283,7 @@ in_flash:
bl cpu_init_f
/* run 1st part of board init code (in Flash)*/
li r3, 0 /* clear boot_flag for calling board_init_f */
bl board_init_f
/* NOTREACHED - board_init_f() does not return */

2
arch/powerpc/cpu/mpc85xx/b4860_ids.c
View File

@ -55,7 +55,7 @@ struct liodn_id_table liodn_tbl[] = {
SET_SDHC_LIODN(1, 552),
SET_USB_LIODN(1, "fsl-usb2-mph", 553),
SET_USB_LIODN(1, "fsl-usb2-dr", 553),
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),

6
arch/powerpc/cpu/mpc85xx/cpu_init_early.c
View File

@ -70,9 +70,9 @@ void setup_ifc(void)
#endif
/* Change flash's physical address */
out_be32(&(ifc_regs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
out_be32(&(ifc_regs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
out_be32(&(ifc_regs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
ifc_out32(&(ifc_regs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
ifc_out32(&(ifc_regs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
ifc_out32(&(ifc_regs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
return ;
}

2
arch/powerpc/cpu/mpc85xx/speed.c
View File

@ -430,7 +430,7 @@ void get_sys_info(sys_info_t *sys_info)
#endif
#if defined(CONFIG_FSL_IFC)
ccr = in_be32(&ifc_regs->ifc_ccr);
ccr = ifc_in32(&ifc_regs->ifc_ccr);
ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
sys_info->freq_localbus = sys_info->freq_systembus / ccr;

2
arch/powerpc/include/asm/fsl_memac.h
View File

@ -159,6 +159,7 @@ struct memac {
#define MEMAC_CMD_CFG_RX_EN 0x00000002 /* MAC Rx path enable */
#define MEMAC_CMD_CFG_TX_EN 0x00000001 /* MAC Tx path enable */
#define MEMAC_CMD_CFG_RXTX_EN (MEMAC_CMD_CFG_RX_EN | MEMAC_CMD_CFG_TX_EN)
#define MEMAC_CMD_CFG_NO_LEN_CHK 0x20000 /* Payload length check disable */
/* HASHTABLE_CTRL - Hashtable control register */
#define HASHTABLE_CTRL_MCAST_EN 0x00000200 /* enable mulitcast Rx hash */
@ -243,6 +244,7 @@ struct memac_mdio_controller {
#define MDIO_STAT_PRE (1 << 5)
#define MDIO_STAT_ENC (1 << 6)
#define MDIO_STAT_HOLD_15_CLK (7 << 2)
#define MDIO_STAT_NEG (1 << 23)
#define MDIO_CTL_DEV_ADDR(x) (x & 0x1f)
#define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5)

11
board/freescale/bsc9131rdb/bsc9131rdb.c
View File

@ -15,6 +15,9 @@
#include <fdt_support.h>
#include <fsl_mdio.h>
#include <tsec.h>
#include <jffs2/load_kernel.h>
#include <mtd_node.h>
#include <flash.h>
#include <netdev.h>
@ -50,6 +53,11 @@ int checkboard(void)
}
#if defined(CONFIG_OF_BOARD_SETUP)
#ifdef CONFIG_FDT_FIXUP_PARTITIONS
struct node_info nodes[] = {
{ "fsl,ifc-nand", MTD_DEV_TYPE_NAND, },
};
#endif
void ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
@ -61,6 +69,9 @@ void ft_board_setup(void *blob, bd_t *bd)
size = getenv_bootm_size();
fdt_fixup_memory(blob, (u64)base, (u64)size);
#ifdef CONFIG_FDT_FIXUP_PARTITIONS
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
#endif
fdt_fixup_dr_usb(blob, bd);
}

12
board/freescale/bsc9132qds/bsc9132qds.c
View File

@ -21,6 +21,9 @@
#include <hwconfig.h>
#include <i2c.h>
#include <fsl_ddr_sdram.h>
#include <jffs2/load_kernel.h>
#include <mtd_node.h>
#include <flash.h>
#ifdef CONFIG_PCI
#include <pci.h>
@ -354,6 +357,12 @@ void fdt_del_node_compat(void *blob, const char *compatible)
}
#if defined(CONFIG_OF_BOARD_SETUP)
#ifdef CONFIG_FDT_FIXUP_PARTITIONS
struct node_info nodes[] = {
{ "cfi-flash", MTD_DEV_TYPE_NOR, },
{ "fsl,ifc-nand", MTD_DEV_TYPE_NAND, },
};
#endif
void ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
@ -369,6 +378,9 @@ void ft_board_setup(void *blob, bd_t *bd)
#endif
fdt_fixup_memory(blob, (u64)base, (u64)size);
#ifdef CONFIG_FDT_FIXUP_PARTITIONS
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
#endif
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 porbmsr = in_be32(&gur->porbmsr);

10
board/freescale/t104xrdb/t104x_pbi.cfg
View File

@ -1,4 +1,14 @@
#PBI commands
#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed
09250100 00000400
09250108 00002000
#Software Workaround for errata A-008007 to reset PVR register
09000010 0000000b
09000014 c0000000
09000018 81d00017
89020400 a1000000
091380c0 000f0000
89020400 00000000
#Initialize CPC1
09010000 00200400
09138000 00000000

1
board/freescale/t4rdb/Makefile
View File

@ -5,6 +5,7 @@
#
obj-$(CONFIG_T4240RDB) += t4240rdb.o
obj-y += cpld.o
obj-y += ddr.o
obj-y += eth.o
obj-$(CONFIG_PCI) += pci.o

136
board/freescale/t4rdb/cpld.c Normal file
View File

@ -0,0 +1,136 @@
/**
* Copyright 2014 Freescale Semiconductor
*
* Author: Chunhe Lan <Chunhe.Lan@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*
* This file provides support for the board-specific CPLD used on some Freescale
* reference boards.
*
* The following macros need to be defined:
*
* CONFIG_SYS_CPLD_BASE - The virtual address of the base of the
* CPLD register map
*
*/
#include <common.h>
#include <command.h>
#include <asm/io.h>
#include "cpld.h"
u8 cpld_read(unsigned int reg)
{
void *p = (void *)CONFIG_SYS_CPLD_BASE;
return in_8(p + reg);
}
void cpld_write(unsigned int reg, u8 value)
{
void *p = (void *)CONFIG_SYS_CPLD_BASE;
out_8(p + reg, value);
}
/**
* Set the boot bank to the alternate bank
*/
void cpld_set_altbank(void)
{
u8 val, curbank, altbank, override;
val = CPLD_READ(vbank);
curbank = val & CPLD_BANK_SEL_MASK;
switch (curbank) {
case CPLD_SELECT_BANK0:
altbank = CPLD_SELECT_BANK4;
CPLD_WRITE(vbank, altbank);
override = CPLD_READ(software_on);
CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN);
CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET);
break;
case CPLD_SELECT_BANK4:
altbank = CPLD_SELECT_BANK0;
CPLD_WRITE(vbank, altbank);
override = CPLD_READ(software_on);
CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN);
CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET);
break;
default:
printf("CPLD Altbank Fail: Invalid value!\n");
return;
}
}
/**
* Set the boot bank to the default bank
*/
void cpld_set_defbank(void)
{
u8 val;
val = CPLD_DEFAULT_BANK;
CPLD_WRITE(global_reset, val);
}
#ifdef DEBUG
static void cpld_dump_regs(void)
{
printf("chip_id1 = 0x%02x\n", CPLD_READ(chip_id1));
printf("chip_id2 = 0x%02x\n", CPLD_READ(chip_id2));
printf("sw_maj_ver = 0x%02x\n", CPLD_READ(sw_maj_ver));
printf("sw_min_ver = 0x%02x\n", CPLD_READ(sw_min_ver));
printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver));
printf("software_on = 0x%02x\n", CPLD_READ(software_on));
printf("cfg_rcw_src = 0x%02x\n", CPLD_READ(cfg_rcw_src));
printf("res0 = 0x%02x\n", CPLD_READ(res0));
printf("vbank = 0x%02x\n", CPLD_READ(vbank));
printf("sw1_sysclk = 0x%02x\n", CPLD_READ(sw1_sysclk));
printf("sw2_status = 0x%02x\n", CPLD_READ(sw2_status));
printf("sw3_status = 0x%02x\n", CPLD_READ(sw3_status));
printf("sw4_status = 0x%02x\n", CPLD_READ(sw4_status));
printf("sys_reset = 0x%02x\n", CPLD_READ(sys_reset));
printf("global_reset = 0x%02x\n", CPLD_READ(global_reset));
printf("res1 = 0x%02x\n", CPLD_READ(res1));
putc('\n');
}
#endif
#ifndef CONFIG_SPL_BUILD
int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int rc = 0;
if (argc <= 1)
return cmd_usage(cmdtp);
if (strcmp(argv[1], "reset") == 0) {
if (strcmp(argv[2], "altbank") == 0)
cpld_set_altbank();
else
cpld_set_defbank();
#ifdef DEBUG
} else if (strcmp(argv[1], "dump") == 0) {
cpld_dump_regs();
#endif
} else
rc = cmd_usage(cmdtp);
return rc;
}
U_BOOT_CMD(
cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
"Reset the board or alternate bank",
"reset - reset to default bank\n"
"cpld reset altbank - reset to alternate bank\n"
#ifdef DEBUG
"cpld dump - display the CPLD registers\n"
#endif
);
#endif

49
board/freescale/t4rdb/cpld.h Normal file
View File

@ -0,0 +1,49 @@
/**
* Copyright 2014 Freescale Semiconductor
*
* Author: Chunhe Lan <Chunhe.Lan@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*
* This file provides support for the ngPIXIS, a board-specific FPGA used on
* some Freescale reference boards.
*/
/*
* CPLD register set. Feel free to add board-specific #ifdefs where necessary.
*/
struct cpld_data {
u8 chip_id1; /* 0x00 - CPLD Chip ID1 Register */
u8 chip_id2; /* 0x01 - CPLD Chip ID2 Register */
u8 sw_maj_ver; /* 0x02 - CPLD Code Major Version Register */
u8 sw_min_ver; /* 0x03 - CPLD Code Minor Version Register */
u8 hw_ver; /* 0x04 - PCBA Version Register */
u8 software_on; /* 0x05 - Override Physical Switch Enable Register */
u8 cfg_rcw_src; /* 0x06 - RCW Source Location Control Register */
u8 res0; /* 0x07 - not used */
u8 vbank; /* 0x08 - Flash Bank Selection Control Register */
u8 sw1_sysclk; /* 0x09 - SW1 Status Read Back Register */
u8 sw2_status; /* 0x0a - SW2 Status Read Back Register */
u8 sw3_status; /* 0x0b - SW3 Status Read Back Register */
u8 sw4_status; /* 0x0c - SW4 Status Read Back Register */
u8 sys_reset; /* 0x0d - Reset System With Reserving Registers Value*/
u8 global_reset;/* 0x0e - Reset System With Default Registers Value */
u8 res1; /* 0x0f - not used */
};
#define CPLD_BANK_SEL_MASK 0x07
#define CPLD_BANK_SEL_EN 0x04
#define CPLD_SYSTEM_RESET 0x01
#define CPLD_SELECT_BANK0 0x00
#define CPLD_SELECT_BANK4 0x04
#define CPLD_DEFAULT_BANK 0x01
/* Pointer to the CPLD register set */
u8 cpld_read(unsigned int reg);
void cpld_write(unsigned int reg, u8 value);
#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
#define CPLD_WRITE(reg, value) \
cpld_write(offsetof(struct cpld_data, reg), value)

3
board/freescale/t4rdb/law.c
View File

@ -16,6 +16,9 @@ struct law_entry law_table[] = {
#ifdef CONFIG_SYS_QMAN_MEM_PHYS
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
#endif
#ifdef CONFIG_SYS_CPLD_BASE_PHYS
SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
/* Limit DCSR to 32M to access NPC Trace Buffer */
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),

12
board/freescale/t4rdb/t4240rdb.c
View File

@ -20,14 +20,26 @@
#include <fm_eth.h>
#include "t4rdb.h"
#include "cpld.h"
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
struct cpu_type *cpu = gd->arch.cpu;
u8 sw;
printf("Board: %sRDB, ", cpu->name);
printf("Board rev: 0x%02x CPLD ver: 0x%02x%02x, ",
CPLD_READ(hw_ver), CPLD_READ(sw_maj_ver), CPLD_READ(sw_min_ver));
sw = CPLD_READ(vbank);
sw = sw & CPLD_BANK_SEL_MASK;
if (sw <= 7)
printf("vBank: %d\n", sw);
else
printf("Unsupported Bank=%x\n", sw);
puts("SERDES Reference Clocks:\n");
printf(" SERDES1=100MHz SERDES2=156.25MHz\n"

5
board/freescale/t4rdb/tlb.c
View File

@ -106,6 +106,11 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 16, BOOKE_PAGESZ_64K, 1),
#endif
#ifdef CONFIG_SYS_CPLD_BASE
SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 17, BOOKE_PAGESZ_4K, 1),
#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

12
drivers/net/fm/memac.c
View File

@ -37,7 +37,8 @@ static void memac_enable_mac(struct fsl_enet_mac *mac)
{
struct memac *regs = mac->base;
setbits_be32(&regs->command_config, MEMAC_CMD_CFG_RXTX_EN);
setbits_be32(&regs->command_config,
MEMAC_CMD_CFG_RXTX_EN | MEMAC_CMD_CFG_NO_LEN_CHK);
}
static void memac_disable_mac(struct fsl_enet_mac *mac)
@ -93,11 +94,16 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac,
if_mode &= ~IF_MODE_MASK;
if_mode |= (IF_MODE_GMII);
break;
case PHY_INTERFACE_MODE_XGMII:
if_mode &= ~IF_MODE_MASK;
if_mode |= IF_MODE_XGMII;
break;
default:
break;
}
/* Enable automatic speed selection */
if_mode |= IF_MODE_EN_AUTO;
/* Enable automatic speed selection for Non-XGMII */
if (type != PHY_INTERFACE_MODE_XGMII)
if_mode |= IF_MODE_EN_AUTO;
if (type == PHY_INTERFACE_MODE_RGMII) {
if_mode &= ~IF_MODE_EN_AUTO;

7
drivers/net/fm/memac_phy.c
View File

@ -71,6 +71,8 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
u32 c45 = 1;
if (dev_addr == MDIO_DEVAD_NONE) {
if (!strcmp(bus->name, DEFAULT_FM_TGEC_MDIO_NAME))
return 0xffff;
c45 = 0; /* clause 22 */
dev_addr = regnum & 0x1f;
clrbits_be32(&regs->mdio_stat, MDIO_STAT_ENC);
@ -137,9 +139,12 @@ int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info)
* is zero, so MDIO clock is disabled.
* So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to
* be properly initialized.
* NEG bit default should be '1' as per FMAN-v3 RM, but on platform
* like T2080QDS, this bit default is '0', which leads to MDIO failure
* on XAUI PHY, so set this bit definitely.
*/
setbits_be32(&((struct memac_mdio_controller *)info->regs)->mdio_stat,
MDIO_STAT_CLKDIV(258));
MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG);
return mdio_register(bus);
}

17
include/configs/BSC9131RDB.h
View File

@ -399,6 +399,23 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_HAS_FSL_DR_USB
#endif
/*
* Dynamic MTD Partition support with mtdparts
*/
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT "nand0=ff800000.flash,"
#define MTDPARTS_DEFAULT "mtdparts=ff800000.flash:1m(uboot)," \
"8m(kernel),512k(dtb),-(fs)"
/*
* Override partitions in device tree using info
* in "mtdparts" environment variable
*/
#ifdef CONFIG_CMD_MTDPARTS
#define CONFIG_FDT_FIXUP_PARTITIONS
#endif
/*
* Environment Configuration
*/

21
include/configs/BSC9132QDS.h
View File

@ -636,6 +636,27 @@ combinations. this should be removed later
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#endif
/*
* Dynamic MTD Partition support with mtdparts
*/
#ifndef CONFIG_SYS_NO_FLASH
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_CMD_MTDPARTS
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT "nor0=88000000.nor,nand0=ff800000.flash,"
#define MTDPARTS_DEFAULT "mtdparts=88000000.nor:256k(dtb),7m(kernel)," \
"55m(fs),1m(uboot);ff800000.flash:1m(uboot)," \
"8m(kernel),512k(dtb),-(fs)"
#endif
/*
* Override partitions in device tree using info
* in "mtdparts" environment variable
*/
#ifdef CONFIG_CMD_MTDPARTS
#define CONFIG_FDT_FIXUP_PARTITIONS
#endif
/*
* Environment Configuration
*/

19
include/configs/P1022DS.h
View File

@ -615,6 +615,25 @@
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
#endif
/*
* Dynamic MTD Partition support with mtdparts
*/
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_CMD_MTDPARTS
#define CONFIG_FLASH_CFI_MTD
#ifdef CONFIG_PHYS_64BIT
#define MTDIDS_DEFAULT "nor0=fe8000000.nor"
#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \
"14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \
"512k(dtb),768k(u-boot)"
#else
#define MTDIDS_DEFAULT "nor0=e8000000.nor"
#define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \
"14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \
"512k(dtb),768k(u-boot)"
#endif
/*
* Environment
*/

23
include/configs/T4240RDB.h
View File

@ -514,6 +514,29 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
/* CPLD on IFC */
#define CONFIG_SYS_CPLD_BASE 0xffdf0000
#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
#define CONFIG_SYS_CSPR3_EXT (0xf)
#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
#define CONFIG_SYS_CSOR3 0x0
/* CPLD Timing parameters for IFC CS3 */
#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
FTIM0_GPCM_TEADC(0x0e) | \
FTIM0_GPCM_TEAHC(0x0e))
#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
FTIM1_GPCM_TRAD(0x1f))
#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
FTIM2_GPCM_TCH(0x0) | \
FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS3_FTIM3 0x0
#if defined(CONFIG_RAMBOOT_PBL)
#define CONFIG_SYS_RAMBOOT
#endif

3
include/configs/km/km83xx-common.h
View File

@ -8,6 +8,9 @@
#ifndef __CONFIG_KM83XX_H
#define __CONFIG_KM83XX_H
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO
/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
#include "km-powerpc.h"

7
include/configs/km/kmp204x-common.h
View File

@ -11,7 +11,7 @@
#define CONFIG_PHYS_64BIT
#define CONFIG_PPC_P2041
#define CONFIG_SYS_TEXT_BASE 0xfff80000
#define CONFIG_SYS_TEXT_BASE 0xfff40000
#define CONFIG_KM_DEF_NETDEV "netdev=eth0\0"
@ -21,6 +21,9 @@
#define CONFIG_NAND_ECC_BCH
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO
/* common KM defines */
#include "keymile-common.h"
@ -235,7 +238,7 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
/* Serial Port - controlled on board with jumper J8

3
include/configs/km82xx.h
View File

@ -29,6 +29,9 @@
#error ("Board unsupported")
#endif
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0xFE000000
/* include common defines/options for all Keymile boards */

44
include/configs/p1_p2_rdb_pc.h
View File

@ -80,6 +80,16 @@
#define __SW_BOOT_NAND 0x44
#define __SW_BOOT_PCIE 0x74
#define CONFIG_SYS_L2_SIZE (256 << 10)
/*
* Dynamic MTD Partition support with mtdparts
*/
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_CMD_MTDPARTS
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT "nor0=ec000000.nor"
#define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \
"57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
#endif
#if defined(CONFIG_P1021RDB)
@ -98,6 +108,24 @@
#define __SW_BOOT_NAND 0xec
#define __SW_BOOT_PCIE 0x6c
#define CONFIG_SYS_L2_SIZE (256 << 10)
/*
* Dynamic MTD Partition support with mtdparts
*/
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_CMD_MTDPARTS
#define CONFIG_FLASH_CFI_MTD
#ifdef CONFIG_PHYS_64BIT
#define MTDIDS_DEFAULT "nor0=fef000000.nor"
#define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \
"256k(dtb),4608k(kernel),9728k(fs)," \
"256k(qe-ucode-firmware),1280k(u-boot)"
#else
#define MTDIDS_DEFAULT "nor0=ef000000.nor"
#define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \
"256k(dtb),4608k(kernel),9728k(fs)," \
"256k(qe-ucode-firmware),1280k(u-boot)"
#endif
#endif
#if defined(CONFIG_P1024RDB)
@ -145,6 +173,22 @@
#define __SW_BOOT_NAND 0xe8
#define __SW_BOOT_PCIE 0xa8
#define CONFIG_SYS_L2_SIZE (512 << 10)
/*
* Dynamic MTD Partition support with mtdparts
*/
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_CMD_MTDPARTS
#define CONFIG_FLASH_CFI_MTD
#ifdef CONFIG_PHYS_64BIT
#define MTDIDS_DEFAULT "nor0=fef000000.nor"
#define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \
"256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
#else
#define MTDIDS_DEFAULT "nor0=ef000000.nor"
#define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \
"256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
#endif
#endif
#ifdef CONFIG_SDCARD

12
include/configs/p1_twr.h
View File

@ -388,6 +388,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#endif /* CONFIG_UEC_ETH5 */
#endif /* CONFIG_TWR-P1025 */
/*
* Dynamic MTD Partition support with mtdparts
*/
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_CMD_MTDPARTS
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT "nor0=ec000000.nor"
#define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:256k(vsc7385-firmware)," \
"256k(dtb),5632k(kernel),57856k(fs)," \
"256k(qe-ucode-firmware),1280k(u-boot)"
/*
* Environment
*/

2
include/configs/sbc8548.h
View File

@ -13,6 +13,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_SYS_GENERIC_BOARD
/*
* Top level Makefile configuration choices
*/