mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-10-01 00:50:43 +09:00
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
This commit is contained in:
commit
1f7bab0832
@ -463,6 +463,6 @@ unsigned int get_cpu_board_revision(void)
|
|||||||
if ((be.major == 0xff) && (be.minor == 0xff))
|
if ((be.major == 0xff) && (be.minor == 0xff))
|
||||||
return MPC85XX_CPU_BOARD_REV(0, 0);
|
return MPC85XX_CPU_BOARD_REV(0, 0);
|
||||||
|
|
||||||
return MPC85XX_CPU_BOARD_REV(e.major, e.minor);
|
return MPC85XX_CPU_BOARD_REV(be.major, be.minor);
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
@ -85,7 +85,8 @@ int checkcpu (void)
|
|||||||
struct cpu_type *cpu;
|
struct cpu_type *cpu;
|
||||||
#ifdef CONFIG_DDR_CLK_FREQ
|
#ifdef CONFIG_DDR_CLK_FREQ
|
||||||
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||||
u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
|
u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
|
||||||
|
>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
|
||||||
#else
|
#else
|
||||||
u32 ddr_ratio = 0;
|
u32 ddr_ratio = 0;
|
||||||
#endif
|
#endif
|
||||||
|
@ -152,7 +152,6 @@ static inline void ft_fixup_l2cache(void *blob)
|
|||||||
}
|
}
|
||||||
fdt_setprop(blob, off, "cache-unified", NULL, 0);
|
fdt_setprop(blob, off, "cache-unified", NULL, 0);
|
||||||
fdt_setprop_cell(blob, off, "cache-block-size", line_size);
|
fdt_setprop_cell(blob, off, "cache-block-size", line_size);
|
||||||
fdt_setprop_cell(blob, off, "cache-line-size", line_size);
|
|
||||||
fdt_setprop_cell(blob, off, "cache-size", size);
|
fdt_setprop_cell(blob, off, "cache-size", size);
|
||||||
fdt_setprop_cell(blob, off, "cache-sets", num_sets);
|
fdt_setprop_cell(blob, off, "cache-sets", num_sets);
|
||||||
fdt_setprop_cell(blob, off, "cache-level", 2);
|
fdt_setprop_cell(blob, off, "cache-level", 2);
|
||||||
@ -181,7 +180,6 @@ static inline void ft_fixup_cache(void *blob)
|
|||||||
dnum_sets = dsize / (dline_size * dnum_ways);
|
dnum_sets = dsize / (dline_size * dnum_ways);
|
||||||
|
|
||||||
fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
|
fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
|
||||||
fdt_setprop_cell(blob, off, "d-cache-line-size", dline_size);
|
|
||||||
fdt_setprop_cell(blob, off, "d-cache-size", dsize);
|
fdt_setprop_cell(blob, off, "d-cache-size", dsize);
|
||||||
fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
|
fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
|
||||||
|
|
||||||
@ -192,7 +190,6 @@ static inline void ft_fixup_cache(void *blob)
|
|||||||
inum_sets = isize / (iline_size * inum_ways);
|
inum_sets = isize / (iline_size * inum_ways);
|
||||||
|
|
||||||
fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
|
fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
|
||||||
fdt_setprop_cell(blob, off, "i-cache-line-size", iline_size);
|
|
||||||
fdt_setprop_cell(blob, off, "i-cache-size", isize);
|
fdt_setprop_cell(blob, off, "i-cache-size", isize);
|
||||||
fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
|
fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
|
||||||
|
|
||||||
|
@ -54,7 +54,8 @@ void get_sys_info (sys_info_t * sysInfo)
|
|||||||
|
|
||||||
#ifdef CONFIG_DDR_CLK_FREQ
|
#ifdef CONFIG_DDR_CLK_FREQ
|
||||||
{
|
{
|
||||||
u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
|
u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
|
||||||
|
>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
|
||||||
if (ddr_ratio != 0x7)
|
if (ddr_ratio != 0x7)
|
||||||
sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
|
sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
|
||||||
}
|
}
|
||||||
@ -101,9 +102,9 @@ int get_clocks (void)
|
|||||||
* PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
|
* PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
|
||||||
*/
|
*/
|
||||||
if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
|
if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
|
||||||
gd->i2c1_clk = sys_info.freqSystemBus / 3;
|
|
||||||
else
|
|
||||||
gd->i2c1_clk = sys_info.freqSystemBus / 2;
|
gd->i2c1_clk = sys_info.freqSystemBus / 2;
|
||||||
|
else
|
||||||
|
gd->i2c1_clk = sys_info.freqSystemBus / 3;
|
||||||
#else
|
#else
|
||||||
/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
|
/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
|
||||||
gd->i2c1_clk = sys_info.freqSystemBus / 2;
|
gd->i2c1_clk = sys_info.freqSystemBus / 2;
|
||||||
|
@ -1552,6 +1552,13 @@ typedef struct par_io {
|
|||||||
*/
|
*/
|
||||||
typedef struct ccsr_gur {
|
typedef struct ccsr_gur {
|
||||||
uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
|
uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
|
||||||
|
#ifdef CONFIG_MPC8536
|
||||||
|
#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
|
||||||
|
#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
|
||||||
|
#else
|
||||||
|
#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
|
||||||
|
#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
|
||||||
|
#endif
|
||||||
uint porbmsr; /* 0xe0004 - POR boot mode status register */
|
uint porbmsr; /* 0xe0004 - POR boot mode status register */
|
||||||
#define MPC85xx_PORBMSR_HA 0x00070000
|
#define MPC85xx_PORBMSR_HA 0x00070000
|
||||||
uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
|
uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
|
||||||
|
@ -59,7 +59,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
|
|||||||
extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||||
#endif
|
#endif
|
||||||
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
|
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
|
||||||
/* #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /\* ddrclk for MPC85xx *\/ FIXME-8536*/
|
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0)
|
||||||
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
|
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
|
||||||
#define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq
|
#define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq
|
||||||
from ICS307 instead of switches */
|
from ICS307 instead of switches */
|
||||||
@ -303,7 +303,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
|||||||
*/
|
*/
|
||||||
#define CONFIG_ID_EEPROM
|
#define CONFIG_ID_EEPROM
|
||||||
#ifdef CONFIG_ID_EEPROM
|
#ifdef CONFIG_ID_EEPROM
|
||||||
#define CONFIG_ID_EEPROM
|
|
||||||
#define CFG_I2C_EEPROM_NXID
|
#define CFG_I2C_EEPROM_NXID
|
||||||
#endif
|
#endif
|
||||||
#define CFG_I2C_EEPROM_ADDR 0x57
|
#define CFG_I2C_EEPROM_ADDR 0x57
|
||||||
|
@ -108,6 +108,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
|||||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
|
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
|
||||||
|
|
||||||
/* I2C addresses of SPD EEPROMs */
|
/* I2C addresses of SPD EEPROMs */
|
||||||
|
#define CFG_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */
|
||||||
#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
|
#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
|
||||||
#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
|
#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
|
||||||
|
|
||||||
@ -293,11 +294,25 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
|||||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||||
|
#define CONFIG_I2C_MULTI_BUS
|
||||||
|
#define CONFIG_I2C_CMD_TREE
|
||||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
|
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||||
#define CFG_I2C_EEPROM_ADDR 0x57
|
#define CFG_I2C_EEPROM_ADDR 0x57
|
||||||
#define CFG_I2C_SLAVE 0x7F
|
#define CFG_I2C_SLAVE 0x7F
|
||||||
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
|
#define CFG_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */
|
||||||
#define CFG_I2C_OFFSET 0x3100
|
#define CFG_I2C_OFFSET 0x3000
|
||||||
|
#define CFG_I2C2_OFFSET 0x3100
|
||||||
|
|
||||||
|
/*
|
||||||
|
* I2C2 EEPROM
|
||||||
|
*/
|
||||||
|
#define CONFIG_ID_EEPROM
|
||||||
|
#ifdef CONFIG_ID_EEPROM
|
||||||
|
#define CFG_I2C_EEPROM_NXID
|
||||||
|
#endif
|
||||||
|
#define CFG_I2C_EEPROM_ADDR 0x57
|
||||||
|
#define CFG_I2C_EEPROM_ADDR_LEN 1
|
||||||
|
#define CFG_EEPROM_BUS_NUM 1
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* General PCI
|
* General PCI
|
||||||
|
Loading…
Reference in New Issue
Block a user