mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-28 07:30:26 +09:00
UniPhier SoC updates for v2020.04 (3rd)
- Enable ADMA and HS400 for the eMMC driver on 64-bit SoCs - Add some convenient environment variables to handle SD card - Sanitize the NAND controller reset sequence and its WP handling - Sync DT with Linux -----BEGIN PGP SIGNATURE----- iQJSBAABCgA8FiEEbmPs18K1szRHjPqEPYsBB53g2wYFAl5Z9MIeHHlhbWFkYS5t YXNhaGlyb0Bzb2Npb25leHQuY29tAAoJED2LAQed4NsGAtMP/jQEdSlUm/Jb/N0G JorNMgv9XbzLARrVv4steQL+vgXcCtzLNmMozhPp+w2w4xIC/uvPX22GdGbcDV4g tvXfTb5JPRlrxRgD+cStBjbBt8tB6D4Ctz3jlZcCzivPGbLunvXUKuuLMqUa1vp5 XCUOWHVL/R+vIG8ag30uytZK4NNFdzioSOTBwsn67QkoA3TS/FweO9EeeiYqE822 YQMukmnzSg4kDbiCZR0xvo2SdwNlZqA15xOkocPfSsslmnhGEgDsWE2z613YpchQ 24lJGe1Sr7fJ4JlqH6TBYIDyLNmltBLWpUqDCXOtFIeRkM3EsbKb/PiCDFH2hBLV GVbvOFE9n9MyxpTzNxUliqFvLa3yxQfgG4QtBbStQzBRoHb9IH5IemyQCwMOpawV 2Rhg8yyMzKQnLwv+G7yYd9drbO0RQeBPQl2XVpTvXJ58wARsFWNe/cJn3w0kRSEQ n1U24Hc/D+thKp9wYeRC2ys9C09Eb+POn3c+NKl+1JCmk+MBfTamhy49i0dWQUrP 98+UfKwl7EqEhicG34XuJtH+QYzCOhBwKLFacomqPVVn5I569mxsdFuMRsLlcCdM M4tzw/FSMnPy9q5q5hiE2QKPMTuPwSdVxUzmPzJn8nzgQCAtQC+iRHiaQ6927c// XMWdvxycmdHpWMPUeJZczDVdqSea =h4lQ -----END PGP SIGNATURE----- Merge tag 'uniphier-v2020.04-3' of https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier UniPhier SoC updates for v2020.04 (3rd) - Enable ADMA and HS400 for the eMMC driver on 64-bit SoCs - Add some convenient environment variables to handle SD card - Sanitize the NAND controller reset sequence and its WP handling - Sync DT with Linux
This commit is contained in:
Tom Rini
commit
1e85aaf372
@ -132,7 +132,7 @@
|
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};
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eeprom@50 {
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||||
compatible = "st,24c64", "atmel,24c64", "i2c-eeprom";
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compatible = "st,24c64", "atmel,24c64";
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reg = <0x50>;
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pagesize = <32>;
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||||
};
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@ -433,7 +433,7 @@
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};
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};
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emmc: sdhc@5a000000 {
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emmc: mmc@5a000000 {
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compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
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reg = <0x5a000000 0x400>;
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interrupts = <0 78 4>;
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@ -566,7 +566,7 @@
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};
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};
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aidet: aidet@5fc20000 {
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aidet: interrupt-controller@5fc20000 {
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compatible = "socionext,uniphier-ld11-aidet";
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reg = <0x5fc20000 0x200>;
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interrupt-controller;
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@ -621,7 +621,7 @@
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};
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};
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nand: nand@68000000 {
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nand: nand-controller@68000000 {
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compatible = "socionext,uniphier-denali-nand-v5b";
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status = "disabled";
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reg-names = "nand_data", "denali_reg";
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@ -631,7 +631,8 @@
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pinctrl-0 = <&pinctrl_nand>;
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clock-names = "nand", "nand_x", "ecc";
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clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
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resets = <&sys_rst 2>;
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reset-names = "nand", "reg";
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resets = <&sys_rst 2>, <&sys_rst 2>;
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};
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};
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};
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@ -559,7 +559,7 @@
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};
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};
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emmc: sdhc@5a000000 {
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emmc: mmc@5a000000 {
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compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
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reg = <0x5a000000 0x400>;
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interrupts = <0 78 4>;
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@ -578,7 +578,7 @@
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cdns,phy-dll-delay-sdclk-hsmmc = <21>;
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};
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sd: sdhc@5a400000 {
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sd: mmc@5a400000 {
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compatible = "socionext,uniphier-sd-v3.1.1";
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status = "disabled";
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reg = <0x5a400000 0x800>;
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@ -664,7 +664,7 @@
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};
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};
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aidet: aidet@5fc20000 {
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aidet: interrupt-controller@5fc20000 {
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compatible = "socionext,uniphier-ld20-aidet";
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reg = <0x5fc20000 0x200>;
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interrupt-controller;
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@ -944,7 +944,7 @@
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socionext,syscon = <&soc_glue>;
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};
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nand: nand@68000000 {
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nand: nand-controller@68000000 {
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compatible = "socionext,uniphier-denali-nand-v5b";
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status = "disabled";
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reg-names = "nand_data", "denali_reg";
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@ -954,7 +954,8 @@
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pinctrl-0 = <&pinctrl_nand>;
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clock-names = "nand", "nand_x", "ecc";
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clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
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resets = <&sys_rst 2>;
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reset-names = "nand", "reg";
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resets = <&sys_rst 2>, <&sys_rst 2>;
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};
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};
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};
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@ -51,7 +51,7 @@
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ranges;
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interrupt-parent = <&intc>;
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l2: l2-cache@500c0000 {
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l2: cache-controller@500c0000 {
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compatible = "socionext,uniphier-system-cache";
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reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
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<0x506c0000 0x400>;
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@ -245,7 +245,7 @@
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#dma-cells = <1>;
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};
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sd: sdhc@5a400000 {
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sd: mmc@5a400000 {
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compatible = "socionext,uniphier-sd-v2.91";
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status = "disabled";
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reg = <0x5a400000 0x200>;
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@ -265,7 +265,7 @@
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sd-uhs-sdr50;
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};
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emmc: sdhc@5a500000 {
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emmc: mmc@5a500000 {
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compatible = "socionext,uniphier-sd-v2.91";
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status = "disabled";
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reg = <0x5a500000 0x200>;
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@ -375,7 +375,7 @@
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interrupt-controller;
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};
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aidet: aidet@61830000 {
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aidet: interrupt-controller@61830000 {
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compatible = "socionext,uniphier-ld4-aidet";
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reg = <0x61830000 0x200>;
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interrupt-controller;
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@ -398,7 +398,7 @@
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};
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};
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nand: nand@68000000 {
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nand: nand-controller@68000000 {
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compatible = "socionext,uniphier-denali-nand-v5a";
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status = "disabled";
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reg-names = "nand_data", "denali_reg";
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@ -408,7 +408,8 @@
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pinctrl-0 = <&pinctrl_nand2cs>;
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clock-names = "nand", "nand_x", "ecc";
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clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
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resets = <&sys_rst 2>;
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reset-names = "nand", "reg";
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resets = <&sys_rst 2>, <&sys_rst 2>;
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};
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};
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};
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@ -50,10 +50,9 @@
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status = "okay";
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eeprom@54 {
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compatible = "st,24c64", "atmel,24c64", "i2c-eeprom";
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compatible = "st,24c64", "atmel,24c64";
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reg = <0x54>;
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pagesize = <32>;
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u-boot,i2c-offset-len = <2>;
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};
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};
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@ -45,10 +45,9 @@
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status = "okay";
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eeprom@54 {
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compatible = "st,24c64", "atmel,24c64", "i2c-eeprom";
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compatible = "st,24c64", "atmel,24c64";
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reg = <0x54>;
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pagesize = <32>;
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u-boot,i2c-offset-len = <2>;
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};
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};
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@ -59,7 +59,7 @@
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ranges;
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interrupt-parent = <&intc>;
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l2: l2-cache@500c0000 {
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l2: cache-controller@500c0000 {
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compatible = "socionext,uniphier-system-cache";
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reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
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<0x506c0000 0x400>;
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@ -279,7 +279,7 @@
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#dma-cells = <1>;
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};
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sd: sdhc@5a400000 {
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sd: mmc@5a400000 {
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compatible = "socionext,uniphier-sd-v2.91";
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status = "disabled";
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reg = <0x5a400000 0x200>;
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@ -299,7 +299,7 @@
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sd-uhs-sdr50;
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};
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emmc: sdhc@5a500000 {
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emmc: mmc@5a500000 {
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compatible = "socionext,uniphier-sd-v2.91";
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status = "disabled";
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reg = <0x5a500000 0x200>;
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@ -317,7 +317,7 @@
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non-removable;
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};
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sd1: sdhc@5a600000 {
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sd1: mmc@5a600000 {
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compatible = "socionext,uniphier-sd-v2.91";
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status = "disabled";
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reg = <0x5a600000 0x200>;
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@ -426,7 +426,7 @@
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};
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};
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aidet: aidet@5fc20000 {
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aidet: interrupt-controller@5fc20000 {
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compatible = "socionext,uniphier-pro4-aidet";
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reg = <0x5fc20000 0x200>;
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interrupt-controller;
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@ -626,7 +626,7 @@
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};
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};
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nand: nand@68000000 {
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nand: nand-controller@68000000 {
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compatible = "socionext,uniphier-denali-nand-v5a";
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status = "disabled";
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reg-names = "nand_data", "denali_reg";
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@ -636,7 +636,8 @@
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pinctrl-0 = <&pinctrl_nand>;
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clock-names = "nand", "nand_x", "ecc";
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clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
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resets = <&sys_rst 2>;
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reset-names = "nand", "reg";
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resets = <&sys_rst 2>, <&sys_rst 2>;
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};
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};
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};
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@ -131,7 +131,7 @@
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ranges;
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interrupt-parent = <&intc>;
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l2: l2-cache@500c0000 {
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l2: cache-controller@500c0000 {
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compatible = "socionext,uniphier-system-cache";
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reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
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<0x506c0000 0x400>;
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@ -144,7 +144,7 @@
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next-level-cache = <&l3>;
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};
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l3: l3-cache@500c8000 {
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l3: cache-controller@500c8000 {
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compatible = "socionext,uniphier-system-cache";
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reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
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<0x506c8000 0x400>;
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@ -408,7 +408,7 @@
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};
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};
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aidet: aidet@5fc20000 {
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aidet: interrupt-controller@5fc20000 {
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compatible = "socionext,uniphier-pro5-aidet";
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reg = <0x5fc20000 0x200>;
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interrupt-controller;
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@ -489,7 +489,7 @@
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};
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};
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nand: nand@68000000 {
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nand: nand-controller@68000000 {
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compatible = "socionext,uniphier-denali-nand-v5b";
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status = "disabled";
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reg-names = "nand_data", "denali_reg";
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@ -499,10 +499,11 @@
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pinctrl-0 = <&pinctrl_nand2cs>;
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clock-names = "nand", "nand_x", "ecc";
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clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
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resets = <&sys_rst 2>;
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reset-names = "nand", "reg";
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resets = <&sys_rst 2>, <&sys_rst 2>;
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};
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emmc: sdhc@68400000 {
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emmc: mmc@68400000 {
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compatible = "socionext,uniphier-sd-v3.1";
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status = "disabled";
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reg = <0x68400000 0x800>;
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||||
@ -518,7 +519,7 @@
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non-removable;
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};
|
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sd: sdhc@68800000 {
|
||||
sd: mmc@68800000 {
|
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compatible = "socionext,uniphier-sd-v3.1";
|
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status = "disabled";
|
||||
reg = <0x68800000 0x800>;
|
||||
|
||||
@ -48,10 +48,9 @@
|
||||
status = "okay";
|
||||
|
||||
eeprom@54 {
|
||||
compatible = "st,24c64", "atmel,24c64", "i2c-eeprom";
|
||||
compatible = "st,24c64", "atmel,24c64";
|
||||
reg = <0x54>;
|
||||
pagesize = <32>;
|
||||
u-boot,i2c-offset-len = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -157,7 +157,7 @@
|
||||
ranges;
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
l2: l2-cache@500c0000 {
|
||||
l2: cache-controller@500c0000 {
|
||||
compatible = "socionext,uniphier-system-cache";
|
||||
reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
|
||||
<0x506c0000 0x400>;
|
||||
@ -446,7 +446,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
emmc: sdhc@5a000000 {
|
||||
emmc: mmc@5a000000 {
|
||||
compatible = "socionext,uniphier-sd-v3.1.1";
|
||||
status = "disabled";
|
||||
reg = <0x5a000000 0x800>;
|
||||
@ -462,7 +462,7 @@
|
||||
non-removable;
|
||||
};
|
||||
|
||||
sd: sdhc@5a400000 {
|
||||
sd: mmc@5a400000 {
|
||||
compatible = "socionext,uniphier-sd-v3.1.1";
|
||||
status = "disabled";
|
||||
reg = <0x5a400000 0x800>;
|
||||
@ -508,7 +508,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
aidet: aidet@5fc20000 {
|
||||
aidet: interrupt-controller@5fc20000 {
|
||||
compatible = "socionext,uniphier-pxs2-aidet";
|
||||
reg = <0x5fc20000 0x200>;
|
||||
interrupt-controller;
|
||||
@ -799,7 +799,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
nand: nand@68000000 {
|
||||
nand: nand-controller@68000000 {
|
||||
compatible = "socionext,uniphier-denali-nand-v5b";
|
||||
status = "disabled";
|
||||
reg-names = "nand_data", "denali_reg";
|
||||
@ -809,7 +809,8 @@
|
||||
pinctrl-0 = <&pinctrl_nand2cs>;
|
||||
clock-names = "nand", "nand_x", "ecc";
|
||||
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
|
||||
resets = <&sys_rst 2>;
|
||||
reset-names = "nand", "reg";
|
||||
resets = <&sys_rst 2>, <&sys_rst 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -353,7 +353,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
emmc: sdhc@5a000000 {
|
||||
emmc: mmc@5a000000 {
|
||||
compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
|
||||
reg = <0x5a000000 0x400>;
|
||||
interrupts = <0 78 4>;
|
||||
@ -372,7 +372,7 @@
|
||||
cdns,phy-dll-delay-sdclk-hsmmc = <21>;
|
||||
};
|
||||
|
||||
sd: sdhc@5a400000 {
|
||||
sd: mmc@5a400000 {
|
||||
compatible = "socionext,uniphier-sd-v3.1.1";
|
||||
status = "disabled";
|
||||
reg = <0x5a400000 0x800>;
|
||||
@ -462,7 +462,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
aidet: aidet@5fc20000 {
|
||||
aidet: interrupt-controller@5fc20000 {
|
||||
compatible = "socionext,uniphier-pxs3-aidet";
|
||||
reg = <0x5fc20000 0x200>;
|
||||
interrupt-controller;
|
||||
@ -821,7 +821,7 @@
|
||||
socionext,syscon = <&soc_glue>;
|
||||
};
|
||||
|
||||
nand: nand@68000000 {
|
||||
nand: nand-controller@68000000 {
|
||||
compatible = "socionext,uniphier-denali-nand-v5b";
|
||||
status = "disabled";
|
||||
reg-names = "nand_data", "denali_reg";
|
||||
@ -831,7 +831,8 @@
|
||||
pinctrl-0 = <&pinctrl_nand>;
|
||||
clock-names = "nand", "nand_x", "ecc";
|
||||
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
|
||||
resets = <&sys_rst 2>;
|
||||
reset-names = "nand", "reg";
|
||||
resets = <&sys_rst 2>, <&sys_rst 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -7,9 +7,8 @@
|
||||
|
||||
&i2c0 {
|
||||
eeprom@50 {
|
||||
compatible = "microchip,24lc128", "i2c-eeprom";
|
||||
compatible = "microchip,24lc128", "atmel,24c128";
|
||||
reg = <0x50>;
|
||||
pagesize = <64>;
|
||||
u-boot,i2c-offset-len = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -51,7 +51,7 @@
|
||||
ranges;
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
l2: l2-cache@500c0000 {
|
||||
l2: cache-controller@500c0000 {
|
||||
compatible = "socionext,uniphier-system-cache";
|
||||
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
|
||||
<0x506c0000 0x400>;
|
||||
@ -249,7 +249,7 @@
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
sd: sdhc@5a400000 {
|
||||
sd: mmc@5a400000 {
|
||||
compatible = "socionext,uniphier-sd-v2.91";
|
||||
status = "disabled";
|
||||
reg = <0x5a400000 0x200>;
|
||||
@ -269,7 +269,7 @@
|
||||
sd-uhs-sdr50;
|
||||
};
|
||||
|
||||
emmc: sdhc@5a500000 {
|
||||
emmc: mmc@5a500000 {
|
||||
compatible = "socionext,uniphier-sd-v2.91";
|
||||
status = "disabled";
|
||||
reg = <0x5a500000 0x200>;
|
||||
@ -379,7 +379,7 @@
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
aidet: aidet@61830000 {
|
||||
aidet: interrupt-controller@61830000 {
|
||||
compatible = "socionext,uniphier-sld8-aidet";
|
||||
reg = <0x61830000 0x200>;
|
||||
interrupt-controller;
|
||||
@ -402,7 +402,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
nand: nand@68000000 {
|
||||
nand: nand-controller@68000000 {
|
||||
compatible = "socionext,uniphier-denali-nand-v5a";
|
||||
status = "disabled";
|
||||
reg-names = "nand_data", "denali_reg";
|
||||
@ -412,7 +412,8 @@
|
||||
pinctrl-0 = <&pinctrl_nand2cs>;
|
||||
clock-names = "nand", "nand_x", "ecc";
|
||||
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
|
||||
resets = <&sys_rst 2>;
|
||||
reset-names = "nand", "reg";
|
||||
resets = <&sys_rst 2>, <&sys_rst 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -22,6 +22,7 @@ endif
|
||||
obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o
|
||||
obj-y += pinctrl-glue.o
|
||||
obj-$(CONFIG_MMC) += mmc-first-dev.o
|
||||
obj-$(CONFIG_NAND_DENALI) += nand-reset.o
|
||||
obj-y += fdt-fixup.o
|
||||
|
||||
endif
|
||||
|
||||
@ -141,6 +141,10 @@ int board_init(void)
|
||||
|
||||
support_card_late_init();
|
||||
|
||||
led_puts("U4");
|
||||
|
||||
uniphier_nand_reset_assert();
|
||||
|
||||
led_puts("Uboo");
|
||||
|
||||
return 0;
|
||||
|
||||
@ -14,25 +14,9 @@
|
||||
#include <stdio.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/printk.h>
|
||||
#include <../drivers/mtd/nand/raw/denali.h>
|
||||
|
||||
#include "init.h"
|
||||
|
||||
static void nand_denali_wp_disable(void)
|
||||
{
|
||||
#ifdef CONFIG_NAND_DENALI
|
||||
/*
|
||||
* Since the boot rom enables the write protection for NAND boot mode,
|
||||
* it must be disabled somewhere for "nand write", "nand erase", etc.
|
||||
* The workaround is here to not disturb the Denali NAND controller
|
||||
* driver just for a really SoC-specific thing.
|
||||
*/
|
||||
void __iomem *denali_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
|
||||
|
||||
writel(WRITE_PROTECT__FLAG, denali_reg + WRITE_PROTECT);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void uniphier_set_env_fdt_file(void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
@ -114,7 +98,6 @@ int board_late_init(void)
|
||||
case BOOT_DEVICE_NAND:
|
||||
printf("NAND Boot");
|
||||
env_set("bootdev", "nand");
|
||||
nand_denali_wp_disable();
|
||||
break;
|
||||
case BOOT_DEVICE_NOR:
|
||||
printf("NOR Boot");
|
||||
|
||||
@ -15,13 +15,6 @@ void uniphier_ld4_early_clk_init(void)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
/* deassert reset */
|
||||
if (spl_boot_device() != BOOT_DEVICE_NAND) {
|
||||
tmp = readl(sc_base + SC_RSTCTRL);
|
||||
tmp &= ~SC_RSTCTRL_NRST_NAND;
|
||||
writel(tmp, sc_base + SC_RSTCTRL);
|
||||
};
|
||||
|
||||
/* provide clocks */
|
||||
tmp = readl(sc_base + SC_CLKCTRL);
|
||||
tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
|
||||
|
||||
@ -101,6 +101,14 @@ unsigned int uniphier_boot_device_raw(void);
|
||||
int uniphier_have_internal_stm(void);
|
||||
int uniphier_boot_from_backend(void);
|
||||
int uniphier_pin_init(const char *pinconfig_name);
|
||||
|
||||
#ifdef CONFIG_NAND_DENALI
|
||||
void uniphier_nand_reset_assert(void);
|
||||
#else
|
||||
static inline void uniphier_nand_reset_assert(void)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_ARM64
|
||||
void uniphier_mem_map_init(unsigned long dram_base, unsigned long dram_size);
|
||||
#else
|
||||
|
||||
@ -1,39 +1,58 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2012-2015 Panasonic Corporation
|
||||
* Copyright (C) 2015-2016 Socionext Inc.
|
||||
* Copyright (C) 2015-2020 Socionext Inc.
|
||||
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm/of.h>
|
||||
#include <fdt_support.h>
|
||||
#include <linux/ctype.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include "micro-support-card.h"
|
||||
|
||||
#define MICRO_SUPPORT_CARD_BASE 0x43f00000
|
||||
#define SMC911X_BASE ((MICRO_SUPPORT_CARD_BASE) + 0x00000)
|
||||
#define LED_BASE ((MICRO_SUPPORT_CARD_BASE) + 0x90000)
|
||||
#define NS16550A_BASE ((MICRO_SUPPORT_CARD_BASE) + 0xb0000)
|
||||
#define MICRO_SUPPORT_CARD_RESET ((MICRO_SUPPORT_CARD_BASE) + 0xd0034)
|
||||
#define MICRO_SUPPORT_CARD_REVISION ((MICRO_SUPPORT_CARD_BASE) + 0xd00E0)
|
||||
#define SMC911X_OFFSET 0x00000
|
||||
#define LED_OFFSET 0x90000
|
||||
#define NS16550A_OFFSET 0xb0000
|
||||
#define MICRO_SUPPORT_CARD_RESET 0xd0034
|
||||
#define MICRO_SUPPORT_CARD_REVISION 0xd00e0
|
||||
|
||||
static bool support_card_found;
|
||||
static void __iomem *support_card_base;
|
||||
|
||||
static void support_card_detect(void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
const void *fdt = gd->fdt_blob;
|
||||
int offset;
|
||||
u64 addr, addr2;
|
||||
|
||||
offset = fdt_node_offset_by_compatible(fdt, 0, "smsc,lan9118");
|
||||
if (offset < 0)
|
||||
return;
|
||||
|
||||
addr = fdt_get_base_address(fdt, offset);
|
||||
if (addr == OF_BAD_ADDR)
|
||||
return;
|
||||
addr -= SMC911X_OFFSET;
|
||||
|
||||
offset = fdt_node_offset_by_compatible(fdt, 0, "ns16550a");
|
||||
if (offset < 0)
|
||||
return;
|
||||
|
||||
addr2 = fdt_get_base_address(fdt, offset);
|
||||
if (addr2 == OF_BAD_ADDR)
|
||||
return;
|
||||
addr2 -= NS16550A_OFFSET;
|
||||
|
||||
/* sanity check */
|
||||
if (addr != addr2)
|
||||
return;
|
||||
|
||||
support_card_base = ioremap(addr, 0x100000);
|
||||
|
||||
support_card_found = true;
|
||||
}
|
||||
|
||||
@ -45,19 +64,19 @@ static void support_card_detect(void)
|
||||
*/
|
||||
static void support_card_reset_deassert(void)
|
||||
{
|
||||
writel(0x00010000, MICRO_SUPPORT_CARD_RESET);
|
||||
writel(0x00010000, support_card_base + MICRO_SUPPORT_CARD_RESET);
|
||||
}
|
||||
|
||||
static void support_card_reset(void)
|
||||
{
|
||||
writel(0x00020003, MICRO_SUPPORT_CARD_RESET);
|
||||
writel(0x00020003, support_card_base + MICRO_SUPPORT_CARD_RESET);
|
||||
}
|
||||
|
||||
static int support_card_show_revision(void)
|
||||
{
|
||||
u32 revision;
|
||||
|
||||
revision = readl(MICRO_SUPPORT_CARD_REVISION);
|
||||
revision = readl(support_card_base + MICRO_SUPPORT_CARD_REVISION);
|
||||
revision &= 0xff;
|
||||
|
||||
/* revision 3.6.x card changed the revision format */
|
||||
@ -94,7 +113,7 @@ int board_eth_init(bd_t *bis)
|
||||
if (!support_card_found)
|
||||
return 0;
|
||||
|
||||
return smc911x_initialize(0, SMC911X_BASE);
|
||||
return smc911x_initialize(0, (unsigned long)support_card_base + SMC911X_OFFSET);
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -264,5 +283,5 @@ void led_puts(const char *s)
|
||||
s++;
|
||||
}
|
||||
|
||||
writel(~val, LED_BASE);
|
||||
writel(~val, support_card_base + LED_OFFSET);
|
||||
}
|
||||
|
||||
@ -9,13 +9,14 @@
|
||||
#include <mmc.h>
|
||||
#include <linux/errno.h>
|
||||
|
||||
static int find_first_mmc_device(void)
|
||||
static int find_first_mmc_device(bool is_sd)
|
||||
{
|
||||
struct mmc *mmc;
|
||||
int i;
|
||||
|
||||
for (i = 0; (mmc = find_mmc_device(i)); i++) {
|
||||
if (!mmc_init(mmc) && IS_MMC(mmc))
|
||||
if (!mmc_init(mmc) &&
|
||||
((is_sd && IS_SD(mmc)) || (!is_sd && IS_MMC(mmc))))
|
||||
return i;
|
||||
}
|
||||
|
||||
@ -24,14 +25,14 @@ static int find_first_mmc_device(void)
|
||||
|
||||
int mmc_get_env_dev(void)
|
||||
{
|
||||
return find_first_mmc_device();
|
||||
return find_first_mmc_device(false);
|
||||
}
|
||||
|
||||
static int do_mmcsetn(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
int dev;
|
||||
|
||||
dev = find_first_mmc_device();
|
||||
dev = find_first_mmc_device(false);
|
||||
if (dev < 0)
|
||||
return CMD_RET_FAILURE;
|
||||
|
||||
@ -44,3 +45,21 @@ U_BOOT_CMD(
|
||||
"Set the first MMC (not SD) dev number to \"mmc_first_dev\" environment",
|
||||
""
|
||||
);
|
||||
|
||||
static int do_sdsetn(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
int dev;
|
||||
|
||||
dev = find_first_mmc_device(true);
|
||||
if (dev < 0)
|
||||
return CMD_RET_FAILURE;
|
||||
|
||||
env_set_ulong("sd_first_dev", dev);
|
||||
return CMD_RET_SUCCESS;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
sdsetn, 1, 1, do_sdsetn,
|
||||
"Set the first SD dev number to \"sd_first_dev\" environment",
|
||||
""
|
||||
);
|
||||
|
||||
43
arch/arm/mach-uniphier/nand-reset.c
Normal file
43
arch/arm/mach-uniphier/nand-reset.c
Normal file
@ -0,0 +1,43 @@
|
||||
// SPDX-License-Identifier: GPL-2.0 or later
|
||||
/*
|
||||
* Copyright (C) 2020 Socionext Inc.
|
||||
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
*/
|
||||
|
||||
#include <linux/errno.h>
|
||||
#include <dm.h>
|
||||
#include <dm/uclass-internal.h>
|
||||
#include <reset.h>
|
||||
|
||||
#include "init.h"
|
||||
|
||||
/*
|
||||
* Assert the Denali NAND controller reset if found.
|
||||
*
|
||||
* On LD4, the bootstrap process starts running after power-on reset regardless
|
||||
* of the boot mode, here the pin-mux is not necessarily set up for NAND, then
|
||||
* the controller is stuck. Assert the controller reset here, and should be
|
||||
* deasserted in the driver after the pin-mux is correctly handled. For other
|
||||
* SoCs, the bootstrap runs only when the boot mode selects ONFi, but it is yet
|
||||
* effective when the boot swap is on. So, the reset should be asserted anyway.
|
||||
*/
|
||||
void uniphier_nand_reset_assert(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
struct reset_ctl_bulk resets;
|
||||
int ret;
|
||||
|
||||
ret = uclass_find_first_device(UCLASS_MTD, &dev);
|
||||
if (ret || !dev)
|
||||
return;
|
||||
|
||||
/* make sure this is the Denali NAND controller */
|
||||
if (strcmp(dev->driver->name, "denali-nand-dt"))
|
||||
return;
|
||||
|
||||
ret = reset_get_bulk(dev, &resets);
|
||||
if (ret)
|
||||
return;
|
||||
|
||||
reset_assert_bulk(&resets);
|
||||
}
|
||||
@ -39,10 +39,10 @@ CONFIG_I2C_EEPROM=y
|
||||
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
|
||||
CONFIG_SUPPORT_EMMC_RPMB=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_MMC_HS200_SUPPORT=y
|
||||
CONFIG_MMC_HS400_SUPPORT=y
|
||||
CONFIG_MMC_UNIPHIER=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ADMA=y
|
||||
CONFIG_MMC_SDHCI_CADENCE=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
|
||||
@ -160,6 +160,7 @@
|
||||
"emmcboot=mmcsetn && run bootcmd_mmc${mmc_first_dev}\0" \
|
||||
"nandboot=run bootcmd_ubifs0\0" \
|
||||
"norboot=run tftpboot\0" \
|
||||
"sdboot=sdsetn && run bootcmd_mmc${sd_first_dev}\0" \
|
||||
"usbboot=run bootcmd_usb0\0" \
|
||||
"emmcscript=setenv devtype mmc && " \
|
||||
"mmcsetn && " \
|
||||
@ -170,6 +171,10 @@
|
||||
"ubifsmount ubi0:boot && " \
|
||||
"ubifsload ${loadaddr} ${script} && " \
|
||||
"source $loadaddr\0" \
|
||||
"sdscript=setenv devtype mmc && " \
|
||||
"sdsetn && " \
|
||||
"setenv devnum ${sd_first_dev} && " \
|
||||
"run loadscript_fat\0" \
|
||||
"norscript=echo Running ${script} from tftp ... && " \
|
||||
"tftpboot ${script} &&" \
|
||||
"source $loadaddr\0" \
|
||||
@ -196,6 +201,12 @@
|
||||
"nand write $loadaddr 0 0x00020000 && " \
|
||||
"tftpboot $third_image && " \
|
||||
"nand write $loadaddr 0x00020000 0x001e0000\0" \
|
||||
"sdupdate=sdsetn &&" \
|
||||
"mmc dev $sd_first_dev &&" \
|
||||
"tftpboot $second_image && " \
|
||||
"mmc write $loadaddr 0 100 && " \
|
||||
"tftpboot $third_image && " \
|
||||
"mmc write $loadaddr 100 f00\0" \
|
||||
"usbupdate=usb start &&" \
|
||||
"tftpboot $second_image && " \
|
||||
"usb write $loadaddr 0 100 && " \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user