tegra: clock: Avoid a divide-by-zero error

The clock fix-up for tegra is still present in the code. It causes a
divide-by-zero bug after relocation when chain-loading U-Boot from
coreboot. Fix this by adding a check.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 7468676 (ARM: tegra: fix clock_get_periph_rate() for UART clocks)
This commit is contained in:
Simon Glass 2017-05-31 17:57:22 -06:00
parent 06cc85a29a
commit 1c6c7b6bd8

View File

@ -339,8 +339,11 @@ unsigned long clock_get_periph_rate(enum periph_id periph_id,
* return value doesn't help. In summary this clock driver is
* quite broken but I'm afraid I have no idea how to fix it
* without completely replacing it.
*
* Be careful to avoid a divide by zero error.
*/
div -= 2;
if (div >= 1)
div -= 2;
break;
#endif
default: