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arm: zynq: zybo z7: fix SPL uart init bitrate

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The board uses 100 MHz clock for UART bitrate generator,
but is configured as 50 MHz on defconfig.

This produces wrong console output.
The first message, "Debug uart enabled" is received as:
"������b"

Fix the issue by configuring the correct clock for the
UART baudrate generator

Signed-off-by: Milan Obuch <u-boot@dino.sk>
Signed-off-by: Luis Araneda <luaraneda@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Milan Obuch 2020-01-19 22:32:19 -03:00 committed by Michal Simek
parent 1a4bf17b02
commit 1bf9e01b8f
1 changed files with 1 additions and 1 deletions
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2
configs/zynq_zybo_z7_defconfig
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@ -6,7 +6,7 @@ CONFIG_DM_GPIO=y
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xe0001000
CONFIG_DEBUG_UART_CLOCK=50000000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y