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arm: dts: k3-j721e-main: Add C71x DSP node
The J721E SoCs have a single TMS320C71x DSP Subsystem in the MAIN voltage domain containing the next-generation C711 CPU core. The subsystem has 32 KB of L1D configurable SRAM/Cache and 512 KB of L2 configurable SRAM/Cache. This subsystem has a CMMU but is not used currently. The inter-processor communication between the main A72 cores and the C711 processor is achieved through shared memory and a Mailbox. Add the DT node for this DSP processor sub-system in the common k3-j721e-main.dtsi file. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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@ -22,6 +22,7 @@
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remoteproc5 = &main_r5fss1_core1;
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remoteproc5 = &main_r5fss1_core1;
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remoteproc6 = &c66_0;
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remoteproc6 = &c66_0;
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remoteproc7 = &c66_1;
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remoteproc7 = &c66_1;
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remoteproc8 = &c71_0;
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};
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};
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};
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};
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@ -328,4 +328,15 @@
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ti,sci-proc-ids = <0x04 0xFF>;
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ti,sci-proc-ids = <0x04 0xFF>;
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resets = <&k3_reset 143 1>;
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resets = <&k3_reset 143 1>;
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};
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};
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c71_0: dsp@64800000 {
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compatible = "ti,j721e-c71-dsp";
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reg = <0x00 0x64800000 0x00 0x00080000>,
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<0x00 0x64e00000 0x00 0x0000c000>;
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reg-names = "l2sram", "l1dram";
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <15>;
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ti,sci-proc-ids = <0x30 0xFF>;
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resets = <&k3_reset 15 1>;
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};
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};
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};
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